[all-commits] [llvm/llvm-project] 82ea1d: [RegAlloc] [X86] Enable callee saved register opti...

[weiguozhi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82ea1d26eca4bb8d12513d29a71536c35f3ff47b
      https://github.com/llvm/llvm-project/commit/82ea1d26eca4bb8d12513d29a71536c35f3ff47b
  Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M clang/test/Frontend/stack-layout-remark.c
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/test/CodeGen/MLRegAlloc/interactive-mode.ll
    M llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll
    M llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
    M llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
    M llvm/test/CodeGen/X86/apx/memfold-origVNI-crash.ll
    M llvm/test/CodeGen/X86/apx/pr191368.ll
    M llvm/test/CodeGen/X86/atom-fixup-lea2.ll
    M llvm/test/CodeGen/X86/block-placement.ll
    M llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
    M llvm/test/CodeGen/X86/fptosi-sat-scalar-f16.ll
    M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/X86/fptoui-sat-scalar.ll
    M llvm/test/CodeGen/X86/indirect-branch-tracking-eh.ll
    M llvm/test/CodeGen/X86/no-split-size.ll
    M llvm/test/CodeGen/X86/ragreedy-bug.ll
    M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
    M llvm/test/CodeGen/X86/sjlj-eh.ll
    M llvm/test/CodeGen/X86/speculative-load-hardening.ll
    M llvm/test/CodeGen/X86/split-reg-with-hint.ll
    M llvm/test/CodeGen/X86/statepoint-vreg-details.ll
    M llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
    M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
    M llvm/test/CodeGen/X86/tail-opts.ll
    M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll

  Log Message:
  -----------
  [RegAlloc] [X86] Enable callee saved register optimization for x86 (#220090)

Enable callee saved register optimization implemented in
RAGreedy::tryAssignCSRFirstTime() for x86. It can replace save/restore
instructions in prologue/epilogue with register spill/reload in cold
blocks or register splits.

Spec cpu 2006 int result with fdo on skylake.
```
regalloc-csr-cost-scale                                 0     30

400.perlbench                                          42.0  42.7   
401.bzip2                                              25.5  26.3   
403.gcc                                                42.1  41.4   
429.mcf                                                45.0  44.4   
456.hmmer                                              38.2  38.2   
458.sjeng                                              32.3  32.0   
462.libquantum                                         68.0  68.9   
471.omnetpp                                            26.9  27.3   
473.astar                                              24.3  24.1  
```
445.gobmk, 464.h264ref and 483.xalancbmk didn't work with my base
compiler.

This PR is split from https://github.com/llvm/llvm-project/pull/188609.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications