[all-commits] [llvm/llvm-project] 517363: [Sparc][clang] Use 64-bit long double on bare-meta...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Tue Sep 22 11:41:16 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpdrop-unprofitable-splat-subtrees-before-the-profitability-trim
Home: https://github.com/llvm/llvm-project
Commit: 5173637372a272790125e6af71576c6607adfef8
https://github.com/llvm/llvm-project/commit/5173637372a272790125e6af71576c6607adfef8
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/CodeGen/Targets/Sparc.cpp
A clang/test/CodeGen/Sparc/sparc-long-double-abi.c
M clang/test/CodeGen/Sparc/sparc-vaarg.c
M clang/test/CodeGen/Sparc/sparcv8-abi.c
M clang/test/CodeGen/Sparc/variadic-aggregate.c
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-arch-macros.c
M llvm/lib/TargetParser/Triple.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[Sparc][clang] Use 64-bit long double on bare-metal targets (#222304)
GCC uses 64-bit long double for bare-metal SPARC V8 targets, including
RTEMS. Keep the default 128-bit for other SPARC targets.
Use the scalar calling convention for 64-bit long double.
Assisted-by: Codex
Commit: 4e22f745681e8dfb30c4feb0b26d3459bf1ff123
https://github.com/llvm/llvm-project/commit/4e22f745681e8dfb30c4feb0b26d3459bf1ff123
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/IR/PassManager.cpp
Log Message:
-----------
[NewPM] Fix OptBisect Functionality for disabled gate
We were never actually checking if the gate was enabled. This patch
fixes it to match the behavior of the LegacyPM.
Reviewers: aeubanks
Pull Request: https://github.com/llvm/llvm-project/pull/225437
Commit: dcdbda6493bc818580299516fb87ee03e879fb2a
https://github.com/llvm/llvm-project/commit/dcdbda6493bc818580299516fb87ee03e879fb2a
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyPostLegalizerCombiner.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyPreLegalizerCombiner.cpp
M llvm/lib/Target/X86/GISel/X86PreLegalizerCombiner.cpp
M llvm/test/CodeGen/X86/replace_unsupported_masked_mem_intrin.ll
M llvm/test/Other/X86/opt-bisect-isel.ll
Log Message:
-----------
[NewPM] Match LegacyPM behavior for opt-bisect in passes
This patch updates passes that change their behavior around opt-bisect
(e.g., performing less optimizations) so that this behavior is
replicated in the NewPM.
Assisted by LLM.
Reviewers: aeubanks, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/225439
Commit: 9a7a665cbe2a9e59403bcfb59ac6c1294370e8ee
https://github.com/llvm/llvm-project/commit/9a7a665cbe2a9e59403bcfb59ac6c1294370e8ee
Author: A. Cauble <accauble at users.noreply.github.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M clang/tools/offload-arch/AMDGPUArchByKFD.cpp
M clang/unittests/offload-arch/OffloadArchTest.cpp
Log Message:
-----------
[offload-arch] Do not print "-strict" if it is disabled by the environment (#224688)
## Motivation
Right now, `HSA_DISABLE_GFX12_STRICT` is set to 1 by default, which the
runtime follows as "gfx1250". The only way to set the runtime to
"gfx1250-strict" is to set `HSA_DISABLE_GFX12_STRICT=0`. My
understanding is that this is a temporary patch to ROCr to ease the
transition to "gfx1250-strict". This PR adds a helper to reflect the
current state.
[This is how
ROCr](https://github.com/ROCm/rocm-systems/blob/28d10d31fcb04d53dedee5c6e66427f0b0449a9e/projects/rocr-runtime/runtime/hsa-runtime/core/util/flag.h#L256)
controls "strict". The very similar rocm_agent_enumerator code can be
found
[here](https://github.com/ROCm/rocm-systems/blob/855ab23c50ee8635e6c068fc3f9ec2eb01f075e0/projects/rocminfo/rocm_agent_enumerator#L270-L273).
## Testing
* Updated the unit tests to keep track of the environment variable and
to check for the expected value depending on it.
Commit: b5dfb7423c6aae8c3a133b08f43e8094b9da2cf3
https://github.com/llvm/llvm-project/commit/b5dfb7423c6aae8c3a133b08f43e8094b9da2cf3
Author: Tadeusz <tadeuszjt at protonmail.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Support/KnownFPClass.cpp
M llvm/test/Transforms/Attributor/nofpclass-sin-cos.ll
M llvm/test/Transforms/Attributor/nofpclass-trig.ll
Log Message:
-----------
[KnownFPClass] Added sNaN deductions for sin, cos and tan. (#224875)
Added the sNaN deductions for sin, cos and tan to KnownFPClass.
Closes #217150
Commit: c96cbf32ba13d3abafea5839ae163407f00986b1
https://github.com/llvm/llvm-project/commit/c96cbf32ba13d3abafea5839ae163407f00986b1
Author: laoshd <shandong.lao at hpe.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/depend01.f90
Log Message:
-----------
[Flang][OpenMP] Add diagnosing zero-length depend array sections and … (#224168)
…tests.
This PR is to fix #222551.
Commit: c6de8f77f1b7ee3ea29da92330fa0e4262f3e7c1
https://github.com/llvm/llvm-project/commit/c6de8f77f1b7ee3ea29da92330fa0e4262f3e7c1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M .github/workflows/containers/libc/Dockerfile
Log Message:
-----------
[Github] Disable bootstrap when building gcc for libc container
We don't need the additional testing from a full bootstrap and the
default system gcc probably produces faster binaries.
This should make the container build a bit faster.
Reviewers: lntue, cmtice
Pull Request: https://github.com/llvm/llvm-project/pull/225453
Commit: 16c9544c26f863bd83538e66e0f09af4b2f4dbd1
https://github.com/llvm/llvm-project/commit/16c9544c26f863bd83538e66e0f09af4b2f4dbd1
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M .github/workflows/containers/libc/Dockerfile
Log Message:
-----------
[Github] Fix /usr/include/asm symlink in libc container
The move to ubuntu 26.04 meant that we are now using rust based
coreutils, and the behavior of uname -p changed to return unknown in the
rust coreutils. So instead use uname -m so that the symlink points at
the right directory.
Reviewers: cmtice, lntue
Pull Request: https://github.com/llvm/llvm-project/pull/225454
Commit: ddc63f8a20b63f2cf76299d73ab5c99c73144374
https://github.com/llvm/llvm-project/commit/ddc63f8a20b63f2cf76299d73ab5c99c73144374
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fminnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fadd.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fmul.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fsub.bf16.ll
Log Message:
-----------
[AMDGPU][GISel] Legalize v2bf16 (#223803)
Add V2BF16 legalization for fadd, fsub, fmul, fma, fmin, fmax and
fcanonicalize.
Reorganize rule building for `MinNumMaxNumIeee` and `MinNumMaxNum` so
that each type is handled independently.
Updated old tests and added new tests GlobalISel/fsub.bf16.ll,
GlobalISel/fabs.bf16.ll, GlobalISel/fminnum.bf16.ll and
GlobalISel/fneg.bf16.ll.
Clamp bf16 to 2 elements.
Test with v4bf16.
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: ae5117cb45b860bf473337523d7fe4a6367dd8d1
https://github.com/llvm/llvm-project/commit/ae5117cb45b860bf473337523d7fe4a6367dd8d1
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M libc/lib/CMakeLists.txt
Log Message:
-----------
[libc] Generate a stub for librt.a (#225357)
Created an empty librt.a static archive on Linux to avoid link errors
when build rules explicitly pass -lrt to the linker. Realtime extensions
reside in the main libc.a archive instead.
Follows the pattern set in commit
ede01decbcb34bd2f04b9102ab96664cc6d5aa4b.
Assisted-by: Automated tooling, human reviewed.
Commit: e4657c791d32993f2253f51f1d1427b72ed39651
https://github.com/llvm/llvm-project/commit/e4657c791d32993f2253f51f1d1427b72ed39651
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[VPlan] Add getRecordedExecutionFrequency helper (NFC). (#225414)
Add a helper to get the execution frequency from a VPBB via the
frequencies attached to its recipes.
Will also be used in https://github.com/llvm/llvm-project/pull/196845,
so it is added in a location where it can be used w/o movement there.
PR: https://github.com/llvm/llvm-project/pull/225414
Commit: 19c33fb826ed11652280fa0a4161675963d09991
https://github.com/llvm/llvm-project/commit/19c33fb826ed11652280fa0a4161675963d09991
Author: Kunal Chadha <kunachad at qti.qualcomm.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
Log Message:
-----------
[AArch64] Override hasSideEffects for LDAR/STLR instructions (#224096)
Override `hasSideEffects()` for `LoadAcquire` and `StoreRelease`.
`LoadAcquire` and `StoreRelease` already have their memory ordering
semantics modeled via atomic MMO flags, so they should not additionally
be marked as having unmodeled side effects.
Marking these instructions as having unmodeled side effects caused
`ShrinkWrap::useOrDefCSROrFI()` to conservatively treat basic blocks
containing them as potentially using the stack. This prevented
ShrinkWrap optimizations such as splitting restore points during
post-shrink-wrapping. The tests added in this PR cover this case.
Updated llvm-mca expectations for the affected instructions.
Fixes #223021
Commit: aa7a0c3c318b8391c61fba9dcbb98e08c85d5776
https://github.com/llvm/llvm-project/commit/aa7a0c3c318b8391c61fba9dcbb98e08c85d5776
Author: Ganesh <Ganesh.Gopalasubramanian at amd.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/SemaX86.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10v2aux_512intrin.h
A clang/lib/Headers/avx10v2auxintrin.h
M clang/lib/Headers/cpuid.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/X86/avx10_2_v2aux-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/CodeGen/builtin-cpu-supports-all.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/attr-target-mv.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp4-fp6-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp8-ps-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-mask-bias-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-mask-cvt-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-pmovssdb-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-unpackb-intrinsics.ll
A llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
A llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
A llvm/test/MC/X86/avx10_v2_aux-att-32.s
A llvm/test/MC/X86/avx10_v2_aux-att-64.s
A llvm/test/MC/X86/avx10_v2_aux-intel-32.s
A llvm/test/MC/X86/avx10_v2_aux-intel-64.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/utils/TableGen/X86ManualFoldTables.def
Log Message:
-----------
[X86] AVX10_V2_AUX Implementation (#206888)
- AVX10_V2_AUX builds on AVX10 with FP8/FP4/FP6 format conversions
optimized for AI/ML inference workloads, enabling efficient
low-precision arithmetic
- Narrowing conversions from single-precision to FP8: VCVTPS2BF8,
VCVTPS2HF8, VCVTPS2BF8S, VCVTPS2HF8S with optional saturation, biasing
(VCVTBIASPS2BF8/HF8), and round-to-odd (VCVTROPS2HF8) variants
- Expanding conversions from FP8 to single-precision: VCVTBF82PS,
VCVTHF82PS that widen 8-bit FP formats with masking support
- FP4/FP6 conversions: VCVTBF82BF4S, VCVTHF82BF4S for truncating,
VCVTBF82BF6S, VCVTHF82HF6S for same-size, and expanding VCVTBF42HF8,
VCVTBF62BF8, VCVTHF62HF8
- Support includes instruction definitions, intrinsics, and Clang
headers
- Tests covering AT&T and Intel syntax assembly for both 32-bit and
64-bit modes, plus disassembler tests verifying encoding and decoding
Specification: [ACE (AI Compute Extensions) Specification
v1.0](https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf)
Co-authored-by: Umesh Kalvakuntla
Co-authored-by: Attarde, Mahesh <mahesh.attarde at intel.com>
Commit: 340b35cd504e01e4eeff0381bd5eb317dfb7f504
https://github.com/llvm/llvm-project/commit/340b35cd504e01e4eeff0381bd5eb317dfb7f504
Author: yebinchon <yebin.chon at princeton.edu>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.h
M flang/lib/Optimizer/Dialect/CUF/Attributes/CUFAttr.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
A flang/test/Transforms/OpenACC/acc-implicit-data-device-data.fir
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsTest.cpp
Log Message:
-----------
[flang][acc] Don't treat a managed pointer as device resident data (#222769)
isDeviceData classifies every entity with a device-data CUDA attribute
(device, managed, constant, shared, unified) as device data, and so all
pointers and allocatables under mem:managed/unified are treated as
deviceptr.
However, managed and unified guarantee accessibility from device but not
that the storage is already residing on device. Treating these
unconditionally as "on device" (deviceptr) asserts to the runtime that
it is a valid device address and skips the mapping/attach the runtime
needs.
This patch adds a Util helper "isDeviceResident" which conservatively
returns false for managed/unified.
The guard for deviceptr is changed from isDeviceValue to
isDeviceResident, and does NOT give deviceptr for managed and unified.
These entities are now mapped (copyin/out) instead.
---------
Co-authored-by: Yebin Chon <ychon at nvidia.com>
Commit: 747cf241988e83e9ab4aae88efc10d91e87a0b90
https://github.com/llvm/llvm-project/commit/747cf241988e83e9ab4aae88efc10d91e87a0b90
Author: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Rework legacy widen/replicate in tryToBuildVPlan (NFC) (#224569)
The code has been rewritten for clarity:
- An RPOT traversal is unnecessary, and a depth-first will do.
- The list of recipes to be skipped continues to grow, and its utility
is in question. Replace it with a clean make_isa_range over
VPInstructions, and an assert.
- Clarify that tryToCreateWidenNonPhiRecipe is the routine that produces
VPWidenIntOrFpInductionRecipes.
- Clarify the necessity of the underling value.
Commit: 2643205b93aa72864b2ac0cd0ae8047bc8048baf
https://github.com/llvm/llvm-project/commit/2643205b93aa72864b2ac0cd0ae8047bc8048baf
Author: Nathan Fusselman <nathanfusselman at icloud.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/evaluate/main.cpp
M lldb/tools/lldb-dap/DAP.cpp
Log Message:
-----------
[lldb-dap] Fix global-scope evaluate always routing to command interpreter (#225243)
DetectReplMode returned Command unconditionally when there was no frame,
since it couldn't check FindVariable without one. A frameless evaluate
(no frameId, e.g. `(int)getpid()`) was always treated as an unknown
command instead of an expression.
Fall back to SBTarget::FindFirstGlobalVariable when there's no frame:
DAP::target is valid independent of frame, so globals/statics can still
be checked without one.
rdar://187884135
Commit: 81a680b6c7aec6fc493fb978ad1902b648781170
https://github.com/llvm/llvm-project/commit/81a680b6c7aec6fc493fb978ad1902b648781170
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M clang/include/clang/AST/DeclFriend.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#225319)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
We must use dyn_cast_if_present here because the operands can be null,
which I have verified with assert(!isNull()) on check-clang.
Assisted-by: Antigravity
Commit: fdf4dcb7b7ddb33e5f4c9ab7fad0fca2e0170daa
https://github.com/llvm/llvm-project/commit/fdf4dcb7b7ddb33e5f4c9ab7fad0fca2e0170daa
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
A llvm/test/CodeGen/NVPTX/infer-address-space-join.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/address-space-join.ll
Log Message:
-----------
[InferAddressSpaces] Add a TTI hook for address space joins (#225161)
InferAddressSpaces currently joins different specific address spaces to
the flat address space. This misses cases where the target has a more
specific common space. For NVPTX, a PHI or select combining shared (AS3)
and cluster-shared (AS7) pointers can use AS7, allowing loads through
the result to use ld.shared::cluster.
Add a getAddressSpaceJoin TTI hook and implement the AS3/AS7 join for
NVPTX.
Commit: efa2e450edc341bac7a5215f408f4d1480047c8c
https://github.com/llvm/llvm-project/commit/efa2e450edc341bac7a5215f408f4d1480047c8c
Author: eleviant <eleviant at accesssoftek.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrControl.td
A llvm/test/CodeGen/X86/pseudo-expand-tc.mir
Log Message:
-----------
[X86] Fix operand of TAILJMPm64_REX (#225080)
The TAILJMPm64_REX pseudo-instruction is emitted by the
x86-expand-pseudo pass after the register allocator, replacing
TCRETURN_WINmi64 or TCRETURNmi64 depending on the target ABI. The
problem is that the former uses the GR64_TC register class for its
memory address operand, while the latter uses GR64_TCW64. This breaks
MachineVerifier, triggering an assertion in EXPENSIVE_CHECKS builds.
Commit: df6eb20ffd22156a6d4fd54e36146d430c8a182a
https://github.com/llvm/llvm-project/commit/df6eb20ffd22156a6d4fd54e36146d430c8a182a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
Log Message:
-----------
[mlir][SPIR-V] Verify NonPrivatePointer requirement for MakePointer{Available,Visible} (#213621)
close #145485
Commit: f05f4f34e5cb107e17672ad806f18d031ab74caf
https://github.com/llvm/llvm-project/commit/f05f4f34e5cb107e17672ad806f18d031ab74caf
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll
Log Message:
-----------
[VPlan] Model epilogue skeleton in VPlan by wrapping in VPIRBBs (NFCI). (#222312)
Replace most of connectEpilogueVectorLoop by modeling the CFG explicitly
in the epilogue VPlan, by importing the CFG for the skeleton created
after executing the main loop.
To do so, update the main loop's plan to replace its VPBasicBlocks with
VPIRBasicBlocks wrapping the generated IR blocks. This allows accessing
the CFG for the VPlan, after execute.
A new modelGeneratedMainLoopBlocks transform then duplicates the CFG
from the main plan in the epilogue plan. This includes all runtime
checks and bypass blocks. This means we no longer need a number of
manual patching up of the IR and DT to connect main and epilogue plans
after execute.
It is another step getting us slightly closer to completely modeling
epilogue vectorization natively in VPlan.
Along the way, it will also help to simplify code needed to perform
folds on the epilogue skeleton (i.e. simplify
https://github.com/llvm/llvm-project/pull/204243).
PR: https://github.com/llvm/llvm-project/pull/222312
Commit: 746076bccd5fa18c09a29107eef5c101ea0e2674
https://github.com/llvm/llvm-project/commit/746076bccd5fa18c09a29107eef5c101ea0e2674
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/X86/vselect-widen-mask-tree.ll
Log Message:
-----------
[SelectionDAG] Fix crash in mask widening for non-simple element types (#225460)
We reconstruct the best fitting type for the two given operands and
those are not guaranteed to have simple types. EVT::getIntegerVT as
opposed to MVT::getIntegerVT handles this case.
Fixes a regression introduced in #217307.
Commit: 8045e64d0e80712952b5820564aa57fbbb42fbda
https://github.com/llvm/llvm-project/commit/8045e64d0e80712952b5820564aa57fbbb42fbda
Author: Christopher Ferris <cferris1000 at users.noreply.github.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
Log Message:
-----------
[scudo] Skip secondary release if interval greater than current time. (#225242)
If the current time is less than the release interval, the call to
releaseOlderThan wraps around and releases all entries. Skip releasing
when detecting this case.
Commit: 5ae71ec799917c67e9e72510e68831602fc60699
https://github.com/llvm/llvm-project/commit/5ae71ec799917c67e9e72510e68831602fc60699
Author: Keith Smiley <keithbsmiley at gmail.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M .github/workflows/release-binaries.yml
M clang/cmake/caches/Release.cmake
M llvm/cmake/modules/FindLibXml2.cmake
Log Message:
-----------
[cmake] Build libxml from source in release (#221365)
With 23.x we started linking a static libxml in release builds to avoid
requiring that to be installed, and the varying names of that library on
different linux distros. That broke more than it fixed because the
static libxml in our docker images are built targeting ICU, and ICU's
shared library version changes quickly, so even between 2 ubuntu
versions the binaries will not work.
With this change we now build from source in the release build, which is
already what windows does, and we disable ICU / iconv since those don't
seem vital for the windows manifest use case. This seems easier than
building a libxml out of band in our CI images that do the release
builds.
Fixes https://github.com/llvm/llvm-project/issues/215764
Assisted-By: codex
Commit: 3f5d17b22586bd080c62d5b294bd05c0dc282ba4
https://github.com/llvm/llvm-project/commit/3f5d17b22586bd080c62d5b294bd05c0dc282ba4
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/test/Transforms/SLPVectorizer/AArch64/narrowed-reduction-chain-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
Log Message:
-----------
[SLP]Vectorize bool-to-bitmask reductions as a bitcast of zero tests
An or-reduction of boolean leaves each shifted by their own bit position
(an array of bools packed into a bitmask) is a bitcast of the per-lane
zero tests to an integer, which the backend lowers to a movmsk (X86).
Emit that instead of the shift and reduce sequence when it is cheaper.
Fixes #41997
Assisted-by: Cursor
Reviewers: RKSimon
Pull Request: https://github.com/llvm/llvm-project/pull/223434
Commit: 728c9659e9eac4890bd347836e678b35b2eb3fd7
https://github.com/llvm/llvm-project/commit/728c9659e9eac4890bd347836e678b35b2eb3fd7
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M .github/workflows/containers/libc/Dockerfile
M .github/workflows/release-binaries.yml
M clang/cmake/caches/Release.cmake
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/DeclFriend.h
M clang/include/clang/Basic/BuiltinsX86.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/SemaX86.h
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/lib/Headers/CMakeLists.txt
A clang/lib/Headers/avx10v2aux_512intrin.h
A clang/lib/Headers/avx10v2auxintrin.h
M clang/lib/Headers/cpuid.h
M clang/lib/Headers/immintrin.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaX86.cpp
A clang/test/CodeGen/Sparc/sparc-long-double-abi.c
M clang/test/CodeGen/Sparc/sparc-vaarg.c
M clang/test/CodeGen/Sparc/sparcv8-abi.c
M clang/test/CodeGen/Sparc/variadic-aggregate.c
A clang/test/CodeGen/X86/avx10_2_v2aux-builtins-errors.c
A clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
M clang/test/CodeGen/attr-target-x86.c
M clang/test/CodeGen/builtin-cpu-supports-all.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/Driver/x86-target-features.c
M clang/test/Preprocessor/init.c
M clang/test/Preprocessor/predefined-arch-macros.c
M clang/test/Preprocessor/x86_target_features.c
M clang/test/Sema/attr-target-mv.c
M clang/tools/offload-arch/AMDGPUArchByKFD.cpp
M clang/unittests/offload-arch/OffloadArchTest.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/scudo/standalone/secondary.h
M compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
M flang/include/flang/Optimizer/Dialect/CUF/Attributes/CUFAttr.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.h
M flang/include/flang/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.h
M flang/lib/Optimizer/Dialect/CUF/Attributes/CUFAttr.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCOpsInterfaces.cpp
M flang/lib/Optimizer/OpenACC/Support/FIROpenACCTypeInterfaces.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/depend01.f90
A flang/test/Transforms/OpenACC/acc-implicit-data-device-data.fir
M libc/lib/CMakeLists.txt
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/test/API/tools/lldb-dap/evaluate/main.cpp
M lldb/tools/lldb-dap/DAP.cpp
M llvm/cmake/modules/FindLibXml2.cmake
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/IR/IntrinsicsX86.td
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/IR/PassManager.cpp
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Target/AArch64/AArch64InstrFormats.td
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
M llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyPostLegalizerCombiner.cpp
M llvm/lib/Target/WebAssembly/GISel/WebAssemblyPreLegalizerCombiner.cpp
M llvm/lib/Target/X86/GISel/X86PreLegalizerCombiner.cpp
M llvm/lib/Target/X86/X86.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
M llvm/lib/Target/X86/X86InstrControl.td
M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
M llvm/lib/Target/X86/X86InstrInfo.td
M llvm/lib/Target/X86/X86InstrPredicates.td
M llvm/lib/Target/X86/X86IntrinsicsInfo.h
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.h
M llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fcanonicalize.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fminnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fadd.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fmul.bf16.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fsub.bf16.ll
A llvm/test/CodeGen/NVPTX/infer-address-space-join.ll
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp4-fp6-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp8-ps-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-cvt-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-mask-bias-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-mask-cvt-ps-fp8-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-pmovssdb-intrinsics.ll
A llvm/test/CodeGen/X86/avx10_v2aux-unpackb-intrinsics.ll
A llvm/test/CodeGen/X86/pseudo-expand-tc.mir
M llvm/test/CodeGen/X86/replace_unsupported_masked_mem_intrin.ll
M llvm/test/CodeGen/X86/vselect-widen-mask-tree.ll
A llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
A llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
A llvm/test/MC/X86/avx10_v2_aux-att-32.s
A llvm/test/MC/X86/avx10_v2_aux-att-64.s
A llvm/test/MC/X86/avx10_v2_aux-intel-32.s
A llvm/test/MC/X86/avx10_v2_aux-intel-64.s
M llvm/test/Other/X86/opt-bisect-isel.ll
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/test/Transforms/Attributor/nofpclass-sin-cos.ll
M llvm/test/Transforms/Attributor/nofpclass-trig.ll
A llvm/test/Transforms/InferAddressSpaces/NVPTX/address-space-join.ll
M llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/narrowed-reduction-chain-use.ll
M llvm/test/Transforms/SLPVectorizer/X86/bool-mask.ll
M llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Ampere/Ampere1B/basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A320-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Nano-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Premium-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/C1Ultra-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/hip12-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/HiSilicon/tsv110-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s
M llvm/test/tools/llvm-mca/AArch64/Olympus/basic-instructions.s
M llvm/unittests/TargetParser/TripleTest.cpp
M llvm/utils/TableGen/X86ManualFoldTables.def
M mlir/include/mlir/Dialect/OpenACC/OpenACCOpsInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCTypeInterfaces.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCUtils.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/OpenACC/Utils/OpenACCUtils.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCUtilsTest.cpp
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/2162982c1cc0...728c9659e9ea
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