[all-commits] [llvm/llvm-project] 3d7395: [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d7395a6b066a476d6e711e7da3be8c47aec81d2
      https://github.com/llvm/llvm-project/commit/3d7395a6b066a476d6e711e7da3be8c47aec81d2
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP_VL pairs (#223863)

Given this pattern
```
  %down = RISCVISD::VSLIDEDOWN_VL undef, %val, %shift, %mask, %vl0
%up = RISCVISD::VSLIDEUP_VL %val, %down, %shift, %mask, %vl1
```
We can simplify it with `%val`, as it's doing redundant shifting.

This pattern usually show up when we emit lots of
insert/extract_subvector or concat_vectors while legalizing ops. Since
those ISD will not be cleaned up by any DAG combine, they are
immediately lowered into RISCVISD. This patch adds the missing DAG
combine to clean them up.



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