[all-commits] [llvm/llvm-project] aa7a0c: [X86] AVX10_V2_AUX Implementation (#206888)

[Ganesh via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa7a0c3c318b8391c61fba9dcbb98e08c85d5776
      https://github.com/llvm/llvm-project/commit/aa7a0c3c318b8391c61fba9dcbb98e08c85d5776
  Author: Ganesh <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M clang/docs/ReleaseNotes.md
    M clang/include/clang/Basic/BuiltinsX86.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Options/Options.td
    M clang/include/clang/Sema/SemaX86.h
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Basic/Targets/X86.h
    M clang/lib/Headers/CMakeLists.txt
    A clang/lib/Headers/avx10v2aux_512intrin.h
    A clang/lib/Headers/avx10v2auxintrin.h
    M clang/lib/Headers/cpuid.h
    M clang/lib/Headers/immintrin.h
    M clang/lib/Sema/SemaX86.cpp
    A clang/test/CodeGen/X86/avx10_2_v2aux-builtins-errors.c
    A clang/test/CodeGen/X86/avx10_2_v2aux-builtins.c
    M clang/test/CodeGen/attr-target-x86.c
    M clang/test/CodeGen/builtin-cpu-supports-all.c
    M clang/test/CodeGen/target-builtin-noerror.c
    M clang/test/Driver/x86-target-features.c
    M clang/test/Preprocessor/x86_target_features.c
    M clang/test/Sema/attr-target-mv.c
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M llvm/docs/ReleaseNotes.md
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/lib/Target/X86/X86InstrAVX10_V2_AUX.td
    M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrPredicates.td
    M llvm/lib/Target/X86/X86IntrinsicsInfo.h
    M llvm/lib/TargetParser/Host.cpp
    M llvm/lib/TargetParser/X86TargetParser.cpp
    A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp4-fp6-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-cvt-fp8-ps-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-cvt-ps-fp8-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-mask-bias-ps-fp8-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-mask-cvt-ps-fp8-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-pmovssdb-intrinsics.ll
    A llvm/test/CodeGen/X86/avx10_v2aux-unpackb-intrinsics.ll
    A llvm/test/MC/Disassembler/X86/avx10_v2_aux-32.txt
    A llvm/test/MC/Disassembler/X86/avx10_v2_aux-64.txt
    A llvm/test/MC/X86/avx10_v2_aux-att-32.s
    A llvm/test/MC/X86/avx10_v2_aux-att-64.s
    A llvm/test/MC/X86/avx10_v2_aux-intel-32.s
    A llvm/test/MC/X86/avx10_v2_aux-intel-64.s
    M llvm/test/TableGen/x86-fold-tables.inc
    M llvm/utils/TableGen/X86ManualFoldTables.def

  Log Message:
  -----------
  [X86] AVX10_V2_AUX Implementation (#206888)

- AVX10_V2_AUX builds on AVX10 with FP8/FP4/FP6 format conversions
optimized for AI/ML inference workloads, enabling efficient
low-precision arithmetic

- Narrowing conversions from single-precision to FP8: VCVTPS2BF8,
VCVTPS2HF8, VCVTPS2BF8S, VCVTPS2HF8S with optional saturation, biasing
(VCVTBIASPS2BF8/HF8), and round-to-odd (VCVTROPS2HF8) variants

- Expanding conversions from FP8 to single-precision: VCVTBF82PS,
VCVTHF82PS that widen 8-bit FP formats with masking support

- FP4/FP6 conversions: VCVTBF82BF4S, VCVTHF82BF4S for truncating,
VCVTBF82BF6S, VCVTHF82HF6S for same-size, and expanding VCVTBF42HF8,
VCVTBF62BF8, VCVTHF62HF8

- Support includes instruction definitions, intrinsics, and Clang
headers

- Tests covering AT&T and Intel syntax assembly for both 32-bit and
64-bit modes, plus disassembler tests verifying encoding and decoding
 
Specification: [ACE (AI Compute Extensions) Specification
v1.0](https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf)

Co-authored-by: Umesh Kalvakuntla
Co-authored-by: Attarde, Mahesh <mahesh.attarde at intel.com>



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