[all-commits] [llvm/llvm-project] abecf7: [SPIR-V][NewPM] Do not require RegBankSelect in in...

[Arseniy Obolenskiy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abecf784ec30bce9d9163bd2e0d14c4a70094045
      https://github.com/llvm/llvm-project/commit/abecf784ec30bce9d9163bd2e0d14c4a70094045
  Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVCodeGenPassBuilder.cpp
    M llvm/test/CodeGen/SPIRV/llc-pipeline.ll

  Log Message:
  -----------
  [SPIR-V][NewPM] Do not require RegBankSelect in instruction selection (#225023)

SPIR-V skips RegBankSelect and keeps virtual registers, so the property
is never set

Match the legacy pipeline



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