[all-commits] [llvm/llvm-project] a0b735: Add PISA codegen pipeline and lowering passes

[Michal Paszkowski via All-commits]

  Branch: refs/heads/users/michalpaszkowski/pisa_backend_upstreaming_6
  Home:   https://github.com/llvm/llvm-project
  Commit: a0b7352b32d60d6602b679393eefbb677922001a
      https://github.com/llvm/llvm-project/commit/a0b7352b32d60d6602b679393eefbb677922001a
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/CMakeLists.txt
    M llvm/lib/Target/PISA/PISA.h
    A llvm/lib/Target/PISA/PISACacheHintSelector.cpp
    A llvm/lib/Target/PISA/PISAConstProp.cpp
    A llvm/lib/Target/PISA/PISAConstProp.h
    A llvm/lib/Target/PISA/PISAEmitIntrinsics.cpp
    A llvm/lib/Target/PISA/PISAExpandIntrinsics.cpp
    A llvm/lib/Target/PISA/PISAInsertLifetimeStart.cpp
    A llvm/lib/Target/PISA/PISAKernelByValArgsLowering.cpp
    A llvm/lib/Target/PISA/PISAKernelByValArgsLowering.h
    A llvm/lib/Target/PISA/PISALayout.cpp
    A llvm/lib/Target/PISA/PISALegalizeCalls.cpp
    A llvm/lib/Target/PISA/PISALegalizePredicates.cpp
    A llvm/lib/Target/PISA/PISALegalizeSubregAccess.cpp
    A llvm/lib/Target/PISA/PISAMarkConvergentNoMerge.cpp
    A llvm/lib/Target/PISA/PISAOptimizeRedundantCopies.cpp
    A llvm/lib/Target/PISA/PISAOptimizeSubregAccess.cpp
    A llvm/lib/Target/PISA/PISAPropagateNullPointers.cpp
    A llvm/lib/Target/PISA/PISAReplaceIntrinsics.cpp
    A llvm/lib/Target/PISA/PISAScopeSelector.cpp
    M llvm/lib/Target/PISA/PISATargetMachine.cpp
    A llvm/lib/Target/PISA/PISAVerifier.cpp
    A llvm/lib/Target/PISA/PISAVerifyTypes.cpp
    A llvm/test/CodeGen/PISA/mark-convergent-no-merge.mir
    A llvm/test/CodeGen/PISA/pisa-scope-selector.mir
    A llvm/test/CodeGen/PISA/propagate-null.ll
    A llvm/test/CodeGen/PISA/verify-types.mir

  Log Message:
  -----------
  Add PISA codegen pipeline and lowering passes

Add the IR- and MIR-level passes that make up the PISA code generation
pipeline and wire them into PISAPassConfig in PISATargetMachine:

- Intrinsic handling: PISAEmitIntrinsics, PISAExpandIntrinsics,
    PISAReplaceIntrinsics
- Call/ABI lowering: PISALegalizeCalls, PISAKernelByValArgsLowering
- IR preparation: PISAPropagateNullPointers, PISALayout, PISAConstProp
- Legalization/verification: PISALegalizePredicates, PISAVerifyTypes,
    PISAVerifier
- Post-selection: PISAScopeSelector, PISACacheHintSelector,
    PISALegalizeSubregAccess, PISAOptimizeSubregAccess,
    PISAOptimizeRedundantCopies, PISAMarkConvergentNoMerge,
    PISAInsertLifetimeStart

PISAPassConfig now overrides the GlobalISel and pre/post-regalloc hooks
to run these passes, disables the machine passes that assume physical
registers, and runs the load/store vectorizer and atomic expansion in
the IR stage.

AsmPrinter is added in a follow-up change, so this commit is tested with
MIR-level -run-pass/-stop-after tests.


  Commit: 59fd1aac01ae72df699e5331ba47b1dca60f4656
      https://github.com/llvm/llvm-project/commit/59fd1aac01ae72df699e5331ba47b1dca60f4656
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/CMakeLists.txt

  Log Message:
  -----------
  Review fixes


  Commit: 4a7a6016b1829c1e731e6c77d23a84e187da3bec
      https://github.com/llvm/llvm-project/commit/4a7a6016b1829c1e731e6c77d23a84e187da3bec
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/PISAKernelByValArgsLowering.cpp

  Log Message:
  -----------
  Formatting fix


  Commit: 2c1e77695f3dc39470152569149665d19697ff53
      https://github.com/llvm/llvm-project/commit/2c1e77695f3dc39470152569149665d19697ff53
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/PISACacheHintSelector.cpp
    M llvm/lib/Target/PISA/PISAConstProp.cpp
    M llvm/lib/Target/PISA/PISAEmitIntrinsics.cpp
    M llvm/lib/Target/PISA/PISAExpandIntrinsics.cpp
    M llvm/lib/Target/PISA/PISAInsertLifetimeStart.cpp
    M llvm/lib/Target/PISA/PISAKernelByValArgsLowering.cpp
    M llvm/lib/Target/PISA/PISALayout.cpp
    M llvm/lib/Target/PISA/PISALegalizeCalls.cpp
    M llvm/lib/Target/PISA/PISALegalizePredicates.cpp
    M llvm/lib/Target/PISA/PISALegalizeSubregAccess.cpp
    M llvm/lib/Target/PISA/PISAOptimizeRedundantCopies.cpp
    M llvm/lib/Target/PISA/PISAOptimizeSubregAccess.cpp
    M llvm/lib/Target/PISA/PISAPropagateNullPointers.cpp
    M llvm/lib/Target/PISA/PISAReplaceIntrinsics.cpp
    M llvm/lib/Target/PISA/PISAScopeSelector.cpp
    M llvm/lib/Target/PISA/PISAVerifier.cpp
    M llvm/lib/Target/PISA/PISAVerifyTypes.cpp
    A llvm/test/CodeGen/PISA/legalize-calls-unsupported-type.ll
    M llvm/test/CodeGen/PISA/mark-convergent-no-merge.mir
    A llvm/test/CodeGen/PISA/pisa-scope-selector-unknown.mir
    M llvm/test/CodeGen/PISA/pisa-scope-selector.mir
    M llvm/test/CodeGen/PISA/propagate-null.ll
    M llvm/test/CodeGen/PISA/verify-types.mir

  Log Message:
  -----------
  Fix issues raised in earlier PRs


  Commit: e5add9ddf9d2698ab069736469a4c5c9cd9ebaae
      https://github.com/llvm/llvm-project/commit/e5add9ddf9d2698ab069736469a4c5c9cd9ebaae
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/PISATargetMachine.cpp

  Log Message:
  -----------
  Improve comment


  Commit: 9e1a623f6cf1db1d624558ead0a2e9096650c593
      https://github.com/llvm/llvm-project/commit/9e1a623f6cf1db1d624558ead0a2e9096650c593
  Author: Michal Paszkowski <michal.paszkowski at intel.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/PISA/PISALegalizeCalls.cpp

  Log Message:
  -----------
  Simplify, remove redundant comment


Compare: https://github.com/llvm/llvm-project/compare/a64bd8c78d73...9e1a623f6cf1

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