[all-commits] [llvm/llvm-project] 325317: [X86] Correct folded insert costs for partial vect...

[Milin Bhade via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 32531790756e61174d7bebb7c0543f643298f596
      https://github.com/llvm/llvm-project/commit/32531790756e61174d7bebb7c0543f643298f596
  Author: Milin Bhade <mbhade at amd.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/X86/load_store.ll
    A llvm/test/Analysis/CostModel/X86/nonpow2-load-fold.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll
    M llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll
    M llvm/test/Transforms/SLPVectorizer/X86/nonpow2-shared-weight-reduction.ll

  Log Message:
  -----------
  [X86] Correct folded insert costs for partial vector loads (#220174)

The SLP vectorizer can form non-power-of-two trees, including width-3
trees, but relies on target costs to determine profitability: #194189

X86 getMemoryOpCost overestimated non-power-of-two vector loads by
counting a folded PINSR*(mem) chunk as both a memory operation and a
separate lane insertion.

Recognize non-0th folded load-insert chunks and charge each once.
Leading sub-dword loads, stores, and 8-byte chunks remain unchanged.



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