[all-commits] [llvm/llvm-project] dc2110: [RISCV] Add assembler support for the Qualcomm Xqc...

[Sudharsan Veeravalli via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc21109c01ad1d52f105f892794b1995e449751b
      https://github.com/llvm/llvm-project/commit/dc21109c01ad1d52f105f892794b1995e449751b
  Author: Sudharsan Veeravalli <svs at qti.qualcomm.com>
  Date:   2026-09-22 (Tue, 22 Sep 2026)

  Changed paths:
    M clang/test/Driver/print-supported-extensions-riscv.c
    M llvm/docs/RISCVUsage.md
    M llvm/docs/ReleaseNotes.md
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/lib/Target/RISCV/RISCVInstrInfoXqccmi.td
    M llvm/lib/Target/RISCV/RISCVSystemOperands.td
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/features-info.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/xqccmi-invalid.s
    A llvm/test/MC/RISCV/xqccmi-valid.s
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add assembler support for the Qualcomm Xqccmi vendor extension (#225119)

This patch adds support for assembling and disassembling the Qualcomm
Xqccmi 16-bit Instruction Lookup Table vendor extension. The extension
has a single `qc.cm.ilut` instruction which executes one or two
instructions from an instruction lookup table. The encoding overlaps
with `c.fld`, making `Xqccmi` and `Zcd` mutually exclusive.

The extension also adds two CSR's `qc.itba` and `qc.itdec` that contain
the lookup table base address and the leading double entries count
respectively.

Spec:
https://github.com/qualcomm/riscv-unified-db/releases#release-Xqccmi-0.2.0

Assisted by gpt-5.6-luna.



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