[all-commits] [llvm/llvm-project] f23066: [X86] Add ACE v1 (AI Compute Extensions) support

Ganesh via All-commits all-commits at lists.llvm.org
Mon Sep 21 16:20:50 PDT 2026 

  Branch: refs/heads/users/ganeshgit/X86ACEV1
  Home:   https://github.com/llvm/llvm-project
  Commit: f230665c970b48f6a7832605bd61100b48397aeb
      https://github.com/llvm/llvm-project/commit/f230665c970b48f6a7832605bd61100b48397aeb
  Author: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86_64.td
    M clang/include/clang/Options/Options.td
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Basic/Targets/X86.h
    M clang/lib/Headers/CMakeLists.txt
    A clang/lib/Headers/acev1intrin.h
    M clang/lib/Headers/cpuid.h
    M clang/lib/Headers/immintrin.h
    M clang/lib/Sema/SemaX86.cpp
    A clang/test/CodeGen/X86/ace-api.c
    A clang/test/CodeGen/X86/ace-builtins.c
    A clang/test/CodeGen/X86/ace-inline-asm.c
    A clang/test/CodeGen/X86/acev1.c
    A clang/test/CodeGen/X86/acev1_api.c
    A clang/test/CodeGen/X86/acev1_bsr.c
    A clang/test/CodeGen/X86/acev1_errors.c
    A clang/test/CodeGen/X86/acev1_inline_asm.c
    A clang/test/CodeGen/X86/acev1_mxfp8.c
    A clang/test/CodeGen/X86/acev1_tile_movement.c
    M clang/test/CodeGen/attr-target-x86.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86FastTileConfig.cpp
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/lib/Target/X86/X86InstrACE.td
    M llvm/lib/Target/X86/X86InstrAMX.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrPredicates.td
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    M llvm/lib/Target/X86/X86LowerTileCopy.cpp
    M llvm/lib/Target/X86/X86MachineFunctionInfo.cpp
    M llvm/lib/Target/X86/X86MachineFunctionInfo.h
    M llvm/lib/Target/X86/X86PreTileConfig.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/Target/X86/X86TileConfig.cpp
    M llvm/lib/TargetParser/X86TargetParser.cpp
    A llvm/test/CodeGen/X86/ACE/ace-intrinsics.ll
    A llvm/test/CodeGen/X86/ACE/acev1-greedy-ra.ll
    A llvm/test/CodeGen/X86/ACE/acev1-outer-product.ll
    A llvm/test/CodeGen/X86/ACE/acev1-tile-basic.ll
    M llvm/test/CodeGen/X86/ipra-reg-usage.ll
    A llvm/test/MC/X86/ACE/ace-att.s
    A llvm/test/MC/X86/ACE/ace-error.s
    A llvm/test/MC/X86/ACE/ace-intel.s
    M llvm/test/TableGen/x86-fold-tables.inc

  Log Message:
  -----------
  [X86] Add ACE v1 (AI Compute Extensions) support

ACE v1 introduces new tile-based matrix operations with fixed 16x64
tile dimensions (Palette 2), unlike AMX's configurable dimensions.

Key features:
- New __acetile type with fixed 16x64 dimensions
- __tile_ace_* intrinsics for ACE tile operations
- Outer product instructions: TOP4BUUD, TOP4BUSD, TOP4BSSD, TOP4BSUD, TOP2BF16PS
- Mixed precision FP8 instructions: TOP4MX variants
- Tile movement: TILEMOVROW, TILEMOVCOL for ZMM<->tile transfers
- BSR (Block Scale Register) operations for scaling factors
- ACE tile spill/reload using TILEMOVROW + VMOVUPS row-by-row
  (ACE doesn't have TILELOADD/TILESTORED instructions)

Backend changes:
- X86LowerTileCopy handles ACE tile copies
- X86PreTileConfig/X86FastPreTileConfig for ACE register allocation
- Palette 2 tile configuration support

Reused from AMX:
- The x86_amx type
- AMX-AVX512f definitions and TILE instruction definitions
- Passes for lowering and handling the x86_amx type
- Wrappers internally use rows and cols to use amx definitions

This PR builds on PR #206888 and should be reviewed after/with it.


  Commit: 096571a9dfc982b9a4595ed613f58e59e6c57aa3
      https://github.com/llvm/llvm-project/commit/096571a9dfc982b9a4595ed613f58e59e6c57aa3
  Author: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86_64.td
    M clang/lib/Headers/acev1intrin.h
    M clang/lib/Sema/SemaX86.cpp
    R clang/test/CodeGen/X86/ace-api.c
    R clang/test/CodeGen/X86/ace-builtins.c
    R clang/test/CodeGen/X86/ace-inline-asm.c
    M clang/test/CodeGen/X86/acev1.c
    M clang/test/CodeGen/X86/acev1_api.c
    M clang/test/CodeGen/X86/acev1_bsr.c
    M clang/test/CodeGen/X86/acev1_errors.c
    M clang/test/CodeGen/X86/acev1_inline_asm.c
    M clang/test/CodeGen/X86/acev1_mxfp8.c
    M clang/test/CodeGen/X86/acev1_tile_movement.c
    M clang/test/CodeGen/attr-target-x86.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrACE.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    M llvm/lib/Target/X86/X86LowerTileCopy.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/TargetParser/X86TargetParser.cpp
    R llvm/test/CodeGen/X86/ACE/ace-intrinsics.ll
    R llvm/test/CodeGen/X86/ACE/acev1-greedy-ra.ll
    R llvm/test/CodeGen/X86/ACE/acev1-outer-product.ll
    R llvm/test/CodeGen/X86/ACE/acev1-tile-basic.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-greedy-ra.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-intrinsics.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-outer-product.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-tile-O0.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-tile-basic.ll
    A llvm/test/CodeGen/X86/ACEV1/acev1-tile-spill.ll
    A llvm/test/MC/Disassembler/X86/acev1.txt
    R llvm/test/MC/X86/ACE/ace-att.s
    R llvm/test/MC/X86/ACE/ace-error.s
    R llvm/test/MC/X86/ACE/ace-intel.s
    A llvm/test/MC/X86/ACEV1/acev1-att.s
    A llvm/test/MC/X86/ACEV1/acev1-error.s
    A llvm/test/MC/X86/ACEV1/acev1-intel.s

  Log Message:
  -----------
  Address review comments

- Rename the ACE tests and directories to acev1 for consistency
- Build acev1 on top of avx10.1 rather than avx10.2
- Fix test encodings and the BSR0 implicit defs
- Make the scale register type consistent with the spec
- Add memory operand tests for bsrmov
- Confirm the ACEV1 ISA implication chain
- Take the outer product ZMM sources by value instead of by register ID,
  so they are allocated conventionally, and mark the 512-bit ACE builtins
  with RequiredVectorWidth<512>
- Use pseudos for SPILL and RELOAD. Spills use scratch zmm. Don't use
  non-ace ISA.
- Fix missing vector r/m in MRMSrcReg4VOp3.


  Commit: f53c0f91225127347eff3805bf7397de0673745b
      https://github.com/llvm/llvm-project/commit/f53c0f91225127347eff3805bf7397de0673745b
  Author: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86_64.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Options/Options.td
    M clang/include/clang/Sema/SemaX86.h
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Headers/acev1intrin.h
    M clang/lib/Sema/SemaX86.cpp
    M clang/test/CodeGen/X86/acev1.c
    M clang/test/CodeGen/X86/acev1_api.c
    M clang/test/CodeGen/X86/acev1_bsr.c
    M clang/test/CodeGen/X86/acev1_errors.c
    A clang/test/CodeGen/X86/acev1_feature_errors.c
    M clang/test/CodeGen/X86/acev1_inline_asm.c
    R clang/test/CodeGen/X86/acev1_mxfp8.c
    M clang/test/CodeGen/X86/acev1_tile_movement.c
    M clang/test/Driver/x86-target-features.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrACE.td
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    M llvm/lib/Target/X86/X86LowerTileCopy.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/X86/ACEV1/acev1-greedy-ra.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-intrinsics.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-outer-product.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-tile-basic.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-tile-spill.ll
    M llvm/test/MC/X86/ACEV1/acev1-att.s
    M llvm/test/MC/X86/ACEV1/acev1-error.s
    M llvm/test/MC/X86/ACEV1/acev1-intel.s

  Log Message:
  -----------
  [X86][ACEV1] Address review comments

- Drop the AMX_TILE dependency; under acev1 enable only the AMX
  instructions that ACE v1 actually shares.
- Namespace the ACE-invented intrinsics under llvm.x86.acev1.* and leave
  the shared AMX-AVX512 ones in the flat llvm.x86.* namespace.
- Sync the public intrinsic and builtin names with GCC, and add the
  helper macros from the ACE v1 spec.
- Tighten Sema checking of the outer-product group bits, and add driver,
  preprocessor and feature-error test coverage.
- Spell BSR0 literally in the AsmStrings with Defs/Uses instead of
  carrying it as a custom operand, which removes the bespoke handling
  from X86AsmParser and both instruction printers.
- Drop the unused BSR register class; like TMMCFG, BSR0 needs only its
  X86Reg definition and the getReservedRegs entry.
- Adopt the operand-type record naming convention, 't' for a TILE and
  'e' for a GR32 index, on both the instructions and their pseudos,
  retiring the ad-hoc _REG suffix.
- Use WriteSystem rather than WriteVecLogic for the tile outer products
  and the BSR moves.
- Pass tiles by pointer in the unit tests, and drop comments that only
  restate the code.


Compare: https://github.com/llvm/llvm-project/compare/6afc0729617a...f53c0f912251

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