[all-commits] [llvm/llvm-project] 1cf089: [CodeGen][AMDGPU] Add opt-in partial SGPR spills

[Yaxun (Sam) Liu via All-commits]

  Branch: refs/heads/users/yxsamliu/amdgpu-partial-spills
  Home:   https://github.com/llvm/llvm-project
  Commit: 1cf089a54dea4ff088aad5ec20e64c0535309d2d
      https://github.com/llvm/llvm-project/commit/1cf089a54dea4ff088aad5ec20e64c0535309d2d
  Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/dead_bundle.mir
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/infloop-subrange-spill-inspect-subrange.mir
    A llvm/test/CodeGen/AMDGPU/partial-sgpr-spill-buffer-resource.ll
    A llvm/test/CodeGen/AMDGPU/partial-sgpr-spill-cleanup.mir
    A llvm/test/CodeGen/AMDGPU/partial-sgpr-spill-loaded-tuple.ll
    A llvm/test/CodeGen/AMDGPU/partial-sgpr-spill-offset.mir
    A llvm/test/CodeGen/AMDGPU/partial-sgpr-spill-scavenge.mir
    M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/splitkit.mir
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/X86/fp16-spill.ll
    M llvm/test/CodeGen/X86/hoist-spill-lpad.ll

  Log Message:
  -----------
  [CodeGen][AMDGPU] Add opt-in partial SGPR spills

A wide scalar load can have just one word live after its early uses. A
buffer resource can also be split while its fields are being
constructed. Full-width spills save words that are not needed at those
points.

Add a target hook to save selected lanes at their original spill-slot
offsets while preserving the other words. Use it for AMDGPU SGPR tuples,
protect partially written slots from whole-value spill optimizations,
and remove unchanged word stores after matching reloads.

Keep this behind `-enable-partial-spills`, disabled by default.
Unsupported targets and register classes retain their existing spill
policy. Tests based on loaded tuples and buffer resources let the
allocator generate the split relationships from LLVM IR.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications