[all-commits] [llvm/llvm-project] 37f85a: [clang][CodeGen] Use ptrtoaddr for the pointer-ove...
Steven Wu via All-commits
all-commits at lists.llvm.org
Mon Sep 21 15:36:04 PDT 2026
Branch: refs/heads/users/cachemeifyoucan/spr/llvmsupport-make-sysfsfile_t-into-a-seperate-type
Home: https://github.com/llvm/llvm-project
Commit: 37f85ad1b302a993a6b2d3afd0a031baf64e7d9c
https://github.com/llvm/llvm-project/commit/37f85ad1b302a993a6b2d3afd0a031baf64e7d9c
Author: Adam Magier <adam.a.magier.foss at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
M clang/test/CodeGen/catch-pointer-overflow-volatile.c
M clang/test/CodeGen/catch-pointer-overflow.c
M clang/test/CodeGen/ubsan-pointer-overflow.c
Log Message:
-----------
[clang][CodeGen] Use ptrtoaddr for the pointer-overflow check (#223446)
Since 052dde9c3a62 ("[SCEV] Do not represent ptrtoint as ptrtoaddr")
SCEV treats the check's ptrtoint as opaque, so IndVarSimplify no longer
infers nuw on the reconstructed address and InstCombine no longer folds
the comparison. Provably safe checks now survive to run time.
ptrtoaddr is correct here: the address is only compared against the
recomputed one and passed to the handler, and is dead otherwise. This is
unlike the pointer subtraction in d7594bf4caa5 (reverted in
fcd814ae4357), whose result is a user-visible value that can be used to
reconstruct a pointer, e.g. via -(nullptr - ptr).
The result type becomes DL.getAddressType(), so the offset arithmetic is
done in the address width rather than the pointer width. They coincide
in every address space the check is emitted in on in-tree targets, and
where they do not the diagnostics are unaffected: EmitCheckValue
zero-extends a narrower argument to IntPtrTy before the handler call.
Assisted-by: Kiro CLI / Claude Opus 5
Commit: d6da65a5b9822dbdc8764c933334cf609655a63c
https://github.com/llvm/llvm-project/commit/d6da65a5b9822dbdc8764c933334cf609655a63c
Author: Yian Su <yiansu.developer at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-thread-private-storage-remark.mlir
Log Message:
-----------
[mlir][openacc] Report privates using thread-private storage (#224398)
ACCCGToGPU reports privates it places in GPU shared memory, but says
nothing when a private is given per-thread storage instead. Collect
those names too and emit a matching remark.
Commit: cb9286833f2b6bac93edcc258289b54b4681037b
https://github.com/llvm/llvm-project/commit/cb9286833f2b6bac93edcc258289b54b4681037b
Author: Nishant Patel <nishant.b.patel at intel.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
M mlir/test/Dialect/XeGPU/peephole-optimize.mlir
Log Message:
-----------
[mlir][xegpu] Fold memref offset in peephole create_nd_tdesc rewrite (#224459)
XeGPUCreateNdDescOpPattern in peephole optimization only extracted
strided metadata for dynamic-shape
memrefs, but hasStaticShapeAndStrides() ignores the offset — so a
static-shape memref with a nonzero or dynamic offset (e.g. from a
subview) would silently read from offset 0. This PR changes it to always
extract and fold the offset into the base pointer.
Assisted by Claude
Commit: 4791c3055214978d6acc5184bf236d75fc75ee23
https://github.com/llvm/llvm-project/commit/4791c3055214978d6acc5184bf236d75fc75ee23
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Analysis/ScalarEvolution/exit-value-nowrap-flags.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-operand-order.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/nsw.ll
M llvm/test/Analysis/ScalarEvolution/ranges.ll
M llvm/test/Transforms/IndVarSimplify/exit-value-nowrap-flags.ll
Log Message:
-----------
[SCEV] Propagate a recurrence's nuw flag to mul in exit value. (#224974)
Follow-up to #217378. The same reasoning applies to the multiply emitted
as well:
A recurrence's exit value is its closed form Start + BTC * Step. The
multiply does not wrap, if the recurrence does not wrap: the recurrence
reached iteration BTC, so the value it computes there is the value the
recurrence had, and that did not wrap.
Alive2 Proof: https://alive2.llvm.org/ce/z/S3_sRh
Also includes small SCEVExpander changes to thread through operands as
SCEVUse.
PR: https://github.com/llvm/llvm-project/pull/224974
Commit: 5e14ef5d10879eafe6b412278d6d851719e62c88
https://github.com/llvm/llvm-project/commit/5e14ef5d10879eafe6b412278d6d851719e62c88
Author: Jian Li <hellothedreamer at 126.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/docs/GlobalISel/GenericOpcode.md
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/RISCV/GlobalISel/clmulr-rv32.ll
A llvm/test/CodeGen/RISCV/GlobalISel/clmulr-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
M llvm/test/TableGen/get-named-operand-idx.td
Log Message:
-----------
[RISCV][GlobalISel] Add G_CLMULR support (#224525)
Add G_CLMULR to represent reversed carry-less multiplication in generic
Machine IR.
Translate llvm.riscv.clmulr to G_CLMULR and mark it legal for native
XLEN scalar types when Zbc is available.
Commit: 31c70556b20ad72bcb91525448bd0821c90efc27
https://github.com/llvm/llvm-project/commit/31c70556b20ad72bcb91525448bd0821c90efc27
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Parser/options.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Parser/parsing.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
A flang/test/Preprocessing/fixed-c-comment01.F
A flang/test/Preprocessing/fixed-c-comment02.F
A flang/test/Preprocessing/fixed-c-comment03.f
A flang/test/Preprocessing/fixed-c-comment04.f
A flang/test/Preprocessing/fixed-c-comment05.f
A flang/test/Preprocessing/free-c-comment01.f90
M flang/tools/bbc/bbc.cpp
M flang/tools/f18-parse-demo/f18-parse-demo.cpp
Log Message:
-----------
[flang] Accept C-style comments in label fields (#207012)
The main goal of this patch is to make multi-language header files
easier to write and use in fixed format sources. For this reason, and
for simplicity, C-style comments after labels, directives and OpenMP
conditional compilation sentinels are not supported.
Fixes #127426
Assisted-by: Claude Opus 5
Commit: 854a9b8d7036ef52490edfb644f30ba043a0f238
https://github.com/llvm/llvm-project/commit/854a9b8d7036ef52490edfb644f30ba043a0f238
Author: Janet Yang <qxy11 at meta.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M .ci/green-dragon/lldb-ubuntu.groovy
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/resources/build.md
M lldb/include/lldb/Host/Config.h.cmake
R lldb/include/lldb/Host/LZMA.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Host/CMakeLists.txt
R lldb/source/Host/common/LZMA.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/test/CMakeLists.txt
M lldb/test/Shell/lit.cfg.py
M lldb/test/Shell/lit.site.cfg.py.in
M llvm/CMakeLists.txt
M llvm/cmake/config-ix.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/CMake.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Config/llvm-config.h.cmake
M llvm/include/llvm/Support/Compression.h
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Compression.cpp
M llvm/test/CMakeLists.txt
M llvm/test/lit.site.cfg.py.in
M llvm/unittests/Support/CompressionTest.cpp
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M llvm/utils/lit/lit/llvm/config.py
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
[Support][lldb] Port xz (lzma) decompression from LLDB into LLVM (#220092)
### Summary
LLDB's `lldb_private::lzma` is currently the only xz decompressor in the
tree. It reads the ELF `.gnu_debugdata` (MiniDebugInfo) section, whose
embedded symbol table can sometimes be the only source of function names
in a stripped binary. Move it to `'llvm::compression::xz` so that other
tools like llvm-gsymutil can use it.
- Only decompression is implemented and it's kept out of
`compression::Format` since it's not written by LLVM and is produced by
an extra packaging step. It also doesn't model the schemes usable for
SHF_COMPRESSED sections, which are self-describing via some type of
`ELFCOMPRESS_*` constant, which doesn't exist for XZ.
- Reformats the ported code to LLVM standards, but avoids other
functional changes unless a comment was specifically made on the PR to
address it. There is a latent bug in the ported code where
`lzma_index_buffer_decode()` was passed a pointer to the stream index
but the size of the whole stream, which could've caused it to
technically read past the end of the buffer. Valid streams aren't
currently affected since the index is self-delimiting and CRC-checked,
so this will just be addressed in a following PR.
- `LLDB_ENABLE_LZMA` is replaced by `LLVM_ENABLE_LZMA`, and is default
to ON globally. Cases where LLDB_ENABLE_LZMA and LLVM_ENABLE_LZMA are in
disagreement will fail, and otherwise, uses of LLDB_ENABLE_LZMA will
result in deprecation warnings.
- In the Bazel overlay, @llvm-project//lldb:lzma=system flag can no
longer work for the same reason, so it is replaced by
-- at llvm-project//third-party:llvm_enable_lzma=true via a new
//third-party:lzma target alongside the existing zlib and zstd wrappers.
### Testing
Added a unit test testing the decompression
Existing LLDB unit tests of minidebuginfo still passing
Tested with `LLVM_ENABLE_LZMA` both on and off, check-llvm, and
check-lldb-shell are clean.
Commit: bbbcb2eb4f793af95ba9380a2c8be1e33cb6fdb2
https://github.com/llvm/llvm-project/commit/bbbcb2eb4f793af95ba9380a2c8be1e33cb6fdb2
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/AArch64/abi-classify-arg-types.c
M clang/test/CodeGen/AArch64/abi-classify-arg-types.cpp
M clang/test/CodeGen/AArch64/abi-classify-return-types.c
M clang/test/CodeGen/AArch64/abi-classify-return-types.cpp
M llvm/include/llvm/ABI/TargetInfo.h
M llvm/include/llvm/ABI/Types.h
M llvm/lib/ABI/TargetInfo.cpp
M llvm/lib/ABI/Targets/AArch64.cpp
M llvm/lib/ABI/Types.cpp
M llvm/unittests/ABI/AArch64TargetInfoTest.cpp
M llvm/unittests/ABI/TypesTest.cpp
Log Message:
-----------
[LLVMABI][AARCH64] Handle conditions for ignoring empty types (#224476)
This adds AArch64 ABI library handling to decide when empty records and
zero-sized (non-SVE) types can be ignored as arguments and return types.
These are always ignored as return types, but the argument handling
depends on the language and ABI kind.
Assisted-by: Cursor / various models
Commit: f5bd36ecc87a5024feeced94815518438f7344a0
https://github.com/llvm/llvm-project/commit/f5bd36ecc87a5024feeced94815518438f7344a0
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
Log Message:
-----------
[AMDGPU] Do not count AGPRs twice in the wave dispatch VGPR minimum (#225110)
The minimum applies to arch VGPRs, but it was taken against the total,
which already counts AGPRs
Commit: 520af5f67f9f6d9a5a250b04de27020b100076d3
https://github.com/llvm/llvm-project/commit/520af5f67f9f6d9a5a250b04de27020b100076d3
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/CIR/MissingFeatures.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/test/CIR/CodeGen/attr-musttail-ehspec-errors.cpp
M clang/test/CIR/CodeGen/ehspec-noexcept.cpp
Log Message:
-----------
[CIR] Implement exception-related musttail diagnostics (#224778)
When a musttail call occurs in a function that was marked noexcept or
has a dynamic exception specification, we must report a diagnostic to
the user saying that the call is not supported in this case. This change
adds such a diagnostic for CIR codegen.
Assisted-by: Cursor / claude-opus-5
Commit: f12afd1dcfdaddc197aeb950c0d7eead6d7d96f6
https://github.com/llvm/llvm-project/commit/f12afd1dcfdaddc197aeb950c0d7eead6d7d96f6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/kcfi-bti.ll
Log Message:
-----------
AArch64: Don't duplicate the branch's implicit defs in call pseudo expansion (#225064)
These pseudo expansions started with an implicit LR def and are replaced
with a new instruction with a different LR def. Previously this would copy the
old instruction's operand list, merging with the newly build instruction def
list. Avoid creating a redundant def with inconsistent dead flags. This avoids
failing a future verifier check.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: f0159c871942b821eb54f057a7739b4269f72b46
https://github.com/llvm/llvm-project/commit/f0159c871942b821eb54f057a7739b4269f72b46
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Basic/FileEntry.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/ASTMatchers/ASTMatchFinder.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
M clang/lib/Index/FileIndexRecord.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
Log Message:
-----------
[clang] Migrate away from PointerUnion::dyn_cast (NFC) (#225022)
Note that PointerUnion::dyn_cast has been soft deprecated in
PointerUnion.h:
// FIXME: Replace the uses of is(), get() and dyn_cast() with
// isa<T>, cast<T> and the llvm::dyn_cast<T>
Literal migration would result in dyn_cast_if_present (see the
definition of PointerUnion::dyn_cast), but this patch uses dyn_cast
where the operands are known to be nonnull.
The operands are known to be nonnull in one of three ways:
- Preceding checks: A null check, assertion, or dereference a few
lines above guarantees the PointerUnion is nonnull.
- Downstream code: The else or fallthrough branch unconditionally
calls cast<...>, dereferences the pointer, or reaches
llvm_unreachable.
- By construction: In DeclContextInternals.h, FileEntry.h,
FileIndexRecord.cpp, and LifetimeSafety/Checker.cpp, only nonnull
pointers are ever stored in the PointerUnion.
Assisted-by: Antigravity
Commit: 8c5c2ccf47434b4c948e5b875c977bef4d15c84e
https://github.com/llvm/llvm-project/commit/8c5c2ccf47434b4c948e5b875c977bef4d15c84e
Author: Nick Desaulniers <ndesaulniers at google.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCleanup.cpp
M clang/lib/CodeGen/CGCleanup.h
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/EHScopeStack.h
M clang/test/CodeGen/compound-literal-lifetime.c
Log Message:
-----------
[clang][CodeGen] Exempt lifetime marker cleanups in musttail check (#224731)
PR #219045 started emitting @llvm.lifetime.start and @llvm.lifetime.end
markers for block-scoped compound literals in C via
pushCleanupAfterFullExpr<CallLifetimeEnd>.
When a compound literal is evaluated inside a conditional branch,
pushCleanupAfterFullExpr wraps CallLifetimeEnd inside
EHScopeStack::ConditionalCleanup, which did not override
EHScopeStack::Cleanup::isRedundantBeforeReturn(). Consequently,
CodeGenFunction::EmitCall rejected [[clang::musttail]] calls when a
conditional compound literal was in scope at -O1 and above.
Because EHScopeStack::ConditionalCleanup wraps cleanups by composition,
virtual methods on EHScopeStack::Cleanup other than Emit() do not work
for conditional cleanups. Replace the virtual
EHScopeStack::Cleanup::isRedundantBeforeReturn() method with a
StackRestore bit on CleanupKind/EHCleanupScope alongside the existing
LifetimeMarker bit, and check EHCleanupScope::isRedundantBeforeReturn()
in CodeGenFunction::EmitCall.
Assisted-by: Gemini
Fixes: 93b2629d1d1f ("[clang][CodeGen] Emit lifetime markers for
block-scoped compound literals in C (#219045)")
Fixes: https://github.com/llvm/llvm-project/issues/224337
Commit: 2c429b568e1ffa1ee7e88444fac6375d46c5d979
https://github.com/llvm/llvm-project/commit/2c429b568e1ffa1ee7e88444fac6375d46c5d979
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
Log Message:
-----------
WebAssembly: Don't duplicate implicit CALL operands in LowerCallResults (#225069)
When recombining the CALL_PARAMS/CALL_RESULTS pseudo-pair into a real
CALL, LowerCallResults copied CallParams.uses() onto the new instruction.
uses() includes the implicit operands (implicit-def $arguments and the implicit
$sp32/$sp64 uses), which the freshly created CALL already carries. This
resulted in a duplicated implicit-def of $arguments. This avoids a
future verifier error.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 6460a5605d9b73640b25bd5987dea597cd648f47
https://github.com/llvm/llvm-project/commit/6460a5605d9b73640b25bd5987dea597cd648f47
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/test/CodeGen/AArch64/sme-streaming-mode-landingpads.ll
Log Message:
-----------
AArch64: Fix duplicating VG def operands in isel pseudo expansion (#225113)
Previously MSRpstatePseudo's handling would produce a duplicate VG operand.
AdjustInstrPostInstrSelection added an implicit VG use/def and an FPMR def. It's
dubious to introduce a def in the output which wasn't already present in the input,
so fix the missing FPMR def. Also guard against re-introducing the operands for
instructions which already have the defs. Ideally there would not be any of these m
anual def add calls, but that is a larger fix.
This removes the duplicate operand and fixes potentially inconsistent
dead flags, avoiding a failure in a future verifier check.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 150f8999285d07bdebc6a73dfdeae520dbdf1468
https://github.com/llvm/llvm-project/commit/150f8999285d07bdebc6a73dfdeae520dbdf1468
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
Log Message:
-----------
[AMDGPU][NFC] Introduce TDMInsts feature for tensor load/store (#225123)
Commit: 82fb38ef98afbc21ca58c0591209e48cd6d83b37
https://github.com/llvm/llvm-project/commit/82fb38ef98afbc21ca58c0591209e48cd6d83b37
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
Log Message:
-----------
[SLP][NFC]Add a test for deleted nodes but still scheduled, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/225154
Commit: 9d73c09b090939b0a94c2d156519f173734e98a0
https://github.com/llvm/llvm-project/commit/9d73c09b090939b0a94c2d156519f173734e98a0
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
A llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir
Log Message:
-----------
[AMDGPU] Use a bf16 operand profile for v_fma_mix_bf16_t16 (#224910)
Assisted-by: Claude Code Opus 5
Commit: 583e39e96333beb6b5809c94cc0607025938644b
https://github.com/llvm/llvm-project/commit/583e39e96333beb6b5809c94cc0607025938644b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
A llvm/test/tools/llvm-dwarfdump/X86/apple-names-overflowing-entry-count.s
Log Message:
-----------
[DebugInfo] Fix 32-bit overflow in AppleAcceleratorTable::equal_range (#224866)
Computing the end offset overflowed 32 bits before widening to 64 bits.
Because SameNameIterator stops on exact equality, a wrapped offset
caused an infinite loop.
Compute the product in 64 bits and return an empty range if the end
offset exceeds the section size.
rdar://186839483
Commit: cde11153fcbda7fce2299c6fe463f21cfb4a6208
https://github.com/llvm/llvm-project/commit/cde11153fcbda7fce2299c6fe463f21cfb4a6208
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang-rt/unittests/Runtime/Assign.cpp
Log Message:
-----------
[flang-rt][unittests] Define MAP_ANONYMOUS fallback for AIX in Assign tests (#224675)
We ran into
```
flang-rt/unittests/Runtime/Assign.cpp:497:21: error: use of undeclared identifier 'MAP_ANONYMOUS'
497 | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0)};
```
On AIX, `flang-rt` is built with `_XOPEN_SOURCE=700` and without `_ALL_SOURCE`, which prevents `<sys/mman.h> `from exposing `MAP_ANONYMOUS` / `MAP_ANON`. Provide a fallback definition so mmap unit tests introduced in PR #222101 compile successfully on AIX.
Commit: 4648d33f8e759d7557fb5bb8a0978023fa67306b
https://github.com/llvm/llvm-project/commit/4648d33f8e759d7557fb5bb8a0978023fa67306b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
Log Message:
-----------
[lldb] Bounds check minidump location descriptors (#223911)
MinidumpParser::GetModuleUUID sliced the file with the RVA and DataSize
taken straight from a module's CvRecord. ArrayRef::slice asserts, but a
build without assertions still reads out of bounds.
Route both through MinidumpFile::getRawData, which range checks in 64
bits, and log the error rather than returning a slice that looks valid.
rdar://186889966
rdar://186890172
Commit: b33f5efbfbfe621d77d90308c01f4a31ccf18fb1
https://github.com/llvm/llvm-project/commit/b33f5efbfbfe621d77d90308c01f4a31ccf18fb1
Author: Domenic Nutile <domenic.nutile at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
Log Message:
-----------
[AMDGPU][MC] Upstream gfx12 true16 disassembler test coverage (#223825)
Upstream new gfx12 disassembler test cases, covering true16 operand
(.l/.h)
and op_sel decoding for f16 opcodes that had no upstream coverage:
Commit: 5301245b7d20fc4871a3253fd235a31e69f1bdfb
https://github.com/llvm/llvm-project/commit/5301245b7d20fc4871a3253fd235a31e69f1bdfb
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
A llvm/test/CodeGen/X86/pr222714.ll
Log Message:
-----------
[X86] Don't drop a redundant 32-bit `and` whose users were selected as def32 (#223750)
Fixes #222714
Nothing was wrong with the IR or the DAG combines here; the `and %idx,
1` survived all the way into instruction selection. Isel selects users
before operands, so the `zext` of the (narrowed, i32) `and` had already
been turned into a `SUBREG_TO_REG` through the `def32` pattern, which
assumes the i32 producer zeroes the upper 32 bits. When isel then
reached the `and`, `shrinkAndImmediate` noticed via known bits that the
mask was redundant and replaced the `and` with its operand — a
`truncate` of a 64-bit `cmov`. That truncate is just a subregister copy,
so the already-emitted `SUBREG_TO_REG` ended up reading the whole 64-bit
register, and the upper bits went straight into the scaled address. The
`_BitInt(98)` is a red herring; the same thing happens with plain `i64`.
The `def32` predicate now lives in `X86DAGToDAGISel::isDef32` (the
PatLeaf calls it), and `shrinkAndImmediate` only drops a 32-bit `and`
when its operand satisfies that predicate. Otherwise it returns false
and the `and` is selected as a normal 32-bit instruction, which zeroes
the upper half as the users expect.
Commit: b0d31f40189dbdcf8b62e2c6ef79b039c5202aba
https://github.com/llvm/llvm-project/commit/b0d31f40189dbdcf8b62e2c6ef79b039c5202aba
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/test/OpenMP/distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_loop_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_loop_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_messages.cpp
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[clang][OpenMP] ORDERED clause is allowed on FOR in 4.5+ (#225106)
Several compound directives containing FOR were missing the ORDERED
clause in the set of allowed (once) clauses.
Commit: 832df12314030ea46e1ea506cabd98d805ae7ce7
https://github.com/llvm/llvm-project/commit/832df12314030ea46e1ea506cabd98d805ae7ce7
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/Transforms/SROA/phi-and-select.ll
A llvm/test/Transforms/SROA/phi-store.ll
Log Message:
-----------
[SROA] Enable alloca promotion for stores through pointer PHIs (#222893)
A store to an alloca through a phi-node prevents promotion of that
alloca in mem2reg. Mem2reg requires all users of the alloca to be
loads/stores. Fixes https://github.com/llvm/llvm-project/issues/202670.
The following is a motivating example:
```llvm
define i32 @store_to_phi(i1 %cond, i32 %value) {
entry:
%a = alloca i32, align 4
%b = alloca i32, align 4
store i32 0, ptr %a, align 4
store i32 0, ptr %b, align 4
br i1 %cond, label %left, label %right
left:
br label %merge
right:
br label %merge
merge:
%ptr = phi ptr [ %a, %left ], [ %b, %right ]
store i32 %value, ptr %ptr, align 4
%a.value = load i32, ptr %a, align 4
%b.value = load i32, ptr %b, align 4
%result = add i32 %a.value, %b.value
ret i32 %result
}
```
To promote, we can rewrite this so that we store on each branch, before
the phi:
```llvm
define i32 @store_to_phi(i1 %cond, i32 %value) {
entry:
%a = alloca i32, align 4
%b = alloca i32, align 4
store i32 0, ptr %a, align 4
store i32 0, ptr %b, align 4
br i1 %cond, label %left, label %right
left:
store i32 %value, ptr %a, align 4
br label %merge
right:
store i32 %value, ptr %b, align 4
br label %merge
merge:
%a.value = load i32, ptr %a, align 4
%b.value = load i32, ptr %b, align 4
%result = add i32 %a.value, %b.value
ret i32 %result
}
```
Now we can promote.
```llvm
define i32 @store_to_phi(i1 %cond, i32 %value) {
entry:
br i1 %cond, label %left, label %right
left:
br label %merge
right:
br label %merge
merge:
%a.value = phi i32 [ %value, %left ], [ 0, %right ]
%b.value = phi i32 [ 0, %left ], [ %value, %right ]
%result = add i32 %a.value, %b.value
ret i32 %result
}
```
Later optimizations can reduce this to just `ret i32 %value`.
You can't always move the store directly into the phi's direct
predecessor. You can only do this if that predecessor's only has one
successor. Consider the following example:
```llvm
define void @store_to_phi_split_edge(
i1 %choose_right, i1 %take_store, i32 %value, ptr %out) {
entry:
%a = alloca i32, align 4
br i1 %choose_right, label %right, label %left
left:
br label %merge
right:
br i1 %take_store, label %merge, label %exit
merge:
%ptr = phi ptr [ %a, %left ], [ %out, %right ]
store i32 %value, ptr %ptr, align 4
br label %exit
exit:
ret void
}
```
If we moved the store into the `right` branch, then we will now execute
the store when `right` branches directly to `exit`, whereas previously
we didn't. We fix this by splitting the `right` branch:
```llvm
define void @store_to_phi_split_edge(
i1 %choose_right, i1 %take_store, i32 %value, ptr %out) {
entry:
%a = alloca i32, align 4
br i1 %choose_right, label %right, label %left
left:
store i32 %value, ptr %a, align 4
br label %merge
right:
br i1 %take_store, label %right.to.merge, label %exit
right.to.merge:
store i32 %value, ptr %out, align 4
br label %merge
merge:
br label %exit
exit:
ret void
}
```
AI assisted.
Commit: eaab73d4bbaafa471f2216d58172126d2fd7c2b6
https://github.com/llvm/llvm-project/commit/eaab73d4bbaafa471f2216d58172126d2fd7c2b6
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/noinline-available-externally-skip.cpp
Log Message:
-----------
[CIR] Correct the behavior of 'shouldEmitFunction' with always/noinline (#224378)
These attributes modified the linkage of functions in certain cases that
caused us to, ironically, skip emitting something when we picked it up
via PCH during self-build. This patch just copies/pastes the code from
classic codegen.
Commit: 5dfe8605911e3f0f43fe2b5c08b4ffc23f2af37a
https://github.com/llvm/llvm-project/commit/5dfe8605911e3f0f43fe2b5c08b4ffc23f2af37a
Author: Pranav Kant <prka at google.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/CMakeLists.txt
M clang/include/clang/Config/config.h.cmake
M clang/lib/Interpreter/IncrementalExecutor.cpp
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/include/clang/Config/config.h
Log Message:
-----------
[clang-repl] Add CLANG_ENABLE_EMUTLS_GET_ADDRESS cmake option (#217700)
Guard the extern "C" declaration and reference to __emutls_get_address
in IncrementalExecutor.cpp behind a new CMake option
CLANG_ENABLE_EMUTLS_GET_ADDRESS, which is OFF by default.
This prevents link errors in environments/runtimes where
__emutls_get_address is not available.
Replace all other guards with the new cmake option.
Commit: 16dcf47ee4fb8a9cb6dd8759e7be6599d935b618
https://github.com/llvm/llvm-project/commit/16dcf47ee4fb8a9cb6dd8759e7be6599d935b618
Author: Francesco Petrogalli <francesco.petrogalli at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMachObjectWriter.cpp
M llvm/test/MC/RISCV/riscv-relocs-macho-data.s
M llvm/test/MC/RISCV/riscv-relocs-macho.s
Log Message:
-----------
[RISC-V][Mach-O] Fix bogus 12-bit range check on subtraction expressions. (#222205)
Assembling a subtraction expression whose offset does not fit in a
signed 12-bit integer, such as
.word _a - _b + 5000
failed with a misleading diagnostic:
error: AUIPC out of range of corresponding %pcrel_lo instruction
The check was copied from the %pcrel_lo path, where 12 bits is a real
constraint because the offset is inlined in the immediate field of an
addi or an lw. For data, the addend is stored inline in the bytes
being relocated, and a .word has all 32 bits available to hold it.
Drop the check. No extra relocation record is needed; the
offset is simply written in the data, as otool reports in the tests:
.long 5000 @ KIND_DATA
Commit: 5306fce6c317c13a5889e6909a7e3c959747fb02
https://github.com/llvm/llvm-project/commit/5306fce6c317c13a5889e6909a7e3c959747fb02
Author: R-Goc <ryszardgoc at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
A clang/lib/CIR/CodeGen/CIRGenMicrosoftCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CMakeLists.txt
A clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerMicrosoftCXXABI.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
A clang/test/CIR/CodeGen/cxx-msvc-abi.cpp
Log Message:
-----------
[CIR] Add initial Microsoft C++ ABI support in ClangIR (#221038)
Stub out Microsoft C++ ABI support for ClangIR CodeGen and dialect
lowering:
- Stub out CIRGenMicrosoftCXXABI.
- Stub out LowerMicrosoftCXXABI to integrate into the TargetLowering
pass in CIR dialect transforms.
- Add error.NYI extensively.
- Add a minimal test file, mainly so that it is in tree.
Assisted-by: Gemini:gemini-3.8-flash-high
Commit: 88c276ca9da8385ceb0b343db45f9f6f4dbaf8dd
https://github.com/llvm/llvm-project/commit/88c276ca9da8385ceb0b343db45f9f6f4dbaf8dd
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/test/Transforms/InstCombine/atomic.ll
Log Message:
-----------
[InstCombine] Preserve elementwise atomic access sizes (#223897)
There are two cases where instcombine currently will change the atomic
access size of an unordered elementwise atomic. Note that, for example,
`load atomic elementwise <4 x i32>` and `load atomic elementwise <2 x
i64>` do not have equivalent semantics. The former has 4 atomic accesses
and the latter has 2. Rewriting the former to the latter can introduce
mixed-size, concurrent, atomic accesses, which race in LLVM. Without
`elementwise`, rewriting _is_ legal.
The two cases are:
1. `mergeStoreIntoSuccessor`:
```
/// Try to transform:
/// if () { *P = v1; } else { *P = v2 }
/// or:
/// *P = v1; if () { *P = v2; }
/// into a phi node with a store in the successor.
```
You can't do this if the stores have different atomic access sizes.
2. Load CSE and load-to-store forwarding. These are also illegal if the
memory operations in question have different atomic access sizes.
Fixes https://github.com/llvm/llvm-project/issues/223738.
AI assisted.
Commit: 364f1c3d236c2cf3c15c0d4b119e7cdd05d1b945
https://github.com/llvm/llvm-project/commit/364f1c3d236c2cf3c15c0d4b119e7cdd05d1b945
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/test/CodeGen/Sparc/sparc-vaarg.c
M clang/test/CodeGen/Sparc/sparcv8-abi.c
Log Message:
-----------
[Sparc][clang] Match GCC's SPARC V8 vector argument passing (#222254)
Pass floating-point vectors and vectors larger than 64 bits indirectly.
Assisted-by: Codex
Commit: 37e2c3bc9610b7952405ddd7c3557c93e933e554
https://github.com/llvm/llvm-project/commit/37e2c3bc9610b7952405ddd7c3557c93e933e554
Author: Konstantinos Parasyris <koparasy at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
A clang/test/CIR/CodeGen/lowering-lang-options.cpp
A clang/test/CIR/IR/lowering-lang-options.cir
Log Message:
-----------
[CIR] Serialize lowering-relevant LangOptions as #cir.lowering_lang_options (#224757)
Post-CIRGen lowering (LoweringPrepare, CallConvLowering)
reads a handful of LangOptions flags that have no
triple/module representation. A reloaded `.cir`
module has no live `clang::LangOptions`, so those flags must be
serialized for the file to be self-describing and lower the
same way it was compiled.
Add a module-level aggregate attribute `#cir.lowering_lang_options`
holding the LangOpts facts lowering consumes: "exceptions,
threadsafe_statics, cuda, cuda_is_device, hip, gpu_rdc, openmp,
openmp_is_target_device, and clang_abi_compat". Target-derived
facts (size_t width, CXXABI, comdat, char/pointer/atomic width,
SDK version, fp formats) are **NOT** stored: they are
rebuilt from `cir.triple`
Co-authored-by: Claude Opus 4.8 (1M context) <noreply at anthropic.com>
Commit: 27b50fc8e7908bc969635c61a96d6d3f08f79941
https://github.com/llvm/llvm-project/commit/27b50fc8e7908bc969635c61a96d6d3f08f79941
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/unittests/Optimizer/InternalNamesTest.cpp
Log Message:
-----------
[flang] Add option to exclude array literals from isCompilerGenerated (#225164)
This is used to register variables under -gpu=mem:unified and array
literals can stay as device resident.
Commit: 2e2655f10d1a05bb585e172083b448a25a5b7434
https://github.com/llvm/llvm-project/commit/2e2655f10d1a05bb585e172083b448a25a5b7434
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/mad-mix-fptrunc-rounding.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
Log Message:
-----------
[AMDGPU] Require flushed FP16 denormals for the mad-mix f16 results (#224911)
v_mad_mixlo_f16 and v_mad_mixhi_f16 are the unfused gfx900 forms and flush 16-bit denormals, so a denormal half result is written as zero even when the FP16 mode asks for it to be kept, while the patterns only required the FP32 mode to flush and that is the one a HIP compile turns off on its own.
Assisted-by: Claude Code Opus 5
Commit: e7b5aa9b5734121f94527261320fcbdb573f37f4
https://github.com/llvm/llvm-project/commit/e7b5aa9b5734121f94527261320fcbdb573f37f4
Author: Jelle Schühmacher <schuehmacher at roofline.ai>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
Log Message:
-----------
[mlir][linalg] Fix exponential walk of tensor.extract indices (#222319)
`isLoopInvariantIdx` showed exponential runtime behavior. Replaced with
a worklist and a visited set.
Encountered in iree-org/iree#24886.
Assisted-by: Claude
Co-authored-by: Claude Opus 5 <noreply at anthropic.com>
Commit: 1492dbc61765111d035eb5a27ea71e7527a8c6c0
https://github.com/llvm/llvm-project/commit/1492dbc61765111d035eb5a27ea71e7527a8c6c0
Author: Adam Magier <adam.a.magier.foss at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/test/CodeGen/ubsan-pointer-overflow-constant-fold.c
Log Message:
-----------
[clang][CodeGen] Compute the pointer-overflow offset from the index list (#225139)
Follow up to #223446. EmitGEPOffsetInBytes recreated the offset by
walking the GEP value that EmitCheckedInBoundsGEP had just created. That
required a separate path for the case where CreateGEP folded the result,
because a folded GEP need not be a GEP at all: `gep(null, 1)` becomes
`inttoptr(1)`, and `gep(@g, 0)` becomes `@g`.
Pass ElemTy and IdxList instead and walk those directly. This removes
the constant path, the cast to GEPOperator, and two asserts that
restated the caller's own behaviour.
This is not quite NFC. The constant path reported OffsetOverflows as
false unconditionally, so a constant GEP whose byte offset wrapped to
exactly zero satisfied the TotalOffset == Zero early return and emitted
no check. The unified path computes the flag, so such a GEP now emits
one. It is provably valid, since TotalOffset == 0 makes the computed
address equal the base, so this is extra IR at -O0 rather than a change
in behaviour.
Add constant-base cases to ubsan-pointer-overflow-constant-fold.c,
including the wraps-to-zero case: it passes before this change only
because no check is emitted at all.
Assisted-by: Kiro CLI / Claude Opus 5
Commit: b09f78de3c4163d6c52971c185dcf4ed66015d06
https://github.com/llvm/llvm-project/commit/b09f78de3c4163d6c52971c185dcf4ed66015d06
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/WasmEHPrepare.cpp
Log Message:
-----------
[WebAssembly] Remove an unnecessary variable (NFC) (#224962)
That `CPI` had a use when first written in
https://github.com/llvm/llvm-project/commit/99d60e0dabcf20f4db683da83cde905b7a1373de
but after
https://github.com/llvm/llvm-project/commit/445f4e74841e87da06743a4c126b09c9b9b05124
it's not necessary to cast it anymore.
Commit: 0b04288569e3daff0c42e302d6e024056eedb895
https://github.com/llvm/llvm-project/commit/0b04288569e3daff0c42e302d6e024056eedb895
Author: Adam Magier <adam.a.magier.foss at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
Log Message:
-----------
[clang][CodeGen] Compute the pointer-overflow offset from the index list (#225139)
Follow up to #223446. EmitGEPOffsetInBytes recreated the offset by
walking the GEP value that EmitCheckedInBoundsGEP had just created. That
required a separate path for the case where CreateGEP folded the result,
because a folded GEP need not be a GEP at all: `gep(null, 1)` becomes
`inttoptr(1)`, and `gep(@g, 0)` becomes `@g`.
Pass ElemTy and IdxList instead and walk those directly. This removes
the constant path, the cast to GEPOperator, and two asserts that
restated the caller's own behaviour.
This is not quite NFC. The constant path reported OffsetOverflows as
false unconditionally, so a constant GEP whose byte offset wrapped to
exactly zero satisfied the TotalOffset == Zero early return and emitted
no check. The unified path computes the flag, so such a GEP now emits
one. It is provably valid, since TotalOffset == 0 makes the computed
address equal the base, so this is extra IR at -O0 rather than a change
in behaviour.
Add constant-base cases to ubsan-pointer-overflow-constant-fold.c,
including the wraps-to-zero case: it passes before this change only
because no check is emitted at all.
Assisted-by: Kiro CLI / Claude Opus 5
Commit: ae22af25cef652dd1741ae720c29d2ecdf627037
https://github.com/llvm/llvm-project/commit/ae22af25cef652dd1741ae720c29d2ecdf627037
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
WebAssembly: Move target EH passes into backend (#225172)
Currently the wasm-specific EH lowering passes are added in the
generic pass configs, driven by the TargetOptions ExceptionModel.
As preparation for driving this process off the IR flag, move these
pass runs into the target. There should be no change in the relative
pass ordering.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 8e635116824243b37aa1cce4a38b0203fad0a0e6
https://github.com/llvm/llvm-project/commit/8e635116824243b37aa1cce4a38b0203fad0a0e6
Author: 1s <zishun.yi.dev at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/test/Driver/fsanitize.c
Log Message:
-----------
[clang][FreeBSD] Enable KASAN and KMSAN for riscv64 (#202288)
enables KASAN and KMSAN for the riscv64 freebsd target in the Clang
driver.
The corresponding FreeBSD kernel runtime support for riscv64 KASAN is
currently under active review.
Depends on: https://reviews.freebsd.org/D57381
Co-authored-by: aokblast <aokblast at FreeBSD.org>
Commit: 9906c580517b6e22df73a6f7206de551e4883a52
https://github.com/llvm/llvm-project/commit/9906c580517b6e22df73a6f7206de551e4883a52
Author: geoffreygaren <ggaren at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
Log Message:
-----------
[WebKit Checkers] Trace through temporaries in tryToFindPtrOrigin (#224877)
RefPtr checking skips temporaries, reporting a path through any
temporary as unsafe. This is mostly correct, but not always. For
example, the following is a false positive:
// makeKey() returns a temporary
RefCountable* p = condition(makeKey()) ? guardian.ptr() : nullptr;
In the upcoming Borrow checker, it's even more important to trace
through temporaries because not tracing an expression can drop a
`lifetimebound` link, resulting in false **negatives**.
This patch adds tracing through temporaries. The logic is:
* In function call arguments, temporaries are lifetime safe because the
full expression does not end until the call returns
* In ranged for loops, temporaries are lifetime safe because lifetime
extends past the full expression to the duration of the loop (C++ P2718)
* Otherwise, temporaries are not lifetime safe
Assisted-by: Claude
Commit: fbbf5d2daec93118bb5e478b7d6089fbbb857f94
https://github.com/llvm/llvm-project/commit/fbbf5d2daec93118bb5e478b7d6089fbbb857f94
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/test/CodeGen/NVPTX/volatile-local.ll
Log Message:
-----------
[NVPTX] Preserve volatile on atomic local loads and stores (#224719)
Local loads and stores discard atomic ordering during instruction
selection, but volatile accesses with acquire, release, or seq_cst
ordering also lose the volatile qualifier. Preserve volatile for all
valid load/store orderings when local volatile instructions are
supported. Follow up to #217764.
Commit: 4a49d09c3358c6ac54362d9a8ef8075a4b121114
https://github.com/llvm/llvm-project/commit/4a49d09c3358c6ac54362d9a8ef8075a4b121114
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
Log Message:
-----------
[DebugInfo] Fix overflow in DWARFDebugLine::SectionParser (#224770)
Adding a DWARF64 unit length can overflow and wrap back into the
section, causing an infinite loop. Saturate the addition so an
overflowing offset fails the bounds check.
rdar://186810393
Commit: 06c7e8db78adf3a5478362ba80d6bb7f25b936b0
https://github.com/llvm/llvm-project/commit/06c7e8db78adf3a5478362ba80d6bb7f25b936b0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Simplify computeKnownBits for EXTRACT_ELEMENT using KnownBits::extractBits. NFC (#225168)
Commit: e7302d9069f007ce968f6eac0a95d0f34cfc1152
https://github.com/llvm/llvm-project/commit/e7302d9069f007ce968f6eac0a95d0f34cfc1152
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/folded-broadcast-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/reordered-gather.ll
Log Message:
-----------
[SLP] Reland: More accurately cost RISCV scalar splats (#224766)
Originally #213104, reverted due to assertion failure in cases of
reordered gather nodes.
Backends may have a fast path for splatting scalar operands (i.e. rather
than generating the splat vector, the vector instruction may be able to
take a scalar operand), for example RISCV `vfoo.vx` instructions. Pass a
hint to the TTI when costing the insert/shuffle sequence in such cases.
Fixes #212413.
Assisted By: Codex
Commit: 434b00aa1d89d276b826f40afd132308ee19277f
https://github.com/llvm/llvm-project/commit/434b00aa1d89d276b826f40afd132308ee19277f
Author: Domenic Nutile <domenic.nutile at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
A llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
A llvm/test/MC/AMDGPU/gfx11_asm_t16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
Log Message:
-----------
[AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test coverage (#223826)
Upstream new assembler test cases, covering true16 .l/.h operands and
op_sel
handling that had no upstream coverage.
Commit: aea2e768d7c2f5d97ae6a41c5c7469dcac4ba113
https://github.com/llvm/llvm-project/commit/aea2e768d7c2f5d97ae6a41c5c7469dcac4ba113
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/union.c
Log Message:
-----------
[CIR] Regenerate CHECK lines for two callconv opt-out tests (#225189)
Neither `union.c` nor `paren-list-agg-init.cpp` is blocked by the
calling convention lowering pass any more, and both compile clean with
it running. Remove the `-fno-clangir-call-conv-lowering` opt-out and
update their CHECK lines. The coerced parameters and returns they now
pin match classic.
The bodies still differ, since CIR round-trips the record through a
fresh coerce slot, so those fragments move to the `LLVMCIR` and `OGCG`
prefixes the file already declares. Four `define` lines in
`paren-list-agg-init.cpp` wildcarded their return type and now pin it.
Assisted-by: Cursor / claude-opus-5
Commit: 418bede1ebba8990349df1e17306a05bb3d75e51
https://github.com/llvm/llvm-project/commit/418bede1ebba8990349df1e17306a05bb3d75e51
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/NativeDylibManagerSPSCI.h
M llvm/unittests/ExecutionEngine/Orc/EPCGenericDylibManagerTest.cpp
Log Message:
-----------
[ORC] Mangle NativeDylibManager CI names as C (#225096)
Flip the NativeDylibManager descriptors (instance + load/lookup) from
Verbatim to C, so their names carry the target's C mangling. Served by
the in-tree SimpleExecutorDylibManager; controller and executor mangle
the same specs and nothing else defines these names.
Also give the CreateFromExecutionSession test EPC the process triple,
matching the memory-manager fix (its bootstrap symbols were keyed with
the process triple but the EPC had an empty target triple).
Commit: 82cf8d465a76e9fda817906a4405fb7d18eb84d5
https://github.com/llvm/llvm-project/commit/82cf8d465a76e9fda817906a4405fb7d18eb84d5
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-22 (Tue, 22 Sep 2026)
Changed paths:
M llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ConnectionSpec.h
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ExecutionEngine/Orc/ConnectionSpecTest.cpp
Log Message:
-----------
[ORC] Rename ConnectionSpec's fd transport to socket:adopt (#225075)
A ConnectionSpec's transport field says what kind of thing the
descriptor names, and "fd" named a representation rather than a kind. It
also left no room for a pipe transport, which takes two descriptors and
a different server.
The transport becomes "socket", and adopting a handed-over handle
becomes an explicit "adopt" action rather than the absence of one. So
"tcp" names an endpoint to reach while "socket" names a handle already
held, and a spec states how the process came by its channel -- worth
spelling out, since "adopt", "connect" and "listen" do not carry the
same trust.
llvm-jitlink-executor takes "socket:adopt=<fd>" in place of "fd=<fd>"
and rejects any other action for that transport. The spec is an internal
handoff from llvm-jitlink in every in-tree use, so nothing else needed
updating. The class comment is rewritten around the same split and stops
describing transports that do not exist yet.
Matches the scheme the ORC runtime uses for its connector registry.
Commit: 9696514f547989b2688e73a987fb676d71f570aa
https://github.com/llvm/llvm-project/commit/9696514f547989b2688e73a987fb676d71f570aa
Author: Alex Duran <alejandro.duran at intel.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/test/OpenMP/nvptx_target_teams_ompx_bare_kernel_environment_codegen.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[clang][openmp] Avoid generating geometry for Bare kernels (#225185)
Don't use the information from num_teams or thread_limit clauses to
initialize the Kernel Environment of bare kernels. They only support one
single dimension and for NVIDIA (only) we generate a "nnvm.maxntid"
attribute which is incompatible with the multi-dimensional launch that
happens at runtime.
Fixes a regression introduced by #223772
Commit: e22f06e20c56cb71c00acd5372c512f54616b884
https://github.com/llvm/llvm-project/commit/e22f06e20c56cb71c00acd5372c512f54616b884
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
Log Message:
-----------
[AMDGPU] Do not match an f16 extension as a bf16 mix source (#224912)
Assisted-by: Claude Code Opus 5
Commit: 32636ffa83325ca3b3c1ae3342d66abe053ddf87
https://github.com/llvm/llvm-project/commit/32636ffa83325ca3b3c1ae3342d66abe053ddf87
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/test/CIR/CodeGen/bitfields.cpp
M clang/test/CIR/CodeGenCXX/uncopyable-args.cpp
Log Message:
-----------
[CIR] Drop the stale callconv opt-out from two CIR tests (#225180)
`bitfields.cpp` was waiting on padded, packed and over-aligned record
shapes. `uncopyable-args.cpp` was waiting on parameters of an empty or
tag class. Both files now compile and check clean with the pass running,
so the `-fno-clangir-call-conv-lowering` opt-out and its TODO header are
removed and the tests exercise the pass as written. Neither file changes
a CHECK directive.
Assisted-by: Cursor / claude-opus-5
Commit: 8374c329d2643ced8c868aabf8004c065108dfce
https://github.com/llvm/llvm-project/commit/8374c329d2643ced8c868aabf8004c065108dfce
Author: Steven Wu <stevenwu at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M .ci/green-dragon/lldb-ubuntu.groovy
M clang/CMakeLists.txt
M clang/include/clang/AST/DeclContextInternals.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Basic/BuiltinsAMDGPU.td
M clang/include/clang/Basic/FileEntry.h
M clang/include/clang/CIR/Dialect/IR/CIRAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/MissingFeatures.h
M clang/include/clang/Config/config.h.cmake
M clang/lib/AST/ASTImporter.cpp
M clang/lib/ASTMatchers/ASTMatchFinder.cpp
M clang/lib/Analysis/LifetimeSafety/Checker.cpp
M clang/lib/Analysis/LifetimeSafety/LiveOrigins.cpp
M clang/lib/CIR/CodeGen/CIRGenCXXABI.h
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
A clang/lib/CIR/CodeGen/CIRGenMicrosoftCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CMakeLists.txt
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRCXXABI.h
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CMakeLists.txt
A clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerMicrosoftCXXABI.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/LowerModule.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGCleanup.cpp
M clang/lib/CodeGen/CGCleanup.h
M clang/lib/CodeGen/CGDecl.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/EHScopeStack.h
M clang/lib/CodeGen/Targets/Sparc.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Index/FileIndexRecord.cpp
M clang/lib/Interpreter/IncrementalExecutor.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaSYCL.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaTemplateVariadic.cpp
M clang/lib/Serialization/ASTReaderStmt.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.h
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefCallArgsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/RawPtrRefLocalVarsChecker.cpp
M clang/lib/StaticAnalyzer/Core/BugSuppression.cpp
M clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp
A clang/test/CIR/CodeGen/attr-musttail-ehspec-errors.cpp
M clang/test/CIR/CodeGen/bitfields.cpp
A clang/test/CIR/CodeGen/cxx-msvc-abi.cpp
M clang/test/CIR/CodeGen/ehspec-noexcept.cpp
A clang/test/CIR/CodeGen/lowering-lang-options.cpp
A clang/test/CIR/CodeGen/noinline-available-externally-skip.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGen/union.c
M clang/test/CIR/CodeGenCXX/uncopyable-args.cpp
A clang/test/CIR/IR/lowering-lang-options.cir
M clang/test/CodeGen/AArch64/abi-classify-arg-types.c
M clang/test/CodeGen/AArch64/abi-classify-arg-types.cpp
M clang/test/CodeGen/AArch64/abi-classify-return-types.c
M clang/test/CodeGen/AArch64/abi-classify-return-types.cpp
M clang/test/CodeGen/Sparc/sparc-vaarg.c
M clang/test/CodeGen/Sparc/sparcv8-abi.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset-when-nullptr-is-defined.c
M clang/test/CodeGen/catch-nullptr-and-nonzero-offset.c
M clang/test/CodeGen/catch-pointer-overflow-volatile.c
M clang/test/CodeGen/catch-pointer-overflow.c
M clang/test/CodeGen/compound-literal-lifetime.c
M clang/test/CodeGen/ubsan-pointer-overflow-constant-fold.c
M clang/test/CodeGen/ubsan-pointer-overflow.c
M clang/test/Driver/fsanitize.c
M clang/test/OpenMP/distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/nvptx_target_teams_ompx_bare_kernel_environment_codegen.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_loop_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/target_teams_distribute_parallel_for_simd_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_loop_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_loop_messages.cpp
M clang/test/OpenMP/teams_distribute_parallel_for_simd_messages.cpp
M flang-rt/unittests/Runtime/Assign.cpp
M flang/docs/Extensions.md
M flang/include/flang/Optimizer/Support/InternalNames.h
M flang/include/flang/Parser/options.h
M flang/lib/Frontend/FrontendAction.cpp
M flang/lib/Optimizer/Support/InternalNames.cpp
M flang/lib/Parser/parsing.cpp
M flang/lib/Parser/prescan.cpp
M flang/lib/Parser/prescan.h
A flang/test/Preprocessing/fixed-c-comment01.F
A flang/test/Preprocessing/fixed-c-comment02.F
A flang/test/Preprocessing/fixed-c-comment03.f
A flang/test/Preprocessing/fixed-c-comment04.f
A flang/test/Preprocessing/fixed-c-comment05.f
A flang/test/Preprocessing/free-c-comment01.f90
M flang/tools/bbc/bbc.cpp
M flang/tools/f18-parse-demo/f18-parse-demo.cpp
M flang/unittests/Optimizer/InternalNamesTest.cpp
M lldb/cmake/modules/LLDBConfig.cmake
M lldb/docs/resources/build.md
M lldb/include/lldb/Host/Config.h.cmake
R lldb/include/lldb/Host/LZMA.h
M lldb/source/Core/Debugger.cpp
M lldb/source/Host/CMakeLists.txt
R lldb/source/Host/common/LZMA.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/Process/minidump/MinidumpParser.cpp
M lldb/test/CMakeLists.txt
M lldb/test/Shell/lit.cfg.py
M lldb/test/Shell/lit.site.cfg.py.in
M lldb/unittests/Process/minidump/MinidumpParserTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/config-ix.cmake
M llvm/cmake/modules/LLVMConfig.cmake.in
M llvm/docs/CMake.md
M llvm/docs/GlobalISel/GenericOpcode.md
M llvm/docs/ReleaseNotes.md
M llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp
M llvm/include/llvm/ABI/TargetInfo.h
M llvm/include/llvm/ABI/Types.h
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/Config/llvm-config.h.cmake
M llvm/include/llvm/ExecutionEngine/Orc/Shared/ConnectionSpec.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SPSCI/NativeDylibManagerSPSCI.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Support/Compression.h
M llvm/include/llvm/Support/TargetOpcodes.def
M llvm/include/llvm/Target/GenericOpcodes.td
M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
M llvm/lib/ABI/TargetInfo.cpp
M llvm/lib/ABI/Targets/AArch64.cpp
M llvm/lib/ABI/Types.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/WasmEHPrepare.cpp
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Compression.cpp
M llvm/lib/Support/Windows/Path.inc
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMachObjectWriter.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
M llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrFragments.td
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/test/Analysis/ScalarEvolution/exit-value-nowrap-flags.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-operand-order.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll
M llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll
M llvm/test/Analysis/ScalarEvolution/nsw.ll
M llvm/test/Analysis/ScalarEvolution/ranges.ll
M llvm/test/CMakeLists.txt
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
M llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/kcfi-bti.ll
M llvm/test/CodeGen/AArch64/sme-streaming-mode-landingpads.ll
M llvm/test/CodeGen/AMDGPU/amdpal-metadata-agpr-register-count.ll
A llvm/test/CodeGen/AMDGPU/mad-mix-bf16-t16-inline-imm.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-fptrunc-rounding.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/NVPTX/lower-byval-args.ll
M llvm/test/CodeGen/NVPTX/volatile-local.ll
A llvm/test/CodeGen/RISCV/GlobalISel/clmulr-rv32.ll
A llvm/test/CodeGen/RISCV/GlobalISel/clmulr-rv64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/X86/pr222714.ll
A llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
A llvm/test/MC/AMDGPU/gfx11_asm_t16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt
M llvm/test/MC/RISCV/riscv-relocs-macho-data.s
M llvm/test/MC/RISCV/riscv-relocs-macho.s
M llvm/test/TableGen/get-named-operand-idx.td
M llvm/test/Transforms/IndVarSimplify/exit-value-nowrap-flags.ll
M llvm/test/Transforms/InstCombine/atomic.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/check-node-without-vector-user.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/folded-broadcast-cost.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/reordered-gather.ll
A llvm/test/Transforms/SLPVectorizer/X86/trimmed-subtree-schedule.ll
M llvm/test/Transforms/SROA/phi-and-select.ll
A llvm/test/Transforms/SROA/phi-store.ll
M llvm/test/lit.site.cfg.py.in
A llvm/test/tools/llvm-dwarfdump/X86/apple-names-overflowing-entry-count.s
M llvm/tools/llvm-jitlink/llvm-jitlink-executor/llvm-jitlink-executor.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/ABI/AArch64TargetInfoTest.cpp
M llvm/unittests/ABI/TypesTest.cpp
M llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp
M llvm/unittests/ExecutionEngine/Orc/ConnectionSpecTest.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericDylibManagerTest.cpp
M llvm/unittests/Support/CompressionTest.cpp
M llvm/utils/gn/secondary/clang/include/clang/Config/BUILD.gn
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Host/BUILD.gn
M llvm/utils/gn/secondary/lldb/test/BUILD.gn
M llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn
M llvm/utils/lit/lit/llvm/config.py
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCCGToGPU.cpp
M mlir/lib/Dialect/XeGPU/Transforms/XeGPUPeepHoleOptimizer.cpp
A mlir/test/Dialect/OpenACC/acc-cg-to-gpu-thread-private-storage-remark.mlir
M mlir/test/Dialect/XeGPU/peephole-optimize.mlir
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/clang/include/clang/Config/config.h
M utils/bazel/llvm-project-overlay/lldb/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/third-party/BUILD.bazel
M utils/bazel/llvm_configs/llvm-config.h.cmake
Log Message:
-----------
fix windows attempt 3
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/e5cc0aa8b504...8374c329d264
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