[all-commits] [llvm/llvm-project] 836443: CodeGen: Compute LiveIntervals before TwoAddressIn...

Mon Sep 21 12:22:23 PDT 2026

  Branch: refs/heads/users/arsenm/codegen/compute-LiveIntervals-before-twoaddr
  Home:   https://github.com/llvm/llvm-project
  Commit: 8364433dfa0767adf9775018521e444a98d11694
      https://github.com/llvm/llvm-project/commit/8364433dfa0767adf9775018521e444a98d11694
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/Passes/CodeGenPassBuilder.cpp
    M llvm/test/CodeGen/AArch64/O3-pipeline.ll
    M llvm/test/CodeGen/AArch64/itofp-bf16.ll
    M llvm/test/CodeGen/AArch64/pr161420.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/add_i128.ll
    M llvm/test/CodeGen/AMDGPU/add_i64.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/and.ll
    M llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
    M llvm/test/CodeGen/AMDGPU/anyext.ll
    M llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll
    M llvm/test/CodeGen/AMDGPU/atomics-system-scope.ll
    M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/bitreverse.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/bswap.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll
    M llvm/test/CodeGen/AMDGPU/bypass-div.ll
    M llvm/test/CodeGen/AMDGPU/clmul.ll
    M llvm/test/CodeGen/AMDGPU/consecutive-loads-in-branch.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/ctlz.ll
    M llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
    M llvm/test/CodeGen/AMDGPU/ctpop.ll
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/ctpop64.ll
    M llvm/test/CodeGen/AMDGPU/cttz.ll
    M llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/div_v2i128.ll
    M llvm/test/CodeGen/AMDGPU/fadd.f16.ll
    M llvm/test/CodeGen/AMDGPU/fceil64.ll
    M llvm/test/CodeGen/AMDGPU/fcmp.f16.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
    M llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
    M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
    M llvm/test/CodeGen/AMDGPU/fmul.f16.ll
    M llvm/test/CodeGen/AMDGPU/fnearbyint.ll
    M llvm/test/CodeGen/AMDGPU/fptoi.i128.ll
    M llvm/test/CodeGen/AMDGPU/fptrunc.ll
    M llvm/test/CodeGen/AMDGPU/freeze.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/fshl.ll
    M llvm/test/CodeGen/AMDGPU/fsub.f16.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/idot2.ll
    M llvm/test/CodeGen/AMDGPU/idot4s.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.group.barrier.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.smfmac.gfx950.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i8.ll
    M llvm/test/CodeGen/AMDGPU/load-local-i16.ll
    M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-variables-update.mir
    M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
    M llvm/test/CodeGen/AMDGPU/mad-combine.ll
    M llvm/test/CodeGen/AMDGPU/mad_uint24.ll
    M llvm/test/CodeGen/AMDGPU/max.ll
    M llvm/test/CodeGen/AMDGPU/memintrinsic-unroll.ll
    M llvm/test/CodeGen/AMDGPU/merge-stores.ll
    M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    M llvm/test/CodeGen/AMDGPU/mul.ll
    M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
    M llvm/test/CodeGen/AMDGPU/or.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp32.ll
    M llvm/test/CodeGen/AMDGPU/packed-fp64.ll
    M llvm/test/CodeGen/AMDGPU/packed-u64.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-mfma-single-exit-copy.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-reserved-wwm-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/sdiv.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i64.ll
    M llvm/test/CodeGen/AMDGPU/shufflevector.v2i64.v8i64.ll
    M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
    M llvm/test/CodeGen/AMDGPU/sra.ll
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/AMDGPU/sub.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
    M llvm/test/CodeGen/AMDGPU/udiv.ll
    M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
    M llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll
    M llvm/test/CodeGen/AMDGPU/unspill-vgpr-after-rewrite-vgpr-mfma.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/vselect.ll
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-pattern.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/xor.ll
    M llvm/test/CodeGen/ARM/O3-pipeline.ll
    M llvm/test/CodeGen/ARM/fp-intrinsics-vector.ll
    M llvm/test/CodeGen/ARM/llvm.modf.ll
    M llvm/test/CodeGen/ARM/llvm.sincos.ll
    M llvm/test/CodeGen/ARM/vldlane.ll
    M llvm/test/CodeGen/Hexagon/cttz-elts-widen.ll
    M llvm/test/CodeGen/LoongArch/opt-pipeline.ll
    M llvm/test/CodeGen/M68k/pipeline.ll
    M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
    M llvm/test/CodeGen/PowerPC/dmr-copy.ll
    M llvm/test/CodeGen/PowerPC/dmr-enable.ll
    M llvm/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
    M llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
    M llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll
    M llvm/test/CodeGen/Thumb2/mve-clmul.ll
    M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-add.ll
    M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-f64-mul.ll
    M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-mixed-cases.ll
    M llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-uniform-cases.ll
    M llvm/test/CodeGen/Thumb2/mve-insertshuffleload.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
    M llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle-fp16.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffle.ll
    M llvm/test/CodeGen/Thumb2/mve-shuffleext.ll
    M llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
    M llvm/test/CodeGen/Thumb2/mve-vld2.ll
    M llvm/test/CodeGen/Thumb2/mve-vld3.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vld4.ll
    M llvm/test/CodeGen/Thumb2/mve-vldst4.ll
    M llvm/test/CodeGen/Thumb2/mve-vst2.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4-post.ll
    M llvm/test/CodeGen/Thumb2/mve-vst4.ll
    M llvm/test/CodeGen/Thumb2/mve-zext-masked-load.ll
    M llvm/test/CodeGen/X86/active_lane_mask.ll
    M llvm/test/CodeGen/X86/addcarry.ll
    M llvm/test/CodeGen/X86/apx/mul-i1024.ll
    M llvm/test/CodeGen/X86/apx/pr191368.ll
    M llvm/test/CodeGen/X86/apx/push2-pop2.ll
    M llvm/test/CodeGen/X86/bit-manip-i512.ll
    M llvm/test/CodeGen/X86/bitselect.ll
    M llvm/test/CodeGen/X86/clmul-vector.ll
    M llvm/test/CodeGen/X86/combine-bitselect.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/ftrunc.ll
    M llvm/test/CodeGen/X86/funnel-shift-i512.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/i128-udiv.ll
    M llvm/test/CodeGen/X86/icmp-abs-C.ll
    M llvm/test/CodeGen/X86/llc-pipeline-npm.ll
    M llvm/test/CodeGen/X86/machine-combiner-int-vec.ll
    M llvm/test/CodeGen/X86/masked-urem.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
    M llvm/test/CodeGen/X86/midpoint-int.ll
    M llvm/test/CodeGen/X86/mul-i1024.ll
    M llvm/test/CodeGen/X86/mul-i256.ll
    M llvm/test/CodeGen/X86/mul-i512.ll
    M llvm/test/CodeGen/X86/mul128.ll
    M llvm/test/CodeGen/X86/neg-abs.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/CodeGen/X86/pr46877.ll
    M llvm/test/CodeGen/X86/scalar-minmax-simd.ll
    M llvm/test/CodeGen/X86/shift-amount-mod.ll
    M llvm/test/CodeGen/X86/shift-and.ll
    M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
    M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
    M llvm/test/CodeGen/X86/ucmp.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
    M llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
    M llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
    M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
    M llvm/test/CodeGen/X86/vector-reduce-smax.ll
    M llvm/test/CodeGen/X86/vector-reduce-smin.ll
    M llvm/test/CodeGen/X86/vector-reduce-umax.ll
    M llvm/test/CodeGen/X86/vector-reduce-umin.ll
    M llvm/test/CodeGen/X86/vector-trunc-packus.ll
    M llvm/test/CodeGen/X86/wide-scalar-shift-by-byte-multiple-legalization.ll
    M llvm/test/CodeGen/X86/widen_arith-2.ll
    M llvm/test/CodeGen/X86/widen_bitcnt.ll
    M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll

  Log Message:
  -----------
  CodeGen: Compute LiveIntervals before TwoAddressInstructions

TwoAddressInstructions is the traditional primary use of LiveVariables,
but it has gained a LiveIntervals path. By moving LiveIntervals earlier,
the default flips to rely on it instead of LiveVariables. The overall
test churn is mostly neutral, with more net wins than losses.

This should move before phi elimination. This is a staging move to
incrementally remove the LiveVariables support from TwoAddressInstructions,
and because the move to running LiveIntervals on SSA is a bigger leap.

Co-authored-by: Claude (Claude-Opus-4.8)

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