[all-commits] [llvm/llvm-project] 87697a: [RISC-V][MC] Update ELF streamer ArchString when e...

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/risc-v-mc-update-elf-streamer-archstring-when-emitting
  Home:   https://github.com/llvm/llvm-project
  Commit: 87697a504b09b33d8b27f0d8428b3b10aa0d16f9
      https://github.com/llvm/llvm-project/commit/87697a504b09b33d8b27f0d8428b3b10aa0d16f9
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M cross-project-tests/riscv/lto-inline-asm-abi.c
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

  Log Message:
  -----------
  [RISC-V][MC] Update ELF streamer ArchString when emitting RISCVAttrs::ARCH

During LTO, the TargetMachine subtarget is initialized with the linker's
default CPU (e.g. `generic-rv64`, `rv64i2p1`), while
RISCVAsmPrinter::emitStartOfAsmFile() reconstructs the module's actual ISA from
the `riscv-isa` module flag and emits RISCVAttrs::ARCH via
RISCVTargetELFStreamer::emitTextAttribute(). Previously only
RISCVAsmParser::parseDirectiveAttribute() called setArchString() after
emitTextAttribute(RISCVAttrs::ARCH, ...), so direct object emission bypassed
the update and tagged `.text` with `$xrv64i2p1` instead of the module's
full architecture string.

Move the setArchString() call into RISCVTargetELFStreamer::emitTextAttribute()
when emitting RISCVAttrs::ARCH so both `.attribute arch` and
RISCVTargetStreamer::emitTargetAttributes() update the active mapping symbol
ISA.

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