[all-commits] [llvm/llvm-project] 8472e4: [flang][OpenMP] Reword some diagnostic messages, N...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Sep 21 05:44:46 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpdrop-unprofitable-splat-subtrees-before-the-profitability-trim
Home: https://github.com/llvm/llvm-project
Commit: 8472e4556c064de7251ac82e0993bdaf05978841
https://github.com/llvm/llvm-project/commit/8472e4556c064de7251ac82e0993bdaf05978841
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/test/Semantics/OpenMP/allocate_do1.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend05.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/map-modifiers-v60.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/uses-allocators-version50.f90
M flang/test/Semantics/OpenMP/uses-allocators-version51.f90
Log Message:
-----------
[flang][OpenMP] Reword some diagnostic messages, NFC (#224945)
Instead of "something...something in OpenMP vX.Y on SOME clause" say
"something...something on SOME clause in OpenMP vX.Y".
Commit: 038f5968616a3b466e790084bc72eab62d6a6743
https://github.com/llvm/llvm-project/commit/038f5968616a3b466e790084bc72eab62d6a6743
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/revec-non-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction-i1-mask.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-vf-to-resize.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP]Cost-based choice of the i1 reduction form
i1 reductions (and/or of <n x i1>, add of zexted <n x i1>) can be
emitted as the plain target reduction or in the bitcast-based form
(bitcast to the scalar int type plus a compare for and/or, plus ctpop
for add). Choose the cheaper form by cost, estimating the bitcast-based
form from its emitted components; the ctpop form is estimated as the
cheaper of the scalar bitcast+ctpop and the vector ctpop on the mask
type.
Fixes #40657
Reviewers: michaelselehov, RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/223163
Commit: 7818c91f7151a50df614fae9211eedfbfd32e938
https://github.com/llvm/llvm-project/commit/7818c91f7151a50df614fae9211eedfbfd32e938
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/test/CodeGen/PowerPC/O0-pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
M llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
M llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
M llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
M llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
M llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
M llvm/test/CodeGen/PowerPC/mi-peephole.mir
M llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
M llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
M llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
M llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
M llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
M llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
M llvm/test/CodeGen/PowerPC/sext_elimination.mir
Log Message:
-----------
PowerPC: Remove LiveVariables dependency from PPCMIPeephole (#222416)
PPCMIPeephole only used LiveVariables to keep kill/dead flags valid
after its transforms, and made no real use of the analysis.
A later LiveVariables run recomputes those flags from scratch anyway, so
just clear possbly stale kill/dead flags on changed registers.
PPCMIPeephole was the only user of LiveVariables at this point in the
pipeline, so also drop the explicit LiveVariables run before
PPCTLSDynamicCallPass, whose comment references a > 10 year old build
bot failure.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 61978757eca575e2743471ddf7bcfb7e3a3979e4
https://github.com/llvm/llvm-project/commit/61978757eca575e2743471ddf7bcfb7e3a3979e4
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll
M llvm/test/CodeGen/SPIRV/atomicrmw-storage-class-semantics.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
A llvm/test/CodeGen/SPIRV/fence-shader.ll
M llvm/test/CodeGen/SPIRV/fence.ll
M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchangeExplicit_cl20.ll
M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchange_cl20.ll
Log Message:
-----------
[SPIR-V] Add storage class bits to fence and generic atomic semantics (#223023)
A barrier only orders the memory it names, and we named none, so fences
ordered nothing
Name every class the target can reach, generic pointers had the same gap
in atomics
Commit: 87c971d36345c0ff4f7a7ae75080bd55e83e4fca
https://github.com/llvm/llvm-project/commit/87c971d36345c0ff4f7a7ae75080bd55e83e4fca
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
Log Message:
-----------
[SLP]Emit loop-carried horizontal reductions as loop vector accumulator
A reduction whose root is the backedge value of a loop accumulator phi
is emitted as a lane-wise vector accumulator in the loop plus a single
reduction in the exit blocks, instead of a horizontal reduction on every
iteration. The loop-carried dependency chain becomes lane-wise and the
reduction is paid once per loop execution.
Note: It is partial vectorization within the loop, LV cannot handle it.
SLP already does something similar with multi-register reductions,
this adds another level - phi-based loop accumulator reductions.
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/221598
Commit: 42ea27ba09c0a09acf9c942b83e09c59632c5042
https://github.com/llvm/llvm-project/commit/42ea27ba09c0a09acf9c942b83e09c59632c5042
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/test/Semantics/OpenMP/allocate_do1.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend05.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/map-modifiers-v60.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/uses-allocators-version50.f90
M flang/test/Semantics/OpenMP/uses-allocators-version51.f90
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/test/CodeGen/PowerPC/O0-pipeline.ll
M llvm/test/CodeGen/PowerPC/O3-pipeline.ll
M llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
M llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir
M llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
M llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir
M llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
M llvm/test/CodeGen/PowerPC/mi-peephole-forwarding-undef.mir
M llvm/test/CodeGen/PowerPC/mi-peephole.mir
M llvm/test/CodeGen/PowerPC/peephole-combineRLWINM-liveness.mir
M llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir
M llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir
M llvm/test/CodeGen/PowerPC/peephole-livevars-tracking.mir
M llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
M llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
M llvm/test/CodeGen/PowerPC/sext_elimination.mir
M llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll
M llvm/test/CodeGen/SPIRV/atomicrmw-storage-class-semantics.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
A llvm/test/CodeGen/SPIRV/fence-shader.ll
M llvm/test/CodeGen/SPIRV/fence.ll
M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchangeExplicit_cl20.ll
M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchange_cl20.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-root.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/revec-non-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction-i1-mask.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/loop-accumulator-reduction.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-vf-to-resize.ll
M llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/d8e0de8f4d45...42ea27ba09c0
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