[all-commits] [llvm/llvm-project] be9e98: [libc] Fix mlock, mlock2, and munlock signatures (...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Sep 21 05:37:37 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpemit-loop-carried-horizontal-reductions-as-loop-vector-accumulator
Home: https://github.com/llvm/llvm-project
Commit: be9e98270a4948e43b6555c7a5908bc9644209f1
https://github.com/llvm/llvm-project/commit/be9e98270a4948e43b6555c7a5908bc9644209f1
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M libc/include/sys/mman.yaml
M libc/src/sys/mman/linux/mlock2.cpp
M libc/src/sys/mman/mlock2.h
Log Message:
-----------
[libc] Fix mlock, mlock2, and munlock signatures (#224905)
Updated libc/include/sys/mman.yaml so the first parameter of mlock,
mlock2, and munlock is const void * rather than void *.
Updated libc/src/sys/mman/mlock2.h and
libc/src/sys/mman/linux/mlock2.cpp so the flags parameter is unsigned
int rather than int.
Assisted-by: Automated tooling, human reviewed.
Commit: f28e7b16b90e3b6e7b38a3399b279308f636f172
https://github.com/llvm/llvm-project/commit/f28e7b16b90e3b6e7b38a3399b279308f636f172
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
A llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
A llvm/test/Analysis/CostModel/X86/speculative-load.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-basic.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-load-types.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-safety.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-scalable.ll
A llvm/test/Transforms/LoopVectorize/VPlan/AArch64/early-exit-with-speculative-load-oracle.ll
M llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
Log Message:
-----------
[LV] Add tests for early-exit loops with faulting loads (NFC). (#224762)
Pre-committing the tests for using @llvm.speculative.load intrinsic in
LoopVectorize.
Commit: cd5a0a4f07c92c65b23436d38b5aa8aa150f06dc
https://github.com/llvm/llvm-project/commit/cd5a0a4f07c92c65b23436d38b5aa8aa150f06dc
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M libc/src/__support/File/file.cpp
M libc/src/__support/File/file.h
Log Message:
-----------
[libc] Move File::close out of line to file.cpp (#224901)
Moved File::close from src/__support/File/file.h into
src/__support/File/file.cpp and removed #include
"src/__support/CPP/new.h" from file.h, matching Dir::close in
src/__support/File/dir.h.
src/__support/CPP/new.h renames global operator delete via __asm__ to
__llvm_libc_delete (which calls free) for the entire translation unit
without renaming operator new. Including new.h in file.h leaked this
replacement operator delete into unit test translation units that
include file.h, causing an AddressSanitizer alloc-dealloc-mismatch in
Test::createCallable during death tests.
Assisted-by: Automated tooling, human reviewed.
Commit: 480adef267b7e225ea52b11d0e1b8516657309ff
https://github.com/llvm/llvm-project/commit/480adef267b7e225ea52b11d0e1b8516657309ff
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M lldb/bindings/interface/SBStringListExtensions.i
A lldb/test/API/python_api/sbstringlist/TestSBStringList.py
Log Message:
-----------
[lldb] Implement the `__repr__` method for SBStringList. (#224134)
It was annoying to working with `SBStringList` from the lldb python
repl, because printing it out will produce something like.
`<lldb.SBStringList; proxy of <Swig Object of type 'lldb::SBStringList
*' at 0x10556a7b0> >`.
This also implicitly implements `str(SBStringList)`.
Extend the `__getitem__` behaviour to cover integer slices. Add test
cases.
Commit: b9be4cc5100477dd5580e11808df046c08bc525b
https://github.com/llvm/llvm-project/commit/b9be4cc5100477dd5580e11808df046c08bc525b
Author: Matt <MattPD at users.noreply.github.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/test/Transforms/LoopInterchange/memory-instr-ratio.ll
Log Message:
-----------
[LoopInterchange] Avoid overflow in the memory-instruction ratio check (#214920)
populateDependencyMatrix bails out if MaxMemInstrRatio * NumInsts is
less than NumMemInstr * NumMemInstr. Both products are computed in
32-bit unsigned arithmetic and can wrap, e.g., with
-loop-interchange-max-mem-instr-ratio=2147483648 and 20 instructions the
left product wraps to 0 and the pass rejects an otherwise eligible nest.
Compute both products in uint64_t instead, which cannot overflow as all
three operands are 32 bits wide.
Assisted-by: Claude Opus 5, GPT-5.6 Sol, GPT-6 Astra, Claude Fable 5.1.
Co-authored-by: Matt P. Dziubinski <matt-p.dziubinski at hpe.com>
Commit: e1eb257d03f78c66d6055fe4b34ac5b02ab507b0
https://github.com/llvm/llvm-project/commit/e1eb257d03f78c66d6055fe4b34ac5b02ab507b0
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/ARC/ARCTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/unittests/CodeGen/MFCommon.inc
Log Message:
-----------
CodeGen: Move DataLayout computation to CodeGenTargetMachineImpl's ctor (#224894)
Commit: 5c0b781b08ac55ceb4432631add3f8965146ae86
https://github.com/llvm/llvm-project/commit/5c0b781b08ac55ceb4432631add3f8965146ae86
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
Log Message:
-----------
[NFC][AMDGPU] Add tests for fpround of fadd and fsub feeding the mix instructions (#224909)
The f32 mix patterns already fold fadd and fsub into v_mad_mix_f32 and
v_fma_mix_f32, but the f16 and bf16 forms only fold fmul, so a half or
bfloat result still pays for a separate convert.
Also cover the denormal modes an f16 result depends on and an f16
source feeding an f16 or bf16 mix. The existing mad-mix-lo and
mad-mix-hi functions now flush denormals for every type rather than
for f32 alone.
Assisted-by: Claude Code Opus 5
Commit: 6e5b86fa50d16d9d3d7cec16aebb88e449e3ee32
https://github.com/llvm/llvm-project/commit/6e5b86fa50d16d9d3d7cec16aebb88e449e3ee32
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Add VPBlockUtils::replaceSuccessor helper (NFC). (#224970)
Add a helper to redirect a single edge, keeping the successor order and
updating the predecessor links of both the old and new successor. Use it
in insertBlockBefore.
Commit: b3154dfe4786e9e6e14f9810a8af62728a9edcd0
https://github.com/llvm/llvm-project/commit/b3154dfe4786e9e6e14f9810a8af62728a9edcd0
Author: Nina Zhang <nizhang8888 at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
A llvm/test/Transforms/LoopUnroll/AMDGPU/partial-unroll-threshold.ll
Log Message:
-----------
[AMDGPU] Add partial unroll threshold function attribute (#223291)
This change adds an `amdgpu-partial-unroll-threshold` function attribute
for controlling
`TargetTransformInfo::UnrollingPreferences::PartialThreshold` on a
per-function basis.
The existing `amdgpu-unroll-threshold` function attribute initializes
`UP.Threshold`, which is used for decisions about full
unrolling. However, there is currently no corresponding AMDGPU function
attribute for configuring `UP.PartialThreshold`
independently. As a result, clients of the AMDGPU backend cannot provide
an independent per-function cost threshold for partial and runtime
unrolling.
When present, the new attribute sets the base value of
`UP.PartialThreshold` for loops in that function. This allows the cost
threshold for partial and runtime unrolling to be configured
independently of the threshold used for full unrolling. Functions that
do not use the new attribute retain their existing behavior.
The AMDGPU function attribute documentation is updated accordingly. A
regression test sets `amdgpu-unroll-threshold` to zero and
`amdgpu-partial-unroll-threshold` to 30, then verifies that the loop is
partially unrolled by a factor of two without being fully unrolled.
Commit: c1b15b54ee18d35be275f04de1a5d0c5d1cd67e3
https://github.com/llvm/llvm-project/commit/c1b15b54ee18d35be275f04de1a5d0c5d1cd67e3
Author: he32 <he at uninett.no>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/M68k.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
Log Message:
-----------
[M68k][NetBSD] Fix alignments for NetBSD/m68k. (#207602)
Linux/m68k uses the ABI from Sun Microsystems for a.out on m68k, which
aligns ints/objects/pointers/stack on 16-bit boundaries.
NetBSD/m68k on the other hand uses the ABI from SVR4 for m68k, which
aligns ints/objects/pointers/stack on 32-bit boundaries.
This is a follow-up of
https://github.com/M680x0/issues/issues/13
Commit: 0bd330675f9eb08126e467505a0800f167084473
https://github.com/llvm/llvm-project/commit/0bd330675f9eb08126e467505a0800f167084473
Author: Mintsuki <36459316+Mintsuki at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/test/Driver/baremetal.cpp
M clang/test/Driver/loongarch-toolchain.c
Log Message:
-----------
[clang][Driver] Use the bare-metal toolchain for LoongArch (#223703)
Clang did not handle loongarch32-\*-none-elf and loongarch64-\*-none-elf
in the
bare-metal toolchain, so these targets fell back to the generic ELF
toolchain,
which links by running gcc. Any -fuse-ld or --ld-path option is
forwarded to
gcc, and linking fails when there is no gcc. On a host whose gcc does
not target
LoongArch, which is the usual case when cross compiling, gcc drives the
linker
for the host, and the link fails with errors such as "a.o is
incompatible with
elf_x86_64". The generic ELF toolchain also searches /usr/local/include
and
/usr/include of the host.
The other bare-metal targets, Arm, AArch64, RISC-V, PowerPC, and x86
since
25f0d08bafa4, use the bare-metal toolchain, which runs the selected
linker
directly and does not search host include directories.
Handle LoongArch there as well. As the GNU toolchain does for LoongArch,
and the
bare-metal toolchain already does for RISC-V, pass -X to the linker, and
--no-relax with -mno-relax.
Assisted-by: Claude Code (Claude Opus 5)
Signed-off-by: Mintsuki <mintsuki at protonmail.com>
Commit: f970f59a9d4e6b8738547d01bc33e8a12df5244b
https://github.com/llvm/llvm-project/commit/f970f59a9d4e6b8738547d01bc33e8a12df5244b
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/AST/Type.cpp
A clang/test/Modules/concept-specialization-deserialization.cppm
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
Log Message:
-----------
[C++20] [Modules] Profiling non dependent noexcept expression by pointer (#224528)
Another approach to solve
https://github.com/llvm/llvm-project/issues/191361 and
https://github.com/llvm/llvm-project/issues/224180 than
https://github.com/llvm/llvm-project/pull/222148
I want to avoid competing PR but I do feel the original one's approach
seems too workaround. And I want to emphasize that, in my experience,
finding the root cause is much more harder than find the solution to me.
Many thanks to @ispeters
For the approach itself, I described them in the comments of the PR.
Note that the real problem is we were profiling something is not
completely deserialized, so that even if it is not crash, the logic is
not correct.
Commit: 316d12deb7725d55f90c01b72799df18a7d71d81
https://github.com/llvm/llvm-project/commit/316d12deb7725d55f90c01b72799df18a7d71d81
Author: Trevor Gross <tg at trevorgross.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M compiler-rt/lib/builtins/extendhfsf2.c
M compiler-rt/lib/builtins/fp_extend.h
M compiler-rt/lib/builtins/fp_trunc.h
M compiler-rt/lib/builtins/truncsfhf2.c
M llvm/include/llvm/IR/RuntimeLibcalls.td
Log Message:
-----------
[compiler-rt] Use integers for __gnu_h2f_ieee and __gnu_f2h_ieee (#220167)
In libgcc, these conversion routines use integers in the signature. In
practice compiler-rt's definition has worked because the AAPCS calling
convention passes and returns floats the same as the same-sized integer,
but this may not be the case on all platforms. Thus, update the
signatures to match GCC.
This new version calls the inlined functions directly., changing the
generated code from:
00000000 <__extendhfsf2>:
0: ee100a10 vmov r0, s0
4: e1a01000 mov r1, r0
<snip>
60: e1800001 orr r0, r0, r1
64: ee000a10 vmov s0, r0
68: e12fff1e bx lr
0000006c <__gnu_h2f_ieee>:
6c: e92d4800 push {fp, lr}
70: ee000a10 vmov s0, r0
74: ebfffffe bl 0 <__extendhfsf2>
78: ee100a10 vmov r0, s0
7c: e8bd8800 pop {fp, pc}
To:
00000000 <__extendhfsf2>:
0: ee100a10 vmov r0, s0
4: e1a01000 mov r1, r0
<snip>
60: e1800001 orr r0, r0, r1
64: ee000a10 vmov s0, r0
68: e12fff1e bx lr
0000006c <__gnu_h2f_ieee>:
6c: e1a01000 mov r1, r0
70: e7e42550 ubfx r2, r0, #10, #5
<snip>
c8: e1800001 orr r0, r0, r1
cc: e12fff1e bx lr
This avoids an unnecessary indirection and register shuffle when calling
`__gnu_h2f_ieee`. It does mean the code is effectively duplicated
however, since any given target will only ever use `__gnu_h2f_ieee` or
`__extendhfsf2` but never mix them, this is an improvement in the final
binary. (The same logic applies to `__gnu_f2h_ieee` and `__truncsfhf2`.)
Commit: bf73ea1468d190513fb887ffad08b36a1986b12c
https://github.com/llvm/llvm-project/commit/bf73ea1468d190513fb887ffad08b36a1986b12c
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
M llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
M llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
M llvm/test/CodeGen/MLRegAlloc/default-eviction-advisor.ll
M llvm/test/CodeGen/MLRegAlloc/default-priority-advisor.ll
Log Message:
-----------
[MLGO] Diagnose unavailable ML advisors under the new pass manager (#224585)
Without an ML model there is no release or development advisor
The legacy pass manager says so and uses the default advisor, but the
new one just crashed
Commit: 328836b340124fc45e8529d64bbd11d1de03d228
https://github.com/llvm/llvm-project/commit/328836b340124fc45e8529d64bbd11d1de03d228
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
Log Message:
-----------
[CIR][ABI] Honor abi::ArgInfo::CanBeFlattened in the call-conv lowering (#220579)
**Summary:**
- CanBeFlattened landed on abi::ArgInfo in main
(llvm/llvm-project#220558).
- Consume the abi::ArgInfo::CanBeFlattened flag in the CIR
call-convention lowering bridge.
Assisted by: Claude Opus 4.8
Commit: 5005bb7eb5d8517e9b476d94760269356a7e87d9
https://github.com/llvm/llvm-project/commit/5005bb7eb5d8517e9b476d94760269356a7e87d9
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
Log Message:
-----------
[clang][bytecode] Check diagnosing() before calling diagnoseUnknownDecl() (#224906)
We can save some small preparations this way, e.g. calling
`getRootVarDecl()`.
Commit: 5e9e32dfeb4376adfe5e118080c73b170429e83a
https://github.com/llvm/llvm-project/commit/5e9e32dfeb4376adfe5e118080c73b170429e83a
Author: lrzlin <linrunze at loongson.cn>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
A llvm/test/CodeGen/LoongArch/frame-base-dedup-la32.mir
A llvm/test/CodeGen/LoongArch/frame-base-dedup-la64.mir
M llvm/test/CodeGen/LoongArch/stack-clash-prologue.ll
Log Message:
-----------
[LoongArch] Introduce PseudoAddUpperImm to deduplicate stack-frame base address materialization (#217250)
This is largely inspired by
https://github.com/llvm/llvm-project/pull/211748, except some LoongArch
specific changes, which includes merge 12-bit signed immediate into
`ld/st` instructions while materializing the frame index first to
generate a `lu12i.w + add` combo if we could, instead of a `lu12i.w +
ori + add`. So that we could use a `PseudoAddUpperImm` to replace them
for `MachineLateInstrsCleanup` to deduplicate them later on.
This patch improves SPEC CPU2026 `709.cactus_r` performance by 27% (from
1.64 to 2.09).
**edit:** After replacing some `ld/st` with `ldptr/stptr` as long as
their address offset could not fit in 12-bit imm but could fit in 14-bit
one, the `709.cactus_r` slightly improved from **2.09** to **2.16**,
however this is done by `-O3 -mlasx`, with `-O3 -mlsx`, the score
remains at **2.31**, which shows its bottleneck is no longer on address
materialization.
Commit: c1324c4b3404119e3128874351eebb3400c2b5c0
https://github.com/llvm/llvm-project/commit/c1324c4b3404119e3128874351eebb3400c2b5c0
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Semantics/check-allocate.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/tools.cpp
A flang/test/Lower/CUDA/cuda-gpu-managed-components-order.cuf
A flang/test/Lower/CUDA/cuda-gpu-managed-components.cuf
Log Message:
-----------
[flang][cuda] Implicitly attribute ALLOCATABLE/POINTER components as managed (#223087)
Under `-gpu=mem:managed`, `resolve-names` implicitly attributes
allocatables and
pointers declared in an ordinary scope as managed.
Apply the same attribution to components in `Post(ComponentDecl)`. An
explicitly
attributed component keeps its own attribute, and a translation unit
without
CUDA Fortran enabled is left alone.
Commit: a3d0da5c2c3cbfc1fc2d569700fd1a6b30c751dc
https://github.com/llvm/llvm-project/commit/a3d0da5c2c3cbfc1fc2d569700fd1a6b30c751dc
Author: Yangyu Chen <cyy at cyyself.name>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/cmov-unpredictable-flag.mir
A llvm/test/CodeGen/X86/cmov-unpredictable-mem.mir
Log Message:
-----------
[X86] Preserve node flags when combineCMov rebuilds a CMOV (#223469)
Commit: 5a50c15fa686c9c49b78631ac42b133340867ae3
https://github.com/llvm/llvm-project/commit/5a50c15fa686c9c49b78631ac42b133340867ae3
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M mlir/include/mlir/Pass/PassOptions.h
Log Message:
-----------
[Support] Remove cl::Sink (#224953)
Nothing uses it: the last users, clang's offloading linker wrappers,
moved to OptTable. The feature would block migration to TableGen based
representation. An unknown option is now always an error.
LLM-aided
Commit: 32150a848d65af432361296bd4a2d7b7de6f01e1
https://github.com/llvm/llvm-project/commit/32150a848d65af432361296bd4a2d7b7de6f01e1
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/AST/OpenMPClause.h
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Serialization/ASTReader.cpp
Log Message:
-----------
[Clang][OpenMP] NFC: Eliminate `Create/CreateEmpty` for scalar clause (#224935)
Use a normal constructor when the clause has a fixed size.
Keep `Create/CreateEmpty` only when the object needs extra tail storage.
Covers: `looprange, full, partial, bind, depobj, align`
Commit: c64686f1f0cce966ac00480dc4d1a91702536145
https://github.com/llvm/llvm-project/commit/c64686f1f0cce966ac00480dc4d1a91702536145
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Sema/SemaOpenMP.cpp
Log Message:
-----------
[Clang][OpenMP][NFC] Use `getLimitedValue` for loop transform counts (#224940)
Use `getLimitedValue()` when reading integer counts for `unroll, split,
interchange, fuse` transforms.
It avoids direct `getZExtValue()` calls and follows the existing OpenMP
count handling style.
Commit: ea52030d57087b910f6fcfe0fa5206969b48ffbd
https://github.com/llvm/llvm-project/commit/ea52030d57087b910f6fcfe0fa5206969b48ffbd
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip.s
Log Message:
-----------
[RISCV][MC] Reject invalid combined immediates for `cv.insert` (#224985)
The CV32E40P specification requires `Is3 + Is2 < 32` for `cv.insert`.
This commit fixes the MC part problem in LLVM.
Link:
https://github.com/openhwfoundation/cv32e40p/blob/cv32e40p_v1.8.3/docs/source/instruction_set_extensions.rst#L600-L604
Commit: 3eaddb5735f63ac1bfe5e27400f457fc38435fb4
https://github.com/llvm/llvm-project/commit/3eaddb5735f63ac1bfe5e27400f457fc38435fb4
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/CMakeLists.txt
M llvm/lib/Target/SystemZ/SystemZ.h
A llvm/lib/Target/SystemZ/SystemZAlignGlobals.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/test/CodeGen/SystemZ/la-01.ll
Log Message:
-----------
[SystemZ] Try to align globals to at least 2 bytes (#224586)
s390x has a minimum ABI alignment of 2 for globals. However, private
globals introduced by optimizations (including directly in the frontend
in the case of promotion of large const variables) are not required to
respect this ABI alignment. To avoid having to go through GOT to load an
unaligned addressed, we should try to raise the alignment of such
globals in the backend. This is done through a new SystemZ-specific
module pass.
Commit: 7d8c2a2f3436df5c564b61b75cd472f2c4a18a7e
https://github.com/llvm/llvm-project/commit/7d8c2a2f3436df5c564b61b75cd472f2c4a18a7e
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/test/CodeGenCXX/new_hot_cold.cpp
M clang/test/CodeGenCXX/operator-new.cpp
Log Message:
-----------
[Clang] Do not apply inaccessiblememonly to ::operator new() (#224316)
Do not apply `memory(inaccessiblemem: readwrite, errnomem: write)` to
`::operator new()` style calls (as opposed to `new T`). This matches the
cases where we mark the call as `builtin`, i.e. we only consider it
inaccessiblememonly in the cases where the allocation is also elidable.
I've left the old `noalias` handling alone, so that part keeps being
applied to `::operator new()` as before. Let me know if I should move
that to EmitNewDeleteCall() as well.
Commit: 01e57356732a91d804114acf4cb389d89e9f9635
https://github.com/llvm/llvm-project/commit/01e57356732a91d804114acf4cb389d89e9f9635
Author: Aleksandr Platonov <platonov.aleksandr at huawei.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/Diagnostics.cpp
M clang-tools-extra/clangd/Diagnostics.h
M clang-tools-extra/clangd/FeatureModule.h
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/Preamble.cpp
M clang-tools-extra/clangd/unittests/FeatureModulesTests.cpp
Log Message:
-----------
[clangd] Extend FeatureModule hooks (#221054)
Feature modules may need to participate at points in AST construction
that `beforeExecute()` and `sawDiagnostic()` cannot represent.
This PR adds:
- `beforePPCallbacks()` for installing preprocessing observers before
clangd starts collecting include and macro events.
- `afterExecute()` for work that needs a completed AST after token
collection and traversal-scope restriction.
- `finalizeDiagnostic()` for transformations that need the complete
diagnostic, including its notes and fixes.
For example, clang-tidy needs to register preprocessing callbacks before
preamble events are replayed, run AST matchers after clangd restricts
the traversal scope, and process diagnostics after their notes and fixes
are attached.
These changes prepare moving the clang-tidy implementation into a
FeatureModule.
RFC:
https://discourse.llvm.org/t/rfc-clangd-move-clang-tidy-integration-into-a-featuremodule/91707
Commit: 1784573db1506040f89bc476fc490ce104206380
https://github.com/llvm/llvm-project/commit/1784573db1506040f89bc476fc490ce104206380
Author: ArdenYang <ardenyang0125 at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
M mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
M mlir/test/Target/LLVMIR/Import/import-failure.ll
M mlir/test/Target/LLVMIR/Import/metadata-loop.ll
M mlir/test/Target/LLVMIR/loop-metadata.mlir
Log Message:
-----------
[mlir][LLVMIR] Fix loop follow-up metadata import and export (#223376)
## Problem
MLIR currently exports loop follow-up metadata by wrapping its
properties in an additional self-referencing loop ID:
```llvm
!1 = !{!"llvm.loop.unroll.followup_unrolled", !2}
!2 = distinct !{!2, !3}
!3 = !{!"llvm.loop.mustprogress"}
```
LLVM expects the properties directly after the follow-up name:
```llvm
!1 = !{!"llvm.loop.unroll.followup_unrolled", !3}
!3 = !{!"llvm.loop.mustprogress"}
```
`makeFollowupLoopID` copies the follow-up operands without unwrapping a
nested loop ID. Consequently, properties such as
`llvm.loop.mustprogress` inside the extra wrapper are not recognized as
properties of the resulting loop.
## Changes
- Export follow-up properties directly, excluding the temporary loop
ID's self-reference.
- Update import to read direct property lists.
- Preserve explicitly empty follow-ups, multiple properties, nested
follow-ups, and debug locations.
- Diagnose malformed follow-up metadata and detect cycles to prevent
infinite recursion.
An explicitly empty follow-up is different from an absent follow-up: it
specifies an empty configuration instead of leaving the transformation
to use its default follow-up attributes. Import therefore preserves it
as a non-null, empty `LoopAnnotationAttr`.
This patch corrects MLIR's representation of existing LLVM follow-up
metadata. It does not change LLVM's transformation policies or introduce
automatic attribute inheritance.
## Testing
Built `mlir-translate`, `FileCheck`, `count`, and `not` on Linux using a
Release build with assertions enabled.
All three targeted regression tests passed:
- `mlir/test/Target/LLVMIR/loop-metadata.mlir`
- `mlir/test/Target/LLVMIR/Import/metadata-loop.ll`
- `mlir/test/Target/LLVMIR/Import/import-failure.ll`
`git diff --check` also passed. The full MLIR test suite was not run.
Assisted-by: OpenAI Codex
---------
Co-authored-by: yangzihan <yangzihan at sunmmio.com>
Commit: fe62ed5134de05e1ac19ce914b15797c95eee0dd
https://github.com/llvm/llvm-project/commit/fe62ed5134de05e1ac19ce914b15797c95eee0dd
Author: Dharuni R Acharya <125176188+DharuniRAcharya at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm100f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm110f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm120f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm90a.py
M llvm/test/CodeGen/NVPTX/wmma.py
Log Message:
-----------
[NVPTX] Add support for ldmatrix extensions introduced in PTX 9.4 (#224264)
This patch adds support for `.s8.s4` types for `ldmatrix` instruction
for `.m8n16` shape introduced in PTX 9.4.
PTX ISA Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#warp-level-matrix-instructions-ldmatrix
---------
Signed-off-by: DharuniRAcharya <dharunira at nvidia.com>
Commit: 8f0baab45375336f4c972c4800376a4938da0d97
https://github.com/llvm/llvm-project/commit/8f0baab45375336f4c972c4800376a4938da0d97
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
Log Message:
-----------
[ORC] Drive COFFPlatform bootstrap calls via proxies (#225007)
Replace the three callSPSWrapper sites in bootstrapCOFFRuntime (platform
bootstrap, register_jitdylib, register_object_sections) with Proxy
dispatch. CI descriptors are kept local to the .cpp, since these are
COFFPlatform specific.
Commit: 5612c2710b855cccaa277890a281fdd43f3ee92b
https://github.com/llvm/llvm-project/commit/5612c2710b855cccaa277890a281fdd43f3ee92b
Author: Timur Baidusenov <timurbaidusenov at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/Intrinsics.td
A llvm/test/Transforms/GVNSink/pseudo-probe.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
Log Message:
-----------
[IR] Mark llvm.pseudoprobe arguments as immarg (#224669)
Per LangRef, llvm.pseudoprobe requires constant integer arguments.
Enforce this by marking them as immarg.
In particular, this prevents invalid sinking of llvm.pseudprobe calls in
GVNSink, which would introduce a phi node for a pseudoprobe argument.
Fixes #166306.
Commit: 2ef17d9c2d8090771aecac3e2e0738eeedd38768
https://github.com/llvm/llvm-project/commit/2ef17d9c2d8090771aecac3e2e0738eeedd38768
Author: David Green <david.green at arm.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
A llvm/test/CodeGen/X86/masked-store-illegal-type.ll
M llvm/test/CodeGen/X86/pr179489.ll
M llvm/test/CodeGen/X86/pr46532.ll
Log Message:
-----------
[DAG] Optimize masked store of constant lane mask to standard store (#224255)
A masked store with a constant mask enabling the first n lanes can be
lowered to a standard store of size n.
For example a masked store with masks `<1, 1, 0, 0>` or a scalable store
with mask `llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 2)`
This is a recommit of #223665 with a legal type check to protect against
v1f64 stores on X86 with +avx512.
Commit: 42b886e3f1b8c0f90f69ec16d2945dde8bfeae06
https://github.com/llvm/llvm-project/commit/42b886e3f1b8c0f90f69ec16d2945dde8bfeae06
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/lib/Support/CommandLine.cpp
M llvm/unittests/Support/CommandLineTest.cpp
M mlir/test/Dialect/SparseTensor/external_direct.mlir
Log Message:
-----------
[Support] Accept only true, false, 1 and 0 for cl::opt<bool> (#224975)
For these internal developer options, accepting `-flag=` (empty
value)/`-flag=True`/`-flag=FALSE` is a weird quirk. To the best of my
knowledge, they are nearly never used. Drop the spellings. In the
future, we will migrate to `-flag`/`-no-flag` (or their double-dash
form).
LLM-aided
Commit: 50a32fcc14d36ecddf3b602530f0e615be9c9aa8
https://github.com/llvm/llvm-project/commit/50a32fcc14d36ecddf3b602530f0e615be9c9aa8
Author: Mariya Podchishchaeva <Mariya.Podchishchaeva at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
A clang/test/CIR/CodeGen/target-lowering-dead-block.cpp
Log Message:
-----------
[CIR] Unreacheable blocks should be target lowered (#224609)
Similar to CXXABILowering and LowerToLLVM, target lowering should also
transform unreacheable blocks to avoid legalization failures.
Commit: 3c85ce724f447a7c2e439d05817b440cb872edd3
https://github.com/llvm/llvm-project/commit/3c85ce724f447a7c2e439d05817b440cb872edd3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
M llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
Log Message:
-----------
LoongArch: Simplify handling of call pseudo operands when expanding. (#224824)
copyImplicitOperands isn't really intended for the call instruction case
where there are also variadic operands. This avoids duplicating the R1
implicit-def operand when expanding calls. This avoids having mixed dead
and not dead flags on the same register, which will fail a future
verifier check.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 8f223ba273618835333666ada2a0c3145010f15b
https://github.com/llvm/llvm-project/commit/8f223ba273618835333666ada2a0c3145010f15b
Author: Jared Wyles <jared.wyles at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/include/orc-rt-c/support/Compiler.h
M orc-rt/include/orc-rt-internal/tools/OptionParser.h
M orc-rt/include/orc-rt/support/BitmaskEnum.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/ExecutorAddress.h
M orc-rt/include/orc-rt/support/bit.h
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/lib/bedrock/sps/AllSPSCI.cpp
A orc-rt/lib/bedrock/sys/windows/DynamicLibrary.cpp
A orc-rt/lib/bedrock/sys/windows/Memory.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
M orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
M orc-rt/test/unit/bedrock/ExecutorProcessInfoTest.cpp
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/NativeDylibManagerTest.cpp
M orc-rt/test/unit/bedrock/SimpleNativeMemoryMapTest.cpp
M orc-rt/test/unit/bedrock/sps/NativeDylibManagerSPSCITest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleNativeMemoryMapSPSCITest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
M orc-rt/test/unit/bedrock/sys/TargetTripleTest.cpp
M orc-rt/test/unit/support/CallableTraitsHelperTest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/bit-test.cpp
M orc-rt/test/unit/tools/OptionParserTest.cpp
Log Message:
-----------
[orc-rt] msvc portability (#224512)
1. designated initializers are not supported under c++17 in msvc. Clang
seems to support them.
2. Fixed constexpr issues requiring everything to be constexpr in msvc.
Mostly the bit changes.
3. Add stubs for all the platform specific code, they will land in
separate patches.
4. Enabling RTTI/Exceptions for lib and tests.
5. Disable and fix up tests so they can compile and pass, future PRs
will enable and make work properly.
6. Fixed some protection issues in simpleCA.
7. Removed posix only files and darwin only files.
Various other small fixes as necessary to get compiling.
Commit: b67d4ccd1ecdecb5a625e41ee9035eac5ae14652
https://github.com/llvm/llvm-project/commit/b67d4ccd1ecdecb5a625e41ee9035eac5ae14652
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
Log Message:
-----------
[VPlan] Move getConstantStride to vputils (NFC). (#224972)
Move the helper from VPlanTransforms.cpp to vputils, so it can also be
used from other VPlan files.
Commit: cf40ab1dc19aa9b42e0725fec1e5cf34f898a4d4
https://github.com/llvm/llvm-project/commit/cf40ab1dc19aa9b42e0725fec1e5cf34f898a4d4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/WebAssembly.cpp
R clang/test/CodeGen/WebAssembly/exception-model-flag.c
M clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-parse-ir-input.ll
M clang/test/CodeGen/exception-model-flag.c
M clang/test/CodeGenCXX/builtins-eh-wasm.cpp
M clang/test/CodeGenCXX/wasm-eh.cpp
M clang/test/CodeGenObjC/wasm32-eh-arc.m
M clang/test/CodeGenObjC/wasm32-eh.m
M clang/test/CodeGenObjCXX/wasm32-eh-objcxx.mm
M clang/test/Driver/wasm-toolchain.c
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj-phi.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj.ll
M llvm/test/CodeGen/WebAssembly/null-streamer.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-em-sjlj-error.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-invalid-personality.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-sjlj-setjmp-within-catch.ll
Log Message:
-----------
WebAssembly: Remove -wasm-enable-eh cl::opt in favor of -exception-model=wasm (#224313)
The -wasm-enable-eh backend flag was redundant with
-exception-model=wasm: every caller paired the two, and the model already
carries the intent.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 0b665c8649f49dc8e44bec3540694b1662c16ea9
https://github.com/llvm/llvm-project/commit/0b665c8649f49dc8e44bec3540694b1662c16ea9
Author: Yangyu Chen <cyy at cyyself.name>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/cmov-unpredictable-flag.mir
M llvm/test/CodeGen/X86/cmov-unpredictable-mem.mir
Log Message:
-----------
[X86] Fix cmov-unpredictable MIR tests under expensive checks (#225011)
The machine functions have no body, so the MIR parser sets NoVRegs and
leaves TracksLiveness unset, and the verifier rejects the vregs created
by instruction selection. Declare tracksRegLiveness: true and noVRegs:
false, and add -verify-machineinstrs to the RUN lines.
Fixes https://lab.llvm.org/buildbot/#/builders/187/builds/23887 after
#223469 (commit a3d0da5c2c3cbfc1fc2d569700fd1a6b30c751dc).
Assisted-by: Claude Code:claude-fable-5-1
Commit: 3783db502a743ff25462590010c4d91d17c918b3
https://github.com/llvm/llvm-project/commit/3783db502a743ff25462590010c4d91d17c918b3
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M lldb/source/Target/Memory.cpp
Log Message:
-----------
[lldb] [NFC] Fix unused variable warning in MemoryCache::InsertPartialLine (#224973)
A Release build (assertions disabled) warns:
```
lldb/source/Target/Memory.cpp:144:18: warning: unused variable 'line_size' [-Wunused-variable]
144 | const uint32_t line_size = m_L2_cache.GetLineByteSize();
| ^~~~~~~~~
```
`line_size` was read only inside the `assert` that checks a partial-line
insert does not cross a cache line boundary. `assert` expands to nothing
when `NDEBUG` is defined, so the variable becomes unused in that
configuration.
`llvm/docs/CodingStandards.md` covers this shape directly:
```
In the first case, the call to `V.size()` is only useful for the assert,
and we don't want it executed when assertions are disabled. Code like
this should move the call into the assert itself.
```
so call `GetLineByteSize()` in the assert and drop the local.
Verified by building `lldb/source/Target/Memory.cpp` with
`-DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=OFF`: the warning
above reproduces before this change and is gone after it, with a clean
rebuild of the same object file.
Commit: 462f83ce4fff5d7fef0e6beb6b8bb2e568a5d13f
https://github.com/llvm/llvm-project/commit/462f83ce4fff5d7fef0e6beb6b8bb2e568a5d13f
Author: Victor Campos <victor.campos at arm.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/test/CodeGen/builtin-clear-padding-codegen.c
M clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
Log Message:
-----------
[Clang] Fix padding clearing logic for packed boolean vectors in big endian (#224033)
The memory layout of packed boolean vectors in big endian mode is quite
involved. This patch adds support for determining the occupied bits of
this type in big endian mode, so that the correct bits are cleared as
padding.
Commit: 622e816cb4bf94ea99e2f1763c5c16b061ec80e2
https://github.com/llvm/llvm-project/commit/622e816cb4bf94ea99e2f1763c5c16b061ec80e2
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-non-native-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
M llvm/test/Transforms/LoopVectorize/scalarized_conditional_ops_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
A llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
Log Message:
-----------
[VPlan] Fix VPInstruction::AnyOf combine undoing freeze (#223640)
There is an any-of combine for unrolled VPlans which does:
any-of (fcmp uno A, A), (fcmp uno B, B), ...-> any-of (fcmp uno A, B)
However any-of implicitly freezes each individual operand and this means
we go from `freeze (fcmp uno A, A)` to `freeze (fcmp uno A, B)` which
isn't sound: https://alive2.llvm.org/ce/z/UdQM7C
This causes miscompiles today with early exit loops that are unrolled,
see the attached test case in single-early-exit-anyof-fold.ll.
This fixes it by explicitly modelling the freeze in VPlan. There are
three places where we use AnyOf:
1) early exit loops: the freeze needs to be applied per-lane, so apply
it as `(any-of (freeze (combined-conds-to-exit)))`
2) handleMaxMinNumReductions: we need to freeze the operands to the
min/max reductions earlier since they have multiple uses introduced and
we don't check the values aren't undef
3) handleFindLastReductions: we need to freeze Cond itself since it's
got multiple uses, but I plan on fixing this in a separate PR
Fable 5.1 was used to help generate the tests
Commit: 3c8ed91159b2144284672cf490cedd7befaba3fa
https://github.com/llvm/llvm-project/commit/3c8ed91159b2144284672cf490cedd7befaba3fa
Author: Marton Moro <moro.marton at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/combine-vmnot-setcc.ll
Log Message:
-----------
[RISCV] Fold vmnot.m of an integer compare into the compare (#222553)
Fold a mask NOT of an integer vector compare into the compare by
inverting
the condition code, so `vmsne.vi` + `vmnot.m` becomes `vmseq.vi`:
(vmxor_vl (setcc_vl a, b, cc), vmset_vl) -> (setcc_vl a, b, !cc)
Only `SETCC_VL` with integer operands, one use and an undef passthru is
handled. The NOT also flips the masked-off lanes, which the inverted compare
would copy unchanged from the passthru, so the passthru must be undef.
The mask can be anything. FP compares are excluded since the inverse of an
ordered compare is unordered.
Fixes #222158
Commit: 723be9c6fceee293c9695aa07c4f9389534934e6
https://github.com/llvm/llvm-project/commit/723be9c6fceee293c9695aa07c4f9389534934e6
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/include/mlir/Analysis/DataFlow/LivenessAnalysis.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Analysis/DataFlow/LivenessAnalysis.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
A mlir/test/Transforms/isolated-region-branch-canonicalize.mlir
A mlir/test/Transforms/remove-dead-values-function-root.mlir
A mlir/test/Transforms/remove-dead-values-nested-root.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
Log Message:
-----------
[MLIR] `remove-dead-values` and RegionBranchOp canononicalizations fixes around the `IsolatedFromAbove` ops (#224831)
I have a downstream op which is both `RegionBranchOpInterface` and
`IsolatedFromAbove`, trying use `remove-dead-values` on it and
especially trying to use this op as pass root uncovered various issues.
* `LivenessAnalysis` were treating yielded values as dead
* `RegionBranchOpInterface` canonicalization were just asserting on
`IsolatedFromAbove`
* When rooting on `func.func` it would leave callers invalid.
* Subsequent canonicalization could reach outside the scope.
Commit: 9e36e5a44bb5ade74202b01246cab4231d202972
https://github.com/llvm/llvm-project/commit/9e36e5a44bb5ade74202b01246cab4231d202972
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/lib/Sema/SemaDecl.cpp
A clang/test/Modules/pr72038.cppm
Log Message:
-----------
[C++20] [Modules] Don't check redeclaration for TagUseKind::Referencekind declaration (#194546)
Close https://github.com/llvm/llvm-project/issues/72038
The reason of the issue is ISO forbids redeclaration between GMF and the
module purview.
But "struct kevent evt;" was thought to be declaration than triggers the
above issue.
In this patch, we simply not checking for cases of TagUseKind::Reference
declaration.
Commit: 16ff0ec65655a16f9a01c20d059d1e6ddb27f6b9
https://github.com/llvm/llvm-project/commit/16ff0ec65655a16f9a01c20d059d1e6ddb27f6b9
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaCXX/dllexport.cpp
M clang/test/SemaCXX/dllimport.cpp
Log Message:
-----------
Revert "[Clang] Warn about ignored dllimport on explicit instantiations" (#224971)
Reverts llvm/llvm-project#191392
Causes wrong warnings on libc++
(https://github.com/llvm/llvm-project/pull/191392#issuecomment-5752359615).
Commit: 3d144ccf9a49b8d0f73bc32b03dd1adb2cf33830
https://github.com/llvm/llvm-project/commit/3d144ccf9a49b8d0f73bc32b03dd1adb2cf33830
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/lib/ExecutionEngine/ArmSMEStubs.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
Log Message:
-----------
[mlir] Fix ArmSME ABI stub exports (#224629)
Previously, the `MLIR_ARMSMEABISTUBS_EXPORTED` macro would expand to
`__declspec(dllimport)` when building LLVM as a dylib on Windows. This
would cause a build failure since it is an incorrect annotation on a
function definition.
The intent here is to always export the symbol, so these changes use the
`LLVM_ALWAYS_EXPORT` macro, which properly expands to the right
attribute depending on the compiler / platform.
The effort to build LLVM as a dylib is tracked in #109483.
Commit: 1758952bc409011b935ed814b36e9339f65ee006
https://github.com/llvm/llvm-project/commit/1758952bc409011b935ed814b36e9339f65ee006
Author: Fabrice de Gans <Steelskin at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/SandboxIR/Region.h
M llvm/include/llvm/Support/SMTAPI.h
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[llvm] Adjust remaining LLVM_ABI annotation issues (#224619)
Following up from #224293. Some annotations cannot be automatically
adjusted by the ids-check-helper and idt:
* Only headers under llvm/include are parsed. Source files and internal
headers are not.
* Headers are parsed in release mode, so debug-only declarations are
invisible.
* idt ignores private declarations.
These were found while performing a dylib build on Windows.
The effort to build LLVM as a dylib is tracked in #109483.
Commit: 468d2e73112a8e9f5fae4e21ad53526a7dc03262
https://github.com/llvm/llvm-project/commit/468d2e73112a8e9f5fae4e21ad53526a7dc03262
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang/docs/InternalsManual.md
Log Message:
-----------
[Clang] Document when to use ExtWarn and Extension (#223440)
Commit: 419a152df732336ffac80a676a81b3cd0560936b
https://github.com/llvm/llvm-project/commit/419a152df732336ffac80a676a81b3cd0560936b
Author: SunilKuravinakop <98882378+SunilKuravinakop at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/docs/OpenMPSupport.md
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Target/LLVMIR/openmp-dispatch.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
Log Message:
-----------
[MLIR][OpenMP] Support for dispatch construct with clauses nocontext & novariants (#215877)
Support for dispatch construct with clauses nocontext & novariants clauses in MLIR
This patch adds the omp.dispatch operation to the OpenMP dialect, along
with the nocontext and novariants clauses, the verifier, and LLVM IR
translation. It is limited to the MLIR layer. Flang lowering follows in
later patches.
Part 1 of 3 of the !$omp dispatch support.
This is derived from
[203320](https://github.com/llvm/llvm-project/pull/203320) (split into 3
parts).
This also Fixes[
#203317](https://github.com/llvm/llvm-project/issues/203317)
---------
Co-authored-by: Sunil Kuravinakop <kuravina at pe31.hpc.amslabs.hpecorp.net>
Commit: 40f30ea173b50c130c01d843b612f9563ca63930
https://github.com/llvm/llvm-project/commit/40f30ea173b50c130c01d843b612f9563ca63930
Author: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/inc-of-add.ll
M llvm/test/CodeGen/X86/masked-udiv.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/sub-of-not.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-shift-lut.ll
Log Message:
-----------
[X86] Prefer sub-of-not for vector inc-of-add (#207695)
Avoids lengthening the dependency chain for vector conditional
increments by preferring sub-of-not for vectors. Keeps existing
inc-of-add for scalars.
Fixes #167441
Commit: 16cbb06c5ce1f1632b6d02346147caa17093e788
https://github.com/llvm/llvm-project/commit/16cbb06c5ce1f1632b6d02346147caa17093e788
Author: unexpectedlydefined <91391114+unexpectedlydefined at users.noreply.github.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/docs/CommandGuide/llvm-dwarfdump.md
M llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage-opt.ll
M llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage.ll
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
Log Message:
-----------
[llvm-dwarfdump][LineCov] Add --variable-coverage-maybe-undefined option (#220855)
This patch adds a `--variable-coverage-maybe-undefined` flag to
llvm-dwarfdump as part of the recently implemented feature that measures
DWARF coverage of local variables in terms of source lines. This causes
the IR-level analysis to consider variables live if they are defined on
any path, and therefore include lines where the variable may be
undefined. By default, variables must be defined on all paths to be
counted.
Additionally, it includes fixes for a few issues found by @SLTozer and
myself after merging the previous patches:
- Variables not present in the DWARF information that appear in the
baseline are now included in the output.
- The assertion that there are no `undef`/`poison` variable locations in
the IR has been removed, as in some circumstances it is possible to have
a `#dbg_declare(poison)` at `-O0`.
- A small error where entries were inserted into the file name map while
iterating through it has been fixed.
Commit: 4b99afb361a8cfd45fc17aebc637688661e9e472
https://github.com/llvm/llvm-project/commit/4b99afb361a8cfd45fc17aebc637688661e9e472
Author: Henrich Lauko <xlauko at mail.muni.cz>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/Remarks.h
Log Message:
-----------
[MLIR][NFC] Drop sentinel leftovers from DenseMapInfo<Remark> (#224612)
`DenseMap` no longer uses sentinel keys, and the `getEmptyKey` and
`getTombstoneKey` members of `DenseMapInfo<Remark>` were removed in
#200633 and #201991. Two leftovers stayed behind, the `"<EMPTY_KEY>"`
comparison at the top of `isEqual` and the static dummy `MLIRContext`
that used to back the sentinel remarks.
The comparison is also wrong. A remark literally named `<EMPTY_KEY>`
compares unequal to any other remark, including one with a matching
hash, which breaks the hash and equality contract. This change removes
both leftovers and adds a comment saying what the specialization
compares, which is location, remark name, combined category name and
kind.
No behaviour change for any remark with a normal name. Existing Remark
unit tests and `mlir/test/Pass/remark-final.mlir` cover the
specialization through `RemarkEmittingPolicyFinal`.
Assisted-by: Claude Code (Claude Fable 5.1).
Commit: cdae908ca061cc4bbf0d43a428107770102d460f
https://github.com/llvm/llvm-project/commit/cdae908ca061cc4bbf0d43a428107770102d460f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/elementwise-fma-operand1.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduced-copyable-element.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
Log Message:
-----------
[SLP]Pass operand info and context to TTI cost queries
Feed operand value info, the context instruction, cast context hints,
and the actual select condition predicate to the TTI cost queries, so
target discounts that depend on them (fused fmul/fma pricing, folded
read-modify-write, constant or uniform operands) apply to both scalar
and vector sides of the SLP cost model. Also make the reversed-store
query describe the stored value instead of the pointer, per the
getMemoryOpCost contract.
Assisted-by: Cursor
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/224931
Commit: 56e8f0393c6ace765f7ae8ca28bfe07151082a5b
https://github.com/llvm/llvm-project/commit/56e8f0393c6ace765f7ae8ca28bfe07151082a5b
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/Target/Target.td
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.td
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
A llvm/test/CodeGen/Mips/named-register-aliases.ll
M llvm/test/MC/Mips/mips-register-names-invalid.s
M llvm/test/MC/Mips/mips64-register-names-n32-n64.s
A llvm/test/TableGen/MatchRegisterAltNameWithIndex.td
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[Mips] Introduce ABI-specific register names and accessors (#224284)
To accommodate the P32/P64 ABIs, we need to separate machine registers
from ABI register names and calling-convention roles. The existing
register IDs use OABI names, even when another ABI assigns a different
role to the same physical register.
As a first step, describe OABI, NABI and PABI names with
RegAltNameIndices. Extend TableGen's AsmMatcherEmitter with the opt-in
ShouldEmitMatchRegisterAltNameWithIndex flag, which generates
MatchRegisterAltName(StringRef, unsigned AltIdx). It matches only names
associated with the selected index, allowing the same spelling to
identify different registers across ABIs.
Use the indexed matcher in shared MIPS register lookup for the assembler
and named-register lowering, retaining compatibility aliases and
diagnostics for deprecated spellings.
Add ABI accessors for argument, temporary, saved and return registers,
backed by shared register lists, and use them in lowering code. Keep the
existing register IDs and assembly/MIR spellings for now, with a TODO
for ABI-independent IDs.
Commit: 72e9d33d2945504159c8d316d12c187fc706b156
https://github.com/llvm/llvm-project/commit/72e9d33d2945504159c8d316d12c187fc706b156
Author: Valeriy Savchenko <vsavchenko at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/test/CodeGen/AArch64/arm64-zip.ll
A llvm/test/CodeGen/AArch64/vselect-widen-mask-tree.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/freeze-vector.ll
A llvm/test/CodeGen/X86/vselect-widen-mask-tree.ll
Log Message:
-----------
Reapply "[SelectionDAG] Recurse through mask expression trees in WidenVSELECTMask" (#217307)
WidenVSELECTMask currently handles only two mask shapes: a bare SETCC
or a single AND/OR/XOR of exactly two SETCCs. Anything deeper bails out
to the generic condition widening path, which often introduces
unnecessary narrow/widen roundtrips (xtn+sshll on AArch64,
packssdw+vpmovsxwd on X86).
Replace the hand-coded cases with a recursive widenMaskTree that walks
through SETCC, AND/OR/XOR, FREEZE, VECTOR_SHUFFLE, SELECT/VSELECT, and
all-ones/all-zeros BUILD_VECTORs.
I had to revert #188085 earlier this year. This PR resolves the flagged
issue and cleans up suggested approach to avoid that class of potential
errors.
Commit: 0da8b0febd7d9105a7bd8e38c576a6a469e2c40c
https://github.com/llvm/llvm-project/commit/0da8b0febd7d9105a7bd8e38c576a6a469e2c40c
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
Log Message:
-----------
[MachineScheduler](NFC) Remove separate handling for non-alias loads and stores (#224310)
The separate handling of non-alias loads and stores was always extra
complexity with no pay off. Remove this.
Split from #205689
Commit: d64a0a9effc7704962e21ede22eb0f5ba24e4390
https://github.com/llvm/llvm-project/commit/d64a0a9effc7704962e21ede22eb0f5ba24e4390
Author: Nathan Corbyn <n_corbyn at apple.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
Log Message:
-----------
[ValueTracking] Make `getUnderlyingObjectsForCodegen()` preserve unidentified objects (#224584)
In some situations, it is useful to inspect the underlying objects of a
memory operation, even if they may alias with one another. A concrete
example comes from the approach to schedule DAG construction I've been
developing (see #205689) where these objects are used to infer that a
class of control dependencies between memory operations is redundant,
whereby eliminating the compile time cost of recording them. Update
`getUnderlyingObjectsForCodegen()` to return these objects.
Split from https://github.com/llvm/llvm-project/pull/205689
Commit: 466df937833ef60bc9f549a01059869ca7143d32
https://github.com/llvm/llvm-project/commit/466df937833ef60bc9f549a01059869ca7143d32
Author: Cheng-Chieh Liu <jay87406 at gmail.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Support/APFloat.cpp
M llvm/unittests/ADT/APFloatTest.cpp
Log Message:
-----------
[APFloat] Fix sign bit corrupting exponent in unsigned FP8 formats (#223286)
`convertIEEEFloatToAPInt` unconditionally ORs the sign bit into the top
bit of the encoded value. `Float8E8M0FNU` and `Float8E5M3FNU` have no
sign bit (`hasSignedRepr = false`), so that top bit actually belongs to
the exponent field. Encoding a value with sign set therefore corrupts
the exponent, in one case colliding with the reserved NaN bit pattern.
Guard the OR with `hasSignedRepr`, matching the existing check in the
decode path (`initFromIEEEAPInt`).
Extend `ConvertLosesUnrepresentableSignAndZero` to also check
`bitcastToAPInt()` after dropping an unrepresentable sign, using `-1.0`
instead of `-2.0` so the corruption is actually visible in the bits.
Commit: 8472e4556c064de7251ac82e0993bdaf05978841
https://github.com/llvm/llvm-project/commit/8472e4556c064de7251ac82e0993bdaf05978841
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/test/Semantics/OpenMP/allocate_do1.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend05.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/map-modifiers-v60.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/uses-allocators-version50.f90
M flang/test/Semantics/OpenMP/uses-allocators-version51.f90
Log Message:
-----------
[flang][OpenMP] Reword some diagnostic messages, NFC (#224945)
Instead of "something...something in OpenMP vX.Y on SOME clause" say
"something...something on SOME clause in OpenMP vX.Y".
Commit: 038f5968616a3b466e790084bc72eab62d6a6743
https://github.com/llvm/llvm-project/commit/038f5968616a3b466e790084bc72eab62d6a6743
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/revec-non-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction-i1-mask.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-vf-to-resize.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
Log Message:
-----------
[SLP]Cost-based choice of the i1 reduction form
i1 reductions (and/or of <n x i1>, add of zexted <n x i1>) can be
emitted as the plain target reduction or in the bitcast-based form
(bitcast to the scalar int type plus a compare for and/or, plus ctpop
for add). Choose the cheaper form by cost, estimating the bitcast-based
form from its emitted components; the ctpop form is estimated as the
cheaper of the scalar bitcast+ctpop and the vector ctpop on the mask
type.
Fixes #40657
Reviewers: michaelselehov, RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/223163
Commit: 63045fbfc45cae11aa3681dad091ade49786c08f
https://github.com/llvm/llvm-project/commit/63045fbfc45cae11aa3681dad091ade49786c08f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-21 (Mon, 21 Sep 2026)
Changed paths:
M clang-tools-extra/clangd/Diagnostics.cpp
M clang-tools-extra/clangd/Diagnostics.h
M clang-tools-extra/clangd/FeatureModule.h
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/Preamble.cpp
M clang-tools-extra/clangd/unittests/FeatureModulesTests.cpp
M clang/docs/InternalsManual.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/AST/OpenMPClause.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/OpenMPClause.cpp
M clang/lib/AST/Type.cpp
M clang/lib/Basic/Targets/M68k.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGExprCXX.cpp
M clang/lib/CodeGen/CGStmtOpenMP.cpp
M clang/lib/Driver/ToolChains/BareMetal.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Serialization/ASTReader.cpp
A clang/test/CIR/CodeGen/target-lowering-dead-block.cpp
R clang/test/CodeGen/WebAssembly/exception-model-flag.c
M clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-parse-ir-input.ll
M clang/test/CodeGen/builtin-clear-padding-codegen.c
M clang/test/CodeGen/exception-model-flag.c
M clang/test/CodeGenCXX/builtin-clear-padding-codegen.cpp
M clang/test/CodeGenCXX/builtins-eh-wasm.cpp
M clang/test/CodeGenCXX/new_hot_cold.cpp
M clang/test/CodeGenCXX/operator-new.cpp
M clang/test/CodeGenCXX/wasm-eh.cpp
M clang/test/CodeGenObjC/wasm32-eh-arc.m
M clang/test/CodeGenObjC/wasm32-eh.m
M clang/test/CodeGenObjCXX/wasm32-eh-objcxx.mm
M clang/test/Driver/baremetal.cpp
M clang/test/Driver/loongarch-toolchain.c
M clang/test/Driver/wasm-toolchain.c
A clang/test/Modules/concept-specialization-deserialization.cppm
A clang/test/Modules/pr72038.cppm
M clang/test/SemaCXX/dllexport.cpp
M clang/test/SemaCXX/dllimport.cpp
M clang/unittests/Serialization/LoadSpecLazilyTest.cpp
M compiler-rt/lib/builtins/extendhfsf2.c
M compiler-rt/lib/builtins/fp_extend.h
M compiler-rt/lib/builtins/fp_trunc.h
M compiler-rt/lib/builtins/truncsfhf2.c
M flang/docs/OpenMPSupport.md
M flang/include/flang/Semantics/symbol.h
M flang/lib/Lower/Allocatable.cpp
M flang/lib/Semantics/check-allocate.cpp
M flang/lib/Semantics/check-omp-syntax.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/tools.cpp
A flang/test/Lower/CUDA/cuda-gpu-managed-components-order.cuf
A flang/test/Lower/CUDA/cuda-gpu-managed-components.cuf
M flang/test/Semantics/OpenMP/allocate_do1.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Semantics/OpenMP/depend05.f90
M flang/test/Semantics/OpenMP/depobj-construct-v52.f90
M flang/test/Semantics/OpenMP/from-clause-v45.f90
M flang/test/Semantics/OpenMP/map-modifiers-v60.f90
M flang/test/Semantics/OpenMP/to-clause-v45.f90
M flang/test/Semantics/OpenMP/uses-allocators-version50.f90
M flang/test/Semantics/OpenMP/uses-allocators-version51.f90
M libc/include/sys/mman.yaml
M libc/src/__support/File/file.cpp
M libc/src/__support/File/file.h
M libc/src/sys/mman/linux/mlock2.cpp
M libc/src/sys/mman/mlock2.h
M lldb/bindings/interface/SBStringListExtensions.i
M lldb/source/Target/Memory.cpp
A lldb/test/API/python_api/sbstringlist/TestSBStringList.py
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CommandGuide/llvm-dwarfdump.md
M llvm/docs/CommandLine.md
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/CodeGen/CodeGenTargetMachineImpl.h
M llvm/include/llvm/CodeGen/RegAllocEvictionAdvisor.h
M llvm/include/llvm/CodeGen/RegAllocPriorityAdvisor.h
M llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
M llvm/include/llvm/DTLTO/DTLTO.h
M llvm/include/llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h
M llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h
M llvm/include/llvm/IR/Intrinsics.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/RuntimeLibcalls.td
M llvm/include/llvm/SandboxIR/Region.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/include/llvm/Support/SMTAPI.h
M llvm/include/llvm/Target/Target.td
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
M llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
M llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
M llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
M llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/StackColoring.cpp
M llvm/lib/ExecutionEngine/Orc/COFFPlatform.cpp
M llvm/lib/Support/APFloat.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
M llvm/lib/Target/ARC/ARCTargetMachine.cpp
M llvm/lib/Target/ARM/ARMTargetMachine.cpp
M llvm/lib/Target/AVR/AVRTargetMachine.cpp
M llvm/lib/Target/BPF/BPFTargetMachine.cpp
M llvm/lib/Target/CSKY/CSKYTargetMachine.cpp
M llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
M llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp
M llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp
M llvm/lib/Target/M68k/M68kTargetMachine.cpp
M llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
M llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
M llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
M llvm/lib/Target/Mips/Mips.td
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsMachineFunction.cpp
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.cpp
M llvm/lib/Target/Mips/MipsRegisterInfo.td
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsTargetMachine.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcTargetMachine.cpp
M llvm/lib/Target/SystemZ/CMakeLists.txt
M llvm/lib/Target/SystemZ/SystemZ.h
A llvm/lib/Target/SystemZ/SystemZAlignGlobals.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/VE/VETargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Target/XCore/XCoreTargetMachine.cpp
M llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
M llvm/lib/TargetParser/TargetDataLayout.cpp
M llvm/lib/Transforms/Scalar/LoopInterchange.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPMemoryUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.h
A llvm/test/Analysis/CostModel/AArch64/speculative-load.ll
A llvm/test/Analysis/CostModel/X86/speculative-load.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
A llvm/test/CodeGen/AArch64/vselect-widen-mask-tree.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-basic.ll
M llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll
A llvm/test/CodeGen/LoongArch/frame-base-dedup-la32.mir
A llvm/test/CodeGen/LoongArch/frame-base-dedup-la64.mir
M llvm/test/CodeGen/LoongArch/stack-clash-prologue.ll
M llvm/test/CodeGen/LoongArch/test_bl_fixupkind.mir
M llvm/test/CodeGen/MLRegAlloc/default-eviction-advisor.ll
M llvm/test/CodeGen/MLRegAlloc/default-priority-advisor.ll
A llvm/test/CodeGen/Mips/named-register-aliases.ll
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm100f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm110f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm120f.py
A llvm/test/CodeGen/NVPTX/wmma-ptx94-sm90a.py
M llvm/test/CodeGen/NVPTX/wmma.py
A llvm/test/CodeGen/RISCV/rvv/combine-vmnot-setcc.ll
M llvm/test/CodeGen/SystemZ/la-01.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh-legacy.mir
M llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll
M llvm/test/CodeGen/WebAssembly/eh-lsda.ll
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.ll
M llvm/test/CodeGen/WebAssembly/exception-legacy.mir
M llvm/test/CodeGen/WebAssembly/exception.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj-phi.ll
M llvm/test/CodeGen/WebAssembly/lower-wasm-ehsjlj.ll
M llvm/test/CodeGen/WebAssembly/null-streamer.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-em-sjlj-error.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-invalid-personality.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-prepare.ll
M llvm/test/CodeGen/WebAssembly/wasm-eh-sjlj-setjmp-within-catch.ll
M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
A llvm/test/CodeGen/X86/cmov-unpredictable-flag.mir
A llvm/test/CodeGen/X86/cmov-unpredictable-mem.mir
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/freeze-vector.ll
M llvm/test/CodeGen/X86/inc-of-add.ll
A llvm/test/CodeGen/X86/masked-store-illegal-type.ll
M llvm/test/CodeGen/X86/masked-udiv.ll
M llvm/test/CodeGen/X86/masked-urem.ll
M llvm/test/CodeGen/X86/pr179489.ll
M llvm/test/CodeGen/X86/pr46532.ll
M llvm/test/CodeGen/X86/sub-of-not.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-shift-lut.ll
A llvm/test/CodeGen/X86/vselect-widen-mask-tree.ll
M llvm/test/MC/Mips/mips-register-names-invalid.s
M llvm/test/MC/Mips/mips64-register-names-n32-n64.s
M llvm/test/MC/RISCV/corev/XCVbitmanip-invalid.s
M llvm/test/MC/RISCV/corev/XCVbitmanip.s
A llvm/test/TableGen/MatchRegisterAltNameWithIndex.td
A llvm/test/Transforms/GVNSink/pseudo-probe.ll
M llvm/test/Transforms/LoopInterchange/memory-instr-ratio.ll
A llvm/test/Transforms/LoopUnroll/AMDGPU/partial-unroll-threshold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/cmp_cost.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-basic.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-load-types.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-safety.ll
A llvm/test/Transforms/LoopVectorize/AArch64/early-exit-with-speculative-load-scalable.ll
M llvm/test/Transforms/LoopVectorize/AArch64/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/AArch64/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-non-native-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/RISCV/early_exit_with_stores.ll
A llvm/test/Transforms/LoopVectorize/VPlan/AArch64/early-exit-with-speculative-load-oracle.ll
M llvm/test/Transforms/LoopVectorize/VPlan/conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/early_exit_with_stores_vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/interleave-conditional-scalar-assignment-vplan.ll
M llvm/test/Transforms/LoopVectorize/VPlan/uncountable-early-exit-vplan.ll
M llvm/test/Transforms/LoopVectorize/X86/cost-any-of.ll
M llvm/test/Transforms/LoopVectorize/early_exit_with_stores.ll
M llvm/test/Transforms/LoopVectorize/epilog-vectorization-fmaxnum-reductions.ll
M llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/interleave_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-non-const-iv-start.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp-trunc.ll
M llvm/test/Transforms/LoopVectorize/iv-select-cmp.ll
M llvm/test/Transforms/LoopVectorize/minmax_reduction.ll
M llvm/test/Transforms/LoopVectorize/scalarized_conditional_ops_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/select-cmp.ll
A llvm/test/Transforms/LoopVectorize/single-early-exit-anyof-fold.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-hint.ll
M llvm/test/Transforms/LoopVectorize/single-early-exit-interleave.ll
M llvm/test/Transforms/LoopVectorize/tail_fold_uncountable_exits.ll
M llvm/test/Transforms/LoopVectorize/unsupported_early_exit.ll
M llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/externally-used-copyables.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/non-power-of-2-with-adjusted-gathers.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/revec-non-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/elementwise-fma-operand1.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction-i1-mask.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/non-commutative-second-arg-only-copyable.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reduced-copyable-element.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/cmp-ptr-minmax.ll
M llvm/test/Transforms/SLPVectorizer/SystemZ/non-power-2-subvector-extract.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/entries-different-vf.ll
M llvm/test/Transforms/SLPVectorizer/X86/fabs-cost-softfp.ll
M llvm/test/Transforms/SLPVectorizer/X86/phi-multi-same-nodes.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll
M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
M llvm/test/Transforms/SLPVectorizer/X86/reorder-vf-to-resize.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit-macho.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-emit.ll
M llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage-opt.ll
M llvm/test/tools/llvm-dwarfdump/X86/Inputs/coverage.ll
M llvm/test/tools/llvm-dwarfdump/X86/coverage.test
M llvm/tools/llvm-dwarfdump/Coverage.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.h
M llvm/unittests/ADT/APFloatTest.cpp
M llvm/unittests/CodeGen/MFCommon.inc
M llvm/unittests/Support/CommandLineTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M mlir/include/mlir/Analysis/DataFlow/LivenessAnalysis.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPClauses.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/IR/Remarks.h
M mlir/include/mlir/Pass/PassOptions.h
M mlir/include/mlir/Transforms/Passes.td
M mlir/lib/Analysis/DataFlow/LivenessAnalysis.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/ExecutionEngine/ArmSMEStubs.cpp
M mlir/lib/ExecutionEngine/CMakeLists.txt
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
M mlir/lib/Target/LLVMIR/LoopAnnotationTranslation.cpp
M mlir/lib/Transforms/RemoveDeadValues.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/SparseTensor/external_direct.mlir
M mlir/test/Target/LLVMIR/Import/import-failure.ll
M mlir/test/Target/LLVMIR/Import/metadata-loop.ll
M mlir/test/Target/LLVMIR/loop-metadata.mlir
A mlir/test/Target/LLVMIR/openmp-dispatch.mlir
M mlir/test/Target/LLVMIR/openmp-todo.mlir
A mlir/test/Transforms/isolated-region-branch-canonicalize.mlir
A mlir/test/Transforms/remove-dead-values-function-root.mlir
A mlir/test/Transforms/remove-dead-values-nested-root.mlir
M mlir/test/lib/Dialect/Test/TestOpDefs.cpp
M mlir/test/lib/Dialect/Test/TestOps.td
M orc-rt/CMakeLists.txt
M orc-rt/include/orc-rt-c/support/Compiler.h
M orc-rt/include/orc-rt-internal/tools/OptionParser.h
M orc-rt/include/orc-rt/support/BitmaskEnum.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/ExecutorAddress.h
M orc-rt/include/orc-rt/support/bit.h
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/lib/bedrock/sps/AllSPSCI.cpp
A orc-rt/lib/bedrock/sys/windows/DynamicLibrary.cpp
A orc-rt/lib/bedrock/sys/windows/Memory.cpp
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
M orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
M orc-rt/test/unit/bedrock/ExecutorProcessInfoTest.cpp
M orc-rt/test/unit/bedrock/InProcessControllerAccessTest.cpp
M orc-rt/test/unit/bedrock/NativeDylibManagerTest.cpp
M orc-rt/test/unit/bedrock/SimpleNativeMemoryMapTest.cpp
M orc-rt/test/unit/bedrock/sps/NativeDylibManagerSPSCITest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleNativeMemoryMapSPSCITest.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
M orc-rt/test/unit/bedrock/sys/TargetTripleTest.cpp
M orc-rt/test/unit/support/CallableTraitsHelperTest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/bit-test.cpp
M orc-rt/test/unit/tools/OptionParserTest.cpp
Log Message:
-----------
Rebase
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/951d0905e710...63045fbfc45c
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