[all-commits] [llvm/llvm-project] 619787: [SPIR-V] Add storage class bits to fence and gener...

[Arseniy Obolenskiy via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 61978757eca575e2743471ddf7bcfb7e3a3979e4
      https://github.com/llvm/llvm-project/commit/61978757eca575e2743471ddf7bcfb7e3a3979e4
  Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
  Date:   2026-09-21 (Mon, 21 Sep 2026)

  Changed paths:
    M llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
    M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
    M llvm/test/CodeGen/SPIRV/AtomicBuiltinsFloat.ll
    M llvm/test/CodeGen/SPIRV/atomicrmw-storage-class-semantics.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-0.ll
    M llvm/test/CodeGen/SPIRV/extensions/SPV_EXT_long_vector/unmerge-crash-1.ll
    A llvm/test/CodeGen/SPIRV/fence-shader.ll
    M llvm/test/CodeGen/SPIRV/fence.ll
    M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchangeExplicit_cl20.ll
    M llvm/test/CodeGen/SPIRV/transcoding/AtomicCompareExchange_cl20.ll

  Log Message:
  -----------
  [SPIR-V] Add storage class bits to fence and generic atomic semantics (#223023)

A barrier only orders the memory it names, and we named none, so fences
ordered nothing

Name every class the target can reach, generic pointers had the same gap
in atomics



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