[all-commits] [llvm/llvm-project] 335793: [SCEV] Increase RewriteMap default size (NFC). (#2...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Sun Sep 20 14:27:37 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slppass-operand-info-and-context-to-tti-cost-queries
Home: https://github.com/llvm/llvm-project
Commit: 335793850c499195d9af75715bbbe84ce272666b
https://github.com/llvm/llvm-project/commit/335793850c499195d9af75715bbbe84ce272666b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
Log Message:
-----------
[SCEV] Increase RewriteMap default size (NFC). (#224864)
The old automatic default of 4 inline buckets meant that in practice we
were frequently hitting the grow path to 64 buckets, causing unnecessary
memory traffic.
SCEVRewriteVisitor is used each time loop guards are applied and the new
default improves compile-time slightly for SCEV-heavy workloads. Geomean
improves by -0.03%, but mafft and lencod see bigger wins:
https://llvm-compile-time-tracker.com/compare.php?from=7c55ad084c8b1503cafa42c60d88bff65919c9fa&to=c1f14fba38c4cd7b282709d8bd9481d28642b2c6&stat=instructions:u
It mostly makes applying loop guards cheaper, making it easier to use in
more places in the future.
PR: https://github.com/llvm/llvm-project/pull/224864
Commit: 99da24b8fd7141c0eb02292e183bc5e97eb55a87
https://github.com/llvm/llvm-project/commit/99da24b8fd7141c0eb02292e183bc5e97eb55a87
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getPSHUFShuffleMask - use PSHUFD/LW/HW decodes directly. NFC. (#224900)
Don't bother going through getTargetShuffleMask and checking for a
repeated lane mask when all we care about is the mask[4] permute mask -
PSHUFLW/HW don't even need the full 128-bit lane mask!
Commit: f28f0baf480125fd1a0b70c39c316778e3794b13
https://github.com/llvm/llvm-project/commit/f28f0baf480125fd1a0b70c39c316778e3794b13
Author: Feng Zou <feng.zou at intel.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/apx/optimize-compare-multipred.mir
Log Message:
-----------
[X86][APX] Fix EFLAGS reuse across cycles (#223613)
optimizeCompareInstr's multi-predecessor NF reuse (added in
ab39c491430e) did not scan the below-CmpInstr region of CmpMBB when
CmpMBB was on a CFG cycle: that region is on the back-edge path but is
scanned by neither the caller nor the helper's predecessor walk. A
non-NF-convertible EFLAGS clobber there (e.g. an unrelated CMP feeding a
JCC, as in the reproducer below with VUCOMISS/CTEST/COPY-\$eflags) still
let the helper delete the redundant compare and mark \$eflags live-in on
CmpMBB. That broke the reused EFLAGS on iteration 2+ and tripped
X86FlagsCopyLowering's SuccMBB == TestMBB self-loop check with a fatal
report_fatal_error when a preexisting COPY \$eflags save/restore sat in
the cycle.
Reproducer: https://godbolt.org/z/s58j5zxqd
Detect CmpMBB on a cycle via a forward-reachability BFS on its
successors and, when so, scan from just after CmpInstr to the block's
end: bail on any non-NF-convertible EFLAGS clobber, stage NF-convertible
ones. The rest of the helper is unchanged.
Tests exercise the bail paths (selfloop_shadow_below,
twoblock_cycle_shadow_below, threeblock_cycle_shadow_below,
selfloop_nfconvertible_below_cap), the positive stage-and-succeed path
(selfloop_nfconvertible_below), and the CmpMBB-not-on-cycle skip path
(multipred_above_cmpmbb).
Fixes: https://github.com/llvm/llvm-project/issues/223282
Assisted by Claude Code.
Commit: 35a11e0d32bd6f8f4eb343a5aeeee1ef401828b8
https://github.com/llvm/llvm-project/commit/35a11e0d32bd6f8f4eb343a5aeeee1ef401828b8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M orc-rt/lib/bedrock/sys/posix/DynamicLibrary.cpp
M orc-rt/lib/bedrock/sys/posix/Memory.cpp
M orc-rt/lib/bedrock/sys/posix/PageSize.cpp
M orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
Log Message:
-----------
[orc-rt] Drop emacs mode lines from .cpp files. (#224928)
These aren't needed for .cpp files where emacs can infer the mode from
the file extension.
Commit: 1e469c741cf0f4c80fdff8749336366a8a5699a4
https://github.com/llvm/llvm-project/commit/1e469c741cf0f4c80fdff8749336366a8a5699a4
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd.s
Log Message:
-----------
[RISCV] Fix immediate operand ranges for XCVsimd instructions (#224876)
See link:
-
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html#simd-bit-manipulation-operations
-
https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html#simd-shuffle-and-pack-operations
Commit: 04865d44edd515cd20ae7037f176e23d2b155544
https://github.com/llvm/llvm-project/commit/04865d44edd515cd20ae7037f176e23d2b155544
Author: knickish <knickish at gmail.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/test/CodeGen/M68k/inline-asm.ll
M llvm/test/MC/M68k/Data/Classes/MxMoveCCR.s
M llvm/test/MC/M68k/Data/Classes/MxMoveSR.s
Log Message:
-----------
[M68k] Add Imm source for MOVE to CCR/SR (#207590)
closes #165077, just adds the imm addressing mode to MOVE to SR/CCR
Commit: fbc222615d759435d4848e54987053fe5b614ce3
https://github.com/llvm/llvm-project/commit/fbc222615d759435d4848e54987053fe5b614ce3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
Log Message:
-----------
CodeGen: Pass instruction and operand index to isPCRelRegisterOperandLegal (#219420)
Replace the MachineOperand argument to the
TargetInstrInfo::isPCRelRegisterOperandLegal hook with the containing
instruction and operand index. The M68k implementation only used the
operand
to recover its parent instruction and operand number, so this drops the
dependence on MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 0de53b0cf6500ad29ba50f64daccf0d6b91fc1fb
https://github.com/llvm/llvm-project/commit/0de53b0cf6500ad29ba50f64daccf0d6b91fc1fb
Author: hev <wangrui at loongson.cn>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchMemoryBarrierOpt.cpp
M llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
Log Message:
-----------
[LoongArch] Drop asm part from memory barrier optimization pass (#223656)
Drop the inline asm part from #218597, which violates inline assembly
semantics.
Commit: 0b44c51c08dcc096f1f1a48532c3da31ceccb036
https://github.com/llvm/llvm-project/commit/0b44c51c08dcc096f1f1a48532c3da31ceccb036
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
A llvm/test/CodeGen/AArch64/sve-vector-interleave-legalize.ll
Log Message:
-----------
[SDAG] Handle widened operands for scalable PromoteIntRes_CONCAT_VECTORS (#224274)
Commit: 5640ecf3d362b9f3bf5d2d9f98631f2c1f0da5c8
https://github.com/llvm/llvm-project/commit/5640ecf3d362b9f3bf5d2d9f98631f2c1f0da5c8
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
Log Message:
-----------
[AMDGPU] Remove dead function and method declarations (NFC) (#224889)
createLowerWWMCopiesPass:
Added on July 28, 2023 in commit
4d42e8b5d1fa87e49768d100dd1bc53515391e89 without a definition or any
callers.
createAMDGPUReserveWWMRegsPass:
Added on September 30, 2024 in commit
ac0f64f06d67a93817ccd9a3c529ad40920115c9 without a definition or any
callers.
createAMDGPUStructurizeCFGPass:
The definition and callers were removed on June 19, 2013 in commit
d46fce11412636ec9cca038e1f2b1addf1690f00.
AMDGPUTargetLowering::LowerSTORE:
The definition was split into R600TargetLowering::LowerSTORE and
SITargetLowering::LowerSTORE on February 11, 2016 in commit
952456631458e638fdcc2509611c356bf0aa2bed.
AMDGPULibFuncBase::Param::mangleItanium,
AMDGPUMangledLibFunc::mangleName:
Added on August 11, 2017 in commit
7f37794ebd2c6c36224597800e4d1e5a99ad80e9 without definitions or any
callers.
AMDGPUTargetMachine::getSubtargetImpl():
The 0-argument overload definition and callers were removed on June
27, 2016 in commit 59c0ffa22ad2d0b3948c545b4eb442173a71633a.
GCNRPTracker::bumpDeadDefs:
Added on October 9, 2024 in commit
17bc959961aa5792821516b547100316fc886ab4 without a definition or any
callers.
PreRARematStage::ScoredRemat::rematerialize (3-argument overload):
The definition and callers were removed on April 11, 2026 in commit
42127fa2775ca9102d4be00cafbe0fcd6f25299d.
GCNSubtarget::getMaxLocalMemSizeWithWaveCount:
Moved to base class AMDGPUCommonSubtarget (now AMDGPUSubtarget) on
June 28, 2018 in commit c5a154db48c3cd9e16b5c74977d506415414daf7.
AMDGPUInstPrinter::printRegOperand (2-argument overload):
The definition and callers were removed on April 8, 2015 in commit
d7e6f13671e4f36c038b1a671697196b7b72db27.
AMDGPUInstPrinter::printLiteral, printLast, printNeg, printOMOD,
printRel, printUpdateExecMask, printUpdatePred, printWrite,
printBankSwizzle, printRSel, printCT, printKCache:
The definitions and callers were removed on June 28, 2018 in commit
c5a154db48c3cd9e16b5c74977d506415414daf7 after moving to
R600InstPrinter in commit a096b126285422933800f776b6eb830d40fed335.
R600TargetLowering::getSubtarget:
The definition and callers were removed on June 28, 2018 in commit
c5a154db48c3cd9e16b5c74977d506415414daf7.
R600InstrInfo::isFlagSet:
Added on December 11, 2012 in commit
75aadc2813824e18449e08a99690a6f886fadf13 without a definition or any
callers.
SIFixSGPRCopies::prepareRegSequenceAndPHIs:
Added on September 7, 2022 in commit
2e8817b90a9aa38c681ca1bb9075f9e8eed3f6e8 without a definition or any
callers.
SIScheduleBlockScheduler::schedule:
Added on January 13, 2016 in commit
02c3291566ff670d3fe1a7a20ba866cbe4c48266 without a definition or any
callers.
Assisted-by: Antigravity
Commit: 52500486a0b723a1d9528e3098901702da837c3d
https://github.com/llvm/llvm-project/commit/52500486a0b723a1d9528e3098901702da837c3d
Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/test/CodeGen/Mips/cconv/arguments-float.ll
M llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
M llvm/test/CodeGen/Mips/cconv/arguments.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
A llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll
A llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
M llvm/test/CodeGen/Mips/cconv/reserved-space.ll
M llvm/test/CodeGen/Mips/cconv/return-float.ll
M llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
M llvm/test/CodeGen/Mips/cconv/return-struct.ll
M llvm/test/CodeGen/Mips/cconv/return.ll
M llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
Log Message:
-----------
[Mips] Fix O32 lowering on 64-bit CPUs (#224937)
Use 32-bit GPR lowering for O32 while preserving the selected ISA and
FPR mode. Handle FP64 transfers through the stack when high-half moves
are unavailable.
Commit: fa360c3b8dbfd8a449364b7a6e454878bcf00eb9
https://github.com/llvm/llvm-project/commit/fa360c3b8dbfd8a449364b7a6e454878bcf00eb9
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
A llvm/test/Transforms/ConstraintElimination/mul-with-overflow.ll
A llvm/test/Transforms/ConstraintElimination/uadd-with-overflow.ll
M llvm/test/Transforms/ConstraintElimination/usub-with-overflow.ll
Log Message:
-----------
[ConstraintElim] Simplify all overflow intrinsics using isKnownNoWrap. (#224848)
Use isKnownNoWrap overload added in
https://github.com/llvm/llvm-project/pull/224758 to simplify all
supported overflowing math intrinsics.
Enables additional simplifications in a few more cases in
https://github.com/dtcxzyw/llvm-opt-benchmark-nightly/pull/1368.
And more simplifications in Swift, which uses overflow intrinsics
extensively.
Compile-time impact in the noise:
https://llvm-compile-time-tracker.com/compare.php?from=7a02bcc9189b467efbb071ab25d99273fefc54da&to=9a224fd59f971aa94b0e3509dcceae3bffb7ec81&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/224848
Commit: 66155d8a7409128e8c427cf5642847e01e40cb37
https://github.com/llvm/llvm-project/commit/66155d8a7409128e8c427cf5642847e01e40cb37
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
[SelectionDAG] Document that ISD::ADDE/SUBE/ADDC/SUBC use glue. NFC (#224765)
Commit: 51d290508d4dd980c3ba03bcc873926c41c6e591
https://github.com/llvm/llvm-project/commit/51d290508d4dd980c3ba03bcc873926c41c6e591
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAGCombiner] Restrict combineOrOfSetCCToUSUBOCarry to ZeroOrOneBooleanContent. (#224759)
We need to ensure the carry in matches boolean contents. We are checking
MaskedValueIsZero which is only valid for ZeroOrOneBooleanContent.
We could check ComputeNumSignBits for ZeroOrNegativeOneBooleanContent,
but no in tree target supports USUBO_CARRY and
ZeroOrNegativeOneBooleanContent.
This was an oversight in #223396 due to incorrect documentation for
USUBO_CARRY. I will fix that in a separate patch.
Commit: ffe46933084f1340211b1e4078d2920996b8e038
https://github.com/llvm/llvm-project/commit/ffe46933084f1340211b1e4078d2920996b8e038
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/ISDOpcodes.h
Log Message:
-----------
[SelectionDAG] Document that UADDO/USUBO_CARRRY follow getBooleanContents. NFC (#224764)
Use 'true' instead of '1'.
Follow up from post commit discussion in #223396.
Commit: c2e0c82edaa4f9a5b5615b67d3ed1768556222ff
https://github.com/llvm/llvm-project/commit/c2e0c82edaa4f9a5b5615b67d3ed1768556222ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
Log Message:
-----------
[RISCV] Add UImmLsbZeroAsmOperand class to use isUImmShifted<N, S> as the PredicateMethod. NFC (#224789)
Allows us to remove some wrappers from RISCVAsmParser.
Commit: 27eb38144a2bc40e989cdefb8265b6eb7aedb21b
https://github.com/llvm/llvm-project/commit/27eb38144a2bc40e989cdefb8265b6eb7aedb21b
Author: serge-sans-paille <sguelton at mozilla.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-t.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.cpp
Log Message:
-----------
[clang-tidy] Add detection of decltype(nullptr) => std::nullptr_t to modernize-use-nullptr (#224591)
Hidden behind an option switch, but on by default.
Commit: d0dc3b038f526cf85fb707cc821f4db33d3cfbcb
https://github.com/llvm/llvm-project/commit/d0dc3b038f526cf85fb707cc821f4db33d3cfbcb
Author: William Tran-Viet <wtranviet at proton.me>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
A libcxx/include/__iterator/static_packed_bounded_iter.h
M libcxx/include/module.modulemap.in
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/arithmetic.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/assert.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/comparison.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/ctor.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/dereference.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/layout.compile.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/types.compile.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/valid.verify.cpp
Log Message:
-----------
[libc++] Add a compact, bounded iterator (#208271)
- By taking advantage of unused alignment bits for a pointer of type `T`
and the static capacity known at compile time, we can make a compact
bounded iterator who's size == `sizeof(T*)` by stuffing a counter inside
those bits.
- This new iterator type is `static_packed_bounded_iterator<class _Ptr, size_t _RangeCapacity>` and is only valid if:
- `_Ptr` is a pointer
- `_RangeCapacity` is <= `(1 << (bit_width(alignof(T)) - 1)) - 1`. The
extra -1 is required, because we need to represent the end position past
the last element.
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 32080ffd98b12a7f4733181790b21ff62f9f31ba
https://github.com/llvm/llvm-project/commit/32080ffd98b12a7f4733181790b21ff62f9f31ba
Author: techmetx11 <114311037+techmetx11 at users.noreply.github.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrControl.td
A llvm/test/MC/M68k/Control/Classes/MxDBcc.s
Log Message:
-----------
[M68k][MC] Add support for DBcc instructions (#193930)
Commit: 1d655b0b72ce2a328e9cb307dfce3048c5700d7a
https://github.com/llvm/llvm-project/commit/1d655b0b72ce2a328e9cb307dfce3048c5700d7a
Author: knickish <knickish at gmail.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/lib/Target/M68k/M68kInstrControl.td
R llvm/test/MC/M68k/Control/Classes/MxDBcc.s
Log Message:
-----------
[M68k][MC] Revert "Add support for DBcc instructions" (#224950)"
llvm/llvm-project#193930 [broke m68k
builds](https://github.com/llvm/llvm-project/pull/193930#issuecomment-5751632991),
reverting
Commit: 4ffcaf61b123ba27c71daf8da7f8eb03ffdd748b
https://github.com/llvm/llvm-project/commit/4ffcaf61b123ba27c71daf8da7f8eb03ffdd748b
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M lldb/source/API/SBProgress.cpp
M lldb/source/Core/Progress.cpp
M lldb/unittests/API/CMakeLists.txt
A lldb/unittests/API/SBProgressTest.cpp
Log Message:
-----------
[lldb][SBAPI] Fix crash when calling SBProgress constructor. (#224176)
Fix crash when calling SBProgress constructor with nullptr.
Commit: 8692dda92022dc121e720b8f096e9dfdd6c00282
https://github.com/llvm/llvm-project/commit/8692dda92022dc121e720b8f096e9dfdd6c00282
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M llvm/docs/CommandLine.md
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/Support/CommandLine.cpp
Log Message:
-----------
[Support] Remove cl::multi_val (#224959)
Nothing uses it: the last user, llvm-nm, moved to OptTable. The feature
would block migration to TableGen based representation.
LLM-aided
Commit: be9e98270a4948e43b6555c7a5908bc9644209f1
https://github.com/llvm/llvm-project/commit/be9e98270a4948e43b6555c7a5908bc9644209f1
Author: Jeff Bailey <jbailey at raspberryginger.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M libc/include/sys/mman.yaml
M libc/src/sys/mman/linux/mlock2.cpp
M libc/src/sys/mman/mlock2.h
Log Message:
-----------
[libc] Fix mlock, mlock2, and munlock signatures (#224905)
Updated libc/include/sys/mman.yaml so the first parameter of mlock,
mlock2, and munlock is const void * rather than void *.
Updated libc/src/sys/mman/mlock2.h and
libc/src/sys/mman/linux/mlock2.cpp so the flags parameter is unsigned
int rather than int.
Assisted-by: Automated tooling, human reviewed.
Commit: 56502327677eff9747cfb8da78e9c132ad6a57b5
https://github.com/llvm/llvm-project/commit/56502327677eff9747cfb8da78e9c132ad6a57b5
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-20 (Sun, 20 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp
M clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst
A clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-t.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.cpp
M libc/include/sys/mman.yaml
M libc/src/sys/mman/linux/mlock2.cpp
M libc/src/sys/mman/mlock2.h
M libcxx/include/CMakeLists.txt
A libcxx/include/__iterator/static_packed_bounded_iter.h
M libcxx/include/module.modulemap.in
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/arithmetic.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/assert.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/comparison.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/ctor.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/dereference.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/layout.compile.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/types.compile.pass.cpp
A libcxx/test/libcxx/iterators/static_packed_bounded_iter/valid.verify.cpp
M lldb/source/API/SBProgress.cpp
M lldb/source/Core/Progress.cpp
M lldb/unittests/API/CMakeLists.txt
A lldb/unittests/API/SBProgressTest.cpp
M llvm/docs/CommandLine.md
M llvm/include/llvm/Analysis/ScalarEvolutionExpressions.h
M llvm/include/llvm/CodeGen/ISDOpcodes.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/Support/CommandLine.h
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/GCNRegPressure.h
M llvm/lib/Target/AMDGPU/GCNSchedStrategy.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/R600ISelLowering.h
M llvm/lib/Target/AMDGPU/R600InstrInfo.h
M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
M llvm/lib/Target/AMDGPU/SIMachineScheduler.h
M llvm/lib/Target/LoongArch/LoongArchMemoryBarrierOpt.cpp
M llvm/lib/Target/M68k/M68kInstrData.td
M llvm/lib/Target/M68k/M68kInstrInfo.cpp
M llvm/lib/Target/M68k/M68kInstrInfo.h
M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSubtarget.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/CodeGen/AArch64/sve-vector-interleave-legalize.ll
M llvm/test/CodeGen/LoongArch/memory-barrier-opt.ll
M llvm/test/CodeGen/M68k/inline-asm.ll
M llvm/test/CodeGen/Mips/cconv/arguments-float.ll
M llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
M llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
M llvm/test/CodeGen/Mips/cconv/arguments.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
M llvm/test/CodeGen/Mips/cconv/callee-saved.ll
M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
A llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll
A llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
M llvm/test/CodeGen/Mips/cconv/reserved-space.ll
M llvm/test/CodeGen/Mips/cconv/return-float.ll
M llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
M llvm/test/CodeGen/Mips/cconv/return-struct.ll
M llvm/test/CodeGen/Mips/cconv/return.ll
M llvm/test/CodeGen/Mips/cconv/stack-alignment.ll
M llvm/test/CodeGen/X86/apx/optimize-compare-multipred.mir
M llvm/test/MC/M68k/Data/Classes/MxMoveCCR.s
M llvm/test/MC/M68k/Data/Classes/MxMoveSR.s
M llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
M llvm/test/MC/RISCV/corev/XCVsimd.s
A llvm/test/Transforms/ConstraintElimination/mul-with-overflow.ll
A llvm/test/Transforms/ConstraintElimination/uadd-with-overflow.ll
M llvm/test/Transforms/ConstraintElimination/usub-with-overflow.ll
M orc-rt/lib/bedrock/sys/posix/DynamicLibrary.cpp
M orc-rt/lib/bedrock/sys/posix/Memory.cpp
M orc-rt/lib/bedrock/sys/posix/PageSize.cpp
M orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
Log Message:
-----------
Address comments
Created using spr 1.3.7
Compare: https://github.com/llvm/llvm-project/compare/e11e18def061...56502327677e
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