[all-commits] [llvm/llvm-project] 525004: [Mips] Fix O32 lowering on 64-bit CPUs (#224937)

[Jiaxun Yang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 52500486a0b723a1d9528e3098901702da837c3d
      https://github.com/llvm/llvm-project/commit/52500486a0b723a1d9528e3098901702da837c3d
  Author: Jiaxun Yang <jiaxun.yang at flygoat.com>
  Date:   2026-09-20 (Sun, 20 Sep 2026)

  Changed paths:
    M llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
    M llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
    M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsSubtarget.cpp
    M llvm/test/CodeGen/Mips/cconv/arguments-float.ll
    M llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
    M llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
    M llvm/test/CodeGen/Mips/cconv/arguments.ll
    M llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
    M llvm/test/CodeGen/Mips/cconv/callee-saved.ll
    M llvm/test/CodeGen/Mips/cconv/memory-layout.ll
    A llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll
    A llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
    M llvm/test/CodeGen/Mips/cconv/reserved-space.ll
    M llvm/test/CodeGen/Mips/cconv/return-float.ll
    M llvm/test/CodeGen/Mips/cconv/return-hard-float.ll
    M llvm/test/CodeGen/Mips/cconv/return-struct.ll
    M llvm/test/CodeGen/Mips/cconv/return.ll
    M llvm/test/CodeGen/Mips/cconv/stack-alignment.ll

  Log Message:
  -----------
  [Mips] Fix O32 lowering on 64-bit CPUs (#224937)

Use 32-bit GPR lowering for O32 while preserving the selected ISA and
FPR mode. Handle FP64 transfers through the stack when high-half moves
are unavailable.



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