[all-commits] [llvm/llvm-project] 0f439a: [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/users/mshockwave/riscv/vslideup-down-elimination
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f439ac5cb85fdc0fe6df193cb579491e1133ed5
      https://github.com/llvm/llvm-project/commit/0f439ac5cb85fdc0fe6df193cb579491e1133ed5
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP_VL pairs


  Commit: 59c554f1f6674566cde6900bcb13360ab3688961
      https://github.com/llvm/llvm-project/commit/59c554f1f6674566cde6900bcb13360ab3688961
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  fixup! Update more tests


  Commit: 226f3222edfd38a62272c1b5bc2a17c6d783a026
      https://github.com/llvm/llvm-project/commit/226f3222edfd38a62272c1b5bc2a17c6d783a026
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  fixup! Rebase


  Commit: e00387720f8264398ffae5313e70afa884877e95
      https://github.com/llvm/llvm-project/commit/e00387720f8264398ffae5313e70afa884877e95
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  fixup! Address review comments


  Commit: a7e104cda2bdcd77d1a578d20cb5ec64bdc93aea
      https://github.com/llvm/llvm-project/commit/a7e104cda2bdcd77d1a578d20cb5ec64bdc93aea
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  fixup! Loosen the mask condition


  Commit: 86ad67fbe7ec25fe116ccbcbf22fc0262d150348
      https://github.com/llvm/llvm-project/commit/86ad67fbe7ec25fe116ccbcbf22fc0262d150348
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  fixup! Add extra condition on VL


  Commit: 20088aecb7cedc9622e89d75c66df85991d2f7d6
      https://github.com/llvm/llvm-project/commit/20088aecb7cedc9622e89d75c66df85991d2f7d6
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  fixup! Rebase


Compare: https://github.com/llvm/llvm-project/compare/a5503d0795b9...20088aecb7ce

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