[all-commits] [llvm/llvm-project] f29371: [AMDGPU] Use integer LLTs for work-item IDs (#224519)

[Keshav Vinayak Jha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f29371ad92f1b47279a3b46f7d336f3e48fa4538
      https://github.com/llvm/llvm-project/commit/f29371ad92f1b47279a3b46f7d336f3e48fa4538
  Author: Keshav Vinayak Jha <31160700+keshavvinayak01 at users.noreply.github.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui-regbanklegalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zext.mir
    M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/fma-mix.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
    M llvm/test/CodeGen/AMDGPU/permlane16_opsel.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll

  Log Message:
  -----------
  [AMDGPU] Use integer LLTs for work-item IDs (#224519)

Type work-item ID preloaded values and special entry-function live-ins
as i32, matching the intrinsic result and the existing GlobalISel and
SelectionDAG lowering. This prevents an s32 live-in type from reaching
the divergent G_AND and lets VgprToVccCopy preserve its source LLT
directly.

The original failure was a GlobalISel cannot-select abort on a 32-bit
VGPR G_AND produced from `llvm.amdgcn.workitem.id.x`. This follows up
#220987 by fixing the type at its producer instead of coercing it in
register-bank legalization.

A lot of tests need to be migrated because of this, owing to the
Extended LLTs change in https://github.com/llvm/llvm-project/pull/207419

Assisted-by: Codex

Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Co-authored-by: GPT-5 <noreply at openai.com>



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