[all-commits] [llvm/llvm-project] 91c00b: [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/users/mshockwave/riscv/vslideup-down-elimination
  Home:   https://github.com/llvm/llvm-project
  Commit: 91c00ba8d7c2440d2375262364937b6155cd058a
      https://github.com/llvm/llvm-project/commit/91c00ba8d7c2440d2375262364937b6155cd058a
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  [RISCV] Eliminate redundant VSLIDEDOWN_VL/VSLIDEUP_VL pairs


  Commit: 1ce218bf867ea8888d544f91cf9b6c30b9a57248
      https://github.com/llvm/llvm-project/commit/1ce218bf867ea8888d544f91cf9b6c30b9a57248
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

  Log Message:
  -----------
  fixup! Update more tests


  Commit: 61d0253d3e7f33c2c9a5fbf8b8f825911f7b0f13
      https://github.com/llvm/llvm-project/commit/61d0253d3e7f33c2c9a5fbf8b8f825911f7b0f13
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  fixup! Rebase


  Commit: 0000553bfcfab2412d83abfc78368d08d9e9c877
      https://github.com/llvm/llvm-project/commit/0000553bfcfab2412d83abfc78368d08d9e9c877
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  fixup! Address review comments


  Commit: 4ef9ec4deff5305acba8b5a98bfba69c7daf9229
      https://github.com/llvm/llvm-project/commit/4ef9ec4deff5305acba8b5a98bfba69c7daf9229
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

  Log Message:
  -----------
  fixup! Loosen the mask condition


  Commit: 35b33e54df40a5740ec2684a963f1b9d54e2b36d
      https://github.com/llvm/llvm-project/commit/35b33e54df40a5740ec2684a963f1b9d54e2b36d
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  fixup! Add extra condition on VL


  Commit: a5503d0795b97b3119af9cc70bd480fbe0a3ee23
      https://github.com/llvm/llvm-project/commit/a5503d0795b97b3119af9cc70bd480fbe0a3ee23
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2026-09-18 (Fri, 18 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

  Log Message:
  -----------
  fixup! Rebase


Compare: https://github.com/llvm/llvm-project/compare/910483ae2603...a5503d0795b9

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