[all-commits] [llvm/llvm-project] 5bc5d8: [CodeGen] Use SmallSetVectorImpl for getRegAllocat...

[Nick Desaulniers via All-commits]

  Branch: refs/heads/users/nickdesaulniers/regalloc_hints_codegen
  Home:   https://github.com/llvm/llvm-project
  Commit: 5bc5d83984e82cbecac5c88fe0b3708a21cd7133
      https://github.com/llvm/llvm-project/commit/5bc5d83984e82cbecac5c88fe0b3708a21cd7133
  Author: Nick Desaulniers <ndesaulniers at google.com>
  Date:   2026-09-17 (Thu, 17 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/CodeGen/AllocationOrder.cpp
    M llvm/lib/CodeGen/AllocationOrder.h
    M llvm/lib/CodeGen/TargetRegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    M llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/unittests/CodeGen/AllocationOrderTest.cpp
    M llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp

  Log Message:
  -----------
  [CodeGen] Use SmallSetVectorImpl for getRegAllocationHints

Change TargetRegisterInfo::getRegAllocationHints and all target overrides
to accept SmallSetVectorImpl<MCPhysReg> &Hints instead of SmallVectorImpl,
structurally preventing duplicate register allocation hints while preserving
insertion order and avoiding hardcoding the inline capacity in virtual
method signatures.

Increase AllocationOrder's inline hint storage capacity from 16 to 32
registers to accommodate 32-register classes without heap allocations.



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