[all-commits] [llvm/llvm-project] a47fe6: [RISCV] Account for VL toggle cost when splitting ...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a47fe60be7facad0f3db9090bb41f94872ee2fa0
      https://github.com/llvm/llvm-project/commit/a47fe60be7facad0f3db9090bb41f94872ee2fa0
  Author: Luke Lau <luke at igalia.com>
  Date:   2026-09-17 (Thu, 17 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/vp-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-access-wide-stride.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses-narrow-iv.ll

  Log Message:
  -----------
  [RISCV] Account for VL toggle cost when splitting VP memory intrinsics (#223992)

Not an alternative to #222836 since this doesn't handle all cases, but
something we should do anyway in the TTI to be accurate.

For vp.load/vp.gather/vp.strided.load and their store counterparts, when
they're split they introduce extra vl toggles which involve computation
on the evl, e.g.

      vsetvli a2, zero, e8, mf4, ta, ma
      vmv1r.v v8, v0
      csrr a2, vlenb
      srli a3, a2, 3
      vslidedown.vx v0, v0, a3
      sub a3, a1, a2
      sltu a4, a1, a3
      addi a4, a4, -1
      slli a5, a2, 3
      and a3, a4, a3
      add a5, a0, a5
      vsetvli zero, a3, e64, m8, ta, ma
      vle64.v v16, (a5), v0.t
      bltu a1, a2, .LBB44_2
    # %bb.1:
      mv a1, a2
    .LBB44_2:
      vmv1r.v v0, v8
      vsetvli zero, a1, e64, m8, ta, ma
      vle64.v v8, (a0), v0.t

Account for some overhead in the cost to influence the loop vectorizer
to avoid picking VFs that lead to types that need split.



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