[all-commits] [llvm/llvm-project] 76bb77: [RISCV] Merge zeroing stores into wider LMUL vecto...

[Pengcheng Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 76bb77e45a478f91bef1ea7369119974c6449c94
      https://github.com/llvm/llvm-project/commit/76bb77e45a478f91bef1ea7369119974c6449c94
  Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
  Date:   2026-09-16 (Wed, 16 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/memset-inline.ll
    M llvm/test/CodeGen/RISCV/rvv/pr83017.ll
    M llvm/test/CodeGen/RISCV/rvv/pr90559.ll

  Log Message:
  -----------
  [RISCV] Merge zeroing stores into wider LMUL vector stores (#223908)

memset lowers to LMUL1 vector stores (v2i64 for e64) that we rely on
store merging to widen. `storeOfVectorConstantIsCheap` counted the
number of MemVT-sized stores, so a v2i64 MemVT needed 4 stores before
merging kicked in, leaving two VL=2 m1 stores for a 32B zero region.

Use the total element count for zeroing stores so two v2i64 stores
merge into one VL=4 e64 m2 store.

Partially fixes #223906

Assisted-by: TRAE CLI (Opus 4.8)



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