[all-commits] [llvm/llvm-project] cf656b: [AMDGPU] Add DSLatencyMode flag + attr to control ...

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/users/jebyrnes/DSLatencyModeRebase0
  Home:   https://github.com/llvm/llvm-project
  Commit: cf656bdca0ab090ca91bec97ce460ed55e4ce821
      https://github.com/llvm/llvm-project/commit/cf656bdca0ab090ca91bec97ce460ed55e4ce821
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUBarrierLatency.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    M llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
    M llvm/test/CodeGen/AMDGPU/coexec-sched-flavor-classification.mir
    M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
    A llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
    A llvm/test/CodeGen/AMDGPU/ds-latency-mode-branch-cost.mir
    A llvm/test/CodeGen/AMDGPU/ds-latency-mode-default-scheduler.mir
    A llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir

  Log Message:
  -----------
  [AMDGPU] Add DSLatencyMode flag + attr to control LDS latency

Change-Id: Ia5fee7983adffdb837ba2e876a64d805263b60c3


  Commit: b8373c3f48e5e3e02610ba1685b03b8a9bc6a61a
      https://github.com/llvm/llvm-project/commit/b8373c3f48e5e3e02610ba1685b03b8a9bc6a61a
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h

  Log Message:
  -----------
  More documentation

Change-Id: I65ff1a1b605796d21a52766dcf04c64bc64aaa4e


  Commit: fa72130f486a196fbf124205ba3df39cd591ecea
      https://github.com/llvm/llvm-project/commit/fa72130f486a196fbf124205ba3df39cd591ecea
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-sched-agpr-excess.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
    M llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll
    M llvm/test/CodeGen/AMDGPU/ds-latency-mode-attr.mir
    M llvm/test/CodeGen/AMDGPU/ds-latency-mode-flag.mir

  Log Message:
  -----------
  Fix lit

Change-Id: Id8c3f63acdce212f1030e5dfc7d9273c56945958


Compare: https://github.com/llvm/llvm-project/compare/21cdedb2a902...fa72130f486a

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