[all-commits] [llvm/llvm-project] fe825a: [AMDGPU] Add MemoryPipeline scheduling to Coexec s...

[Austin Kerbow via All-commits]

  Branch: refs/heads/users/jebyrnes/FenceWaitRebase2
  Home:   https://github.com/llvm/llvm-project
  Commit: fe825a47b9e6b9d331c2c1bbd3b04bb38067d86a
      https://github.com/llvm/llvm-project/commit/fe825a47b9e6b9d331c2c1bbd3b04bb38067d86a
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  [AMDGPU] Add MemoryPipeline scheduling to Coexec sched

Change-Id: I52c476834155823d1ba998cdbbcb3ad6a7e6f2f5


  Commit: b79aaf5cb1bf7cdc6798ad2945f76931121e8978
      https://github.com/llvm/llvm-project/commit/b79aaf5cb1bf7cdc6798ad2945f76931121e8978
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Add a comment

Change-Id: I447f7f1fb185b18924cfd98249b5a0a05fef2484


  Commit: a92cbbd5310344b80aa4bdbba43dc4af55ab5d6c
      https://github.com/llvm/llvm-project/commit/a92cbbd5310344b80aa4bdbba43dc4af55ab5d6c
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h

  Log Message:
  -----------
  Make fence heuristic work bottom-up

Change-Id: I629cbc8905b87a962e8b123287e5f60a3154df6b


  Commit: 06ea0d696e716187cfb97b8e7bf311973f630116
      https://github.com/llvm/llvm-project/commit/06ea0d696e716187cfb97b8e7bf311973f630116
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add back tryLatency

Change-Id: I12d4f255c48ed77ba927eb3b192e5903f1f5e24f


  Commit: a33e068a3c84f510f9f5db03033606d50962b4e7
      https://github.com/llvm/llvm-project/commit/a33e068a3c84f510f9f5db03033606d50962b4e7
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp

  Log Message:
  -----------
  Add comment

Change-Id: I2180bba631fe4a01ed3c3fbcfa8c19cbefa84133


  Commit: 8d2597d5e29ca8c210a006580321462683ce888c
      https://github.com/llvm/llvm-project/commit/8d2597d5e29ca8c210a006580321462683ce888c
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Adrress comments from https://github.com/llvm/llvm-project/pull/188658

Change-Id: Ia94c567a753168c1ffa16dc5d91195e7dd0ba044


  Commit: d5626964a6befba4b4613abf90ab33222a51af66
      https://github.com/llvm/llvm-project/commit/d5626964a6befba4b4613abf90ab33222a51af66
  Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Update tests

Change-Id: Ided5a4e6968d4670d1fd09bcb327a75a25273d4e


  Commit: 81c7e6e44c42cb4976d35167be2a4ea33914451e
      https://github.com/llvm/llvm-project/commit/81c7e6e44c42cb4976d35167be2a4ea33914451e
  Author: Austin Kerbow <Austin.Kerbow at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
    M llvm/test/CodeGen/AMDGPU/coexec-block-carried-latency.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-ds-fifo.mir
    M llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir

  Log Message:
  -----------
  Address comments.

Avoid prioritizing DMA and fence candidates while they still have an effective stall.

Make the top-down requirement explicit and remove unreachable bottom-up handling.


Compare: https://github.com/llvm/llvm-project/compare/9020a868c856...81c7e6e44c42

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