[all-commits] [llvm/llvm-project] 6a8b94: [Xtensa] Implement esp32s3 target. (#220393)

[Andrei Safronov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a8b946a43c5ded4a1055cdd36f23fef11812fa0
      https://github.com/llvm/llvm-project/commit/6a8b946a43c5ded4a1055cdd36f23fef11812fa0
  Author: Andrei Safronov <andrei.safronov at espressif.com>
  Date:   2026-09-16 (Wed, 16 Sep 2026)

  Changed paths:
    M llvm/include/llvm/TargetParser/XtensaTargetParser.def
    M llvm/include/llvm/TargetParser/XtensaTargetParser.h
    M llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp
    M llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp
    M llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
    M llvm/lib/Target/Xtensa/Xtensa.td
    M llvm/lib/Target/Xtensa/XtensaFeatures.td
    M llvm/lib/Target/Xtensa/XtensaInstrFormats.td
    M llvm/lib/Target/Xtensa/XtensaInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaOperands.td
    M llvm/lib/Target/Xtensa/XtensaProcessors.td
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
    M llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
    A llvm/lib/Target/Xtensa/XtensaS3DSPInstrInfo.td
    M llvm/lib/Target/Xtensa/XtensaSubtarget.h
    A llvm/test/MC/Xtensa/xtensa-esp32s3-invalid.s
    A llvm/test/MC/Xtensa/xtensa-esp32s3-valid.s

  Log Message:
  -----------
  [Xtensa] Implement esp32s3 target. (#220393)

- Add esp32s3 CPU support
- Implement esp32s3 DSP operations with test
- Improve asm register parsing



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