[all-commits] [llvm/llvm-project] 320bc6: [AMDGPU] Fix for GFX11 VOPD interlock hazard (#220...

[hidekisaito via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 320bc620c46b0fd49a9976e499cd4252d78297b8
      https://github.com/llvm/llvm-project/commit/320bc620c46b0fd49a9976e499cd4252d78297b8
  Author: hidekisaito <hidekido at amd.com>
  Date:   2026-09-15 (Tue, 15 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNSubtarget.h
    M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
    M llvm/test/CodeGen/AMDGPU/arbitrary-fp-to-float-fp8-hw.ll
    M llvm/test/CodeGen/AMDGPU/bf16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
    M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
    M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
    M llvm/test/CodeGen/AMDGPU/fdiv.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fmed3.ll
    M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
    M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
    M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
    M llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
    M llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
    M llvm/test/CodeGen/AMDGPU/fpow.ll
    M llvm/test/CodeGen/AMDGPU/freeze-binary.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
    M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.maximum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.minimum.f32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/llvm.powi.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
    M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
    M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
    M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
    M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
    M llvm/test/CodeGen/AMDGPU/select.f16.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
    M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
    M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
    M llvm/test/CodeGen/AMDGPU/vopd-combine.mir

  Log Message:
  -----------
  [AMDGPU] Fix for GFX11 VOPD interlock hazard (#220348)

On GFX11, a VOPD consumer whose X/Y sources share a gather class (srcA
or srcB) and the same VGPR parity can lose the destination-buffer interlock
for one of those sources. Thus, use parity as bank mask instead.



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