[all-commits] [llvm/llvm-project] 8e38a3: [RISCV] Improve the earlyclobber constraint for ve...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8e38a37adaf935561d6fe8d7e2323a4042cee556
      https://github.com/llvm/llvm-project/commit/8e38a37adaf935561d6fe8d7e2323a4042cee556
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-14 (Mon, 14 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/GlobalISel/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

  Log Message:
  -----------
  [RISCV] Improve the earlyclobber constraint for vector index load. (#223565)

When the data EEW is smaller than the index EEW, the destination may
overlap the index operand as long as the overlap is in the
lowest-numbered part of the index register group. If the index EMUL is
no larger than 1 then both operands are a single register, so any
overlap is necessarily the lowest-numbered part and no constraint is
needed.

Assisted-by: Claude



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