[all-commits] [llvm/llvm-project] 44d1d0: Add standard libc package features to libc subpack...
Ryunosuke (Rick) Yanashita via All-commits
all-commits at lists.llvm.org
Mon Sep 14 20:47:20 PDT 2026
Branch: refs/heads/users/arichardson/spr/main.riscv-select-the-capability-abi-by-default-when-the-y-extension-is-enabled
Home: https://github.com/llvm/llvm-project
Commit: 44d1d020a920341903e726506f3efefe27ea3145
https://github.com/llvm/llvm-project/commit/44d1d020a920341903e726506f3efefe27ea3145
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
Add standard libc package features to libc subpackages (#223079)
Commit: 04a04612e6696d36cd26edadddf20d1329794d2e
https://github.com/llvm/llvm-project/commit/04a04612e6696d36cd26edadddf20d1329794d2e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][Cpp] Stop using Operation::getAttrs (NFC) (#223080)
Only discardable attributes on multi-result func.return operations are
C++ tuple arguments; the operation has no inherent attributes relevant
to the translation.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: b5874129d921518823d257770c742da2a860b2cf
https://github.com/llvm/llvm-project/commit/b5874129d921518823d257770c742da2a860b2cf
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/test/Transforms/licm.fir
Log Message:
-----------
[flang] Do not hoist fir.field_index out of loops (#222891)
Lowering a consumer of a !fir.field value inspects its defining
operation: for a record whose layout is known at compile time the field
becomes an LLVM GEP struct index, which must be a constant, and
otherwise the `field` attribute is read off the defining op. A field
value therefore may not be a block argument.
LICM broke that. fir.field_index is Pure and takes no operands, so it is
trivially loop-invariant and was hoisted out of the loop. Lowering emits
one inside each arm of a construct -- for example the CASEs of a SELECT
CASE that each pass a different component of the same derived type as an
actual argument -- so hoisting them left those arms as
otherwise-identical blocks differing only in that operand. Block merging
then merged them and threaded the field through a new block argument,
and codegen aborted with "must be a constant".
Leave producers of a !fir.field where they are. The arms then differ by
an operation rather than by an operand, so they are no longer merge
candidates. Consumers are unaffected and still hoist: fir.coordinate_of
uses the attribute form of the field, so it does not depend on the
fir.field_index value.
The check keys on the result type rather than on FieldIndexOp so that
any operation producing a !fir.field is covered, and sits in the
predicate shared by the direct-loop and nested-region hoisting paths.
Commit: f795e9526254f4d1cee4855b40041d5797d2f676
https://github.com/llvm/llvm-project/commit/f795e9526254f4d1cee4855b40041d5797d2f676
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Shape/IR/Shape.cpp
Log Message:
-----------
[mlir][Shape] Stop using Operation::getAttrs in printers (NFC) (#223083)
Print only discardable attributes after inherent fields are handled by
the custom assembly formats.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: bb14dc958cbb7f9742f37cbae6d290a0997e7299
https://github.com/llvm/llvm-project/commit/bb14dc958cbb7f9742f37cbae6d290a0997e7299
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/examples/toy/Ch2/mlir/Dialect.cpp
M mlir/examples/toy/Ch3/mlir/Dialect.cpp
M mlir/examples/toy/Ch4/mlir/Dialect.cpp
M mlir/examples/toy/Ch5/mlir/Dialect.cpp
M mlir/examples/toy/Ch6/mlir/Dialect.cpp
M mlir/examples/toy/Ch7/mlir/Dialect.cpp
Log Message:
-----------
[mlir][Toy] Stop using Operation::getAttrs (NFC) (#223082)
Print only discardable attributes in Toy custom operation printers.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: c7a7f8364a1335b8938af2113fd8ec43cd3a2c47
https://github.com/llvm/llvm-project/commit/c7a7f8364a1335b8938af2113fd8ec43cd3a2c47
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
Log Message:
-----------
[mlir] Stop using Operation::getAttrs in dialect utilities (NFC) (#223081)
Copy operation properties and discardable attributes separately.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 4cec7e6e3082e8abbee08f90db3c353c4c379bdb
https://github.com/llvm/llvm-project/commit/4cec7e6e3082e8abbee08f90db3c353c4c379bdb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
Log Message:
-----------
[mlir][SMT] Stop using Operation::getAttrs (NFC) (#223086)
Print only discardable attributes after inherent fields are handled by
the custom operation printers.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 0cc524fdf4becec3763cd50930de5156d76ba1d4
https://github.com/llvm/llvm-project/commit/0cc524fdf4becec3763cd50930de5156d76ba1d4
Author: nvptm <pmathew at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-declare-globals.f90
M flang/test/Lower/module-parameter-linkonce-odr.f90
Log Message:
-----------
[flang][OpenACC] Do not emit declare ctor/dtor for module PARAMETER variables (#222993)
A module PARAMETER in !$acc declare is already emitted as an initialized
device global. A host ctor/dtor would still register that same symbol
with the runtime. Skip the registration pair and keep acc.declare so the
constant is
still emitted as an initialized global in the GPU module.
Commit: 5f09d40446ffbcd92d9e1a2a14bae974eb445cdb
https://github.com/llvm/llvm-project/commit/5f09d40446ffbcd92d9e1a2a14bae974eb445cdb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/PDLInterp/IR/PDLInterp.cpp
Log Message:
-----------
[mlir][PDLInterp] Stop using Operation::getAttrs (NFC) (#223088)
Print the discardable dictionary after the inherent fields handled by
the custom assembly format.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 641dc586869b21dc42785aa72949ed57c408204e
https://github.com/llvm/llvm-project/commit/641dc586869b21dc42785aa72949ed57c408204e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/docs/CodingConventions.md
M orc-rt/include/orc-rt-c/support/CoreTypes.h
M orc-rt/include/orc-rt-c/support/Error.h
A orc-rt/include/orc-rt-c/support/RTTI.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/RTTI.h
M orc-rt/lib/support/Error.cpp
M orc-rt/lib/support/RTTI.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/Inputs/RTTICrossDylibTestError.h
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
M orc-rt/test/unit/support/CAPICompileTest.c
M orc-rt/test/unit/support/ErrorCAPITest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
A orc-rt/test/unit/support/RTTICrossDylibTest.cpp
M orc-rt/test/unit/support/RTTITest.cpp
Log Message:
-----------
[orc-rt] Refactor RTTI for cross-library support, add C API (#222946)
Identify types by name rather than by the address of a per-type ID
object, so that a type's identity survives crossing a library boundary:
an object may be constructed by one library and have its type queried by
another, each with its own copy of orc-rt, where per-type addresses
would not agree. Participating classes now declare an RTTIName, which
must be unique across the process.
RTTIRoot records which library produced each value, so same-library
queries still resolve by pointer comparison, and only cross-library ones
fall back to strcmp.
Adds orc-rt-c/support/RTTI.h to expose this to C.
ORC_RT_RTTI_PARTICIPANT and ORC_RT_C_RTTI_IMPL declare and define a
per-type cast entry point, reached via ORC_RT_DYNCAST, alongside
orc_rt_RTTIRoot_getTypeName for logging. This replaces the
orc_rt_Error_TypeId API (orc_rt_Error_getTypeId,
orc_rt_StringError_getTypeId), which exposed ID addresses and so could
not work across libraries. orc_rt_ErrorRef moves from CoreTypes.h to
Error.h.
RTTICrossDylibTest checks identity across a real boundary: its helper
library links its own copy of orc-rt-bedrock, giving it a distinct
library ID.
Commit: 80bc02604c4ecec507c906552db3e03e5efdaee3
https://github.com/llvm/llvm-project/commit/80bc02604c4ecec507c906552db3e03e5efdaee3
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
Log Message:
-----------
[flang][OpenACC] Allocate bufferized recipe descriptors in device memory (#223028)
ACCRecipeBufferization places the descriptor of a bufferized recipe
clause next to the variable it holds. When the clause sits inside a
compute construct and the variable is already produced by a data entry
operation, that memory is host memory no data clause maps, so device
code reading the descriptor through it gets a host address.
Place the descriptor in the construct region in that case. The region is
device memory and needs no data clause of its own, and the mapped
variable is a legal live-in since a data entry operation produces it.
The region entry block is used rather than the clause operation so that
a clause on a nested loop does not allocate on every iteration.
Assisted-by: Cursor
Commit: a8e989fe377385906abdda1f965622fe83941fd4
https://github.com/llvm/llvm-project/commit/a8e989fe377385906abdda1f965622fe83941fd4
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
M flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[mlir][OpenACC] Preserve reduction mappings during materialization. (#222189)
Create or reuse structured reduction mappings before compute-construct
reduction recipes are consumed. Materialize initialization and
combination against the mapped value while leaving nested loop
reductions unchanged.
Assisted-by: Cursor
Commit: 4d10444e7d4c8fcb6533522f39cd0ffb88497253
https://github.com/llvm/llvm-project/commit/4d10444e7d4c8fcb6533522f39cd0ffb88497253
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
Log Message:
-----------
[mlir][OpenACC] Restrict implicit data to compute constructs (#222759)
acc.kernel_environment contains host-side preparation around an outlined
compute region; it is not itself an OpenACC compute construct. Treating
all of its live-ins as implicit device mappings can map
compiler-generated host operations and assign them kernels-style copy
semantics.
Limit ACCImplicitData to parallel, kernels, and serial. In particular,
do not process kernel_environment or the lowered compute_region form.
Assisted-by: Cursor
Commit: 329f45430835fe803b753ac78fc823b5dfc5df69
https://github.com/llvm/llvm-project/commit/329f45430835fe803b753ac78fc823b5dfc5df69
Author: Douglas <Douglas.Gliner at sony.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SafeStack.cpp
A llvm/test/Transforms/SafeStack/X86/pointer-address-domtree.ll
Log Message:
-----------
[CodeGen][SafeStack] Successful InlineFunction should force a recalculation of potentially stale DominatorTree (#222820)
In commit 51a25846c198, Safe Stack began preserving the `DominatorTree`
by the end of the pass' run. Updates to the `DominatorTree` were then
made lazily via inclusion of `DomTreeUpdater` and its use with
`SplitBlockAndInsertIfThen`. Preservation was maintained when updated to
the new pass manager in 3bd517205799. However, there was an overlooked
case where the `DominatorTree` would remain stale by the end of the Safe
Stack pass if the actions under `TryInlinePointerAddress` completed
successfully and modified the caller's CFG.
The conditions for a stale `DominatorTree` to exist are roughly:
1. Safe Stack obtains the Unsafe Stack pointer location as a `CallInst`
(i.e. one way is `-safestack-use-pointer-address`)
2. `__safestack_pointer_address` is defined and inlined successfully.
3. The inlining changes the CFG such that a recalculated `DominatorTree`
would differ.
4. `DominatorTree` remains unchanged since it is preserved and currently
not recalculated.
Here's a simple example that demonstrates the issue:
```
@unsafe_stack_pointer_a = thread_local global ptr null
@unsafe_stack_pointer_b = thread_local global ptr null
declare i32 @get_runtime_mode() nounwind willreturn memory(none)
declare void @escape(ptr)
define ptr @__safestack_pointer_address() alwaysinline {
entry:
%first = call i32 @get_runtime_mode()
%use_a = icmp eq i32 %first, 0
br i1 %use_a, label %a, label %b
a:
ret ptr @unsafe_stack_pointer_a
b:
ret ptr @unsafe_stack_pointer_b
}
define i32 @caller() safestack {
entry:
%unsafe = alloca i32, align 4
call void @escape(ptr %unsafe)
%second = call i32 @get_runtime_mode()
ret i32 %second
}
```
```
> opt -mtriple=x86_64-pc-linux-gnu -safestack-use-pointer-address -passes=require<libcall-lowering-info>,function(safe-stack,verify<domtree>) -disable-output example.ll
DominatorTree is different than a freshly computed one!
Current:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
[1] %entry {4294967295,4294967295} [0]
Roots: %entry
Freshly computed tree:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
[1] %entry {4294967295,4294967295} [0]
[2] %a.i {4294967295,4294967295} [1]
[2] %__safestack_pointer_address.exit {4294967295,4294967295} [1]
[2] %b.i {4294967295,4294967295} [1]
Roots: %entry
```
To avoid a stale `DominatorTree` by the end of the Safe Stack pass, I
propose calling `recalculate` on the `DominatorTree` for the function
which will have the call to `__safestack_pointer_address` inlined
assuming the inlining was successful and `DomTreeUpdater` is non-NULL.
Commit: 923902483c7a6937a65b9679795a247ae2a2ad56
https://github.com/llvm/llvm-project/commit/923902483c7a6937a65b9679795a247ae2a2ad56
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M lldb/include/lldb/Host/SafeMachO.h
Log Message:
-----------
[lldb] Attempt to unbreak building lldb with the 27 SDK (#223090)
See this report:
https://github.com/llvm/llvm-project/pull/222721#issuecomment-5636252813
Commit: 4e3b379b6cfcd13a11e26834756519430a9f9377
https://github.com/llvm/llvm-project/commit/4e3b379b6cfcd13a11e26834756519430a9f9377
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/include/mlir/CAPI/Wrap.h
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Support/DebugStringHelper.h
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Tools/mlir-pdll-lsp-server/Protocol.cpp
Log Message:
-----------
[MLIR] Fix -Wunused-template (#221480) (#223094)
This warning was enabled by default for clang 23 (although reverted in
23.1.1). Given someone might enable it in the future and the cleanup
seemed nice, we should just do it.
This was done primarily by removing static from templates in headers and
then deleting any unused templates in translation units.
Previously attempted to land this in #221480, but accidentally merged
into a user branch rather than main.
Commit: 675cfb91660e20bfc17456f347c01c310322fc9d
https://github.com/llvm/llvm-project/commit/675cfb91660e20bfc17456f347c01c310322fc9d
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
A llvm/test/CodeGen/NVPTX/atomics-system-scope-sm50.err.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
Log Message:
-----------
[NVPTX] Error on atomics with system scope pre-sm60 (#222458)
Pre-SM60, atomics could only have device scope.
`NVPTXDAGToDAGISel::getAtomicScope` can conservatively emit device scope
for all scopes that are not system scope. For system scope, we need to
error out.
This resolves a TODO in llvm/test/CodeGen/NVPTX/cmpxchg.ll. Update that
and llvm/test/CodeGen/NVPTX/cmpxchg.ll to use SM60 now, demonstrating
correct lowering for system scope.
Commit: 5618cfdae27157a48ea670e6d817310404afb746
https://github.com/llvm/llvm-project/commit/5618cfdae27157a48ea670e6d817310404afb746
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Remove hasCZEROLike() in favor of directly checking for Zicond Extension (#221053)
Only Zicond implements a CZero-Like instruction now that Ventana
Conditional Operations have been removed.
Commit: 7727fb8eaed54b90d08a35fca4896a21a04349b2
https://github.com/llvm/llvm-project/commit/7727fb8eaed54b90d08a35fca4896a21a04349b2
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
Log Message:
-----------
[NFC][AMDGPU] Add tests for converting an i64 that fits in 32 bits (#223030)
It is converted with the full i64 expansion. The shifts by 31 leave a
value that does not fit.
The idea is to optimize conversion of an i64 that fits in 32 bits from
its low half.
Commit: 355cbe15b1c7694cab8590ecd773087b78a31121
https://github.com/llvm/llvm-project/commit/355cbe15b1c7694cab8590ecd773087b78a31121
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Implement MonotonicDescriptor (#214490)
RFC link:
https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442
"Monotonic" variable is similar to induction variable, but its value is
updated under some condition, e.g.:
```
int idx = 0;
for(int i = 0; i < n; ++i) {
// some uses of idx
if (cond)
++idx;
}
```
In this example, `i` is induction variable and `idx` is monotonic
variable: it's updated only when cond == true. In LLVM IR, this looks
like:
```
loop_header:
%monotonic_phi = phi [ %start, %preheader ], [ %update, %latch ]
br i1 %do_step, label %step_bb, label %latch
step_bb:
%step = add/gep %monotonic_phi, %step_val
br label %latch
latch:
%update = phi [ %monotonic_phi, %loop_header ], [ %step, %step_bb ]
br label %loop_header
```
This initial patch only matches the case where `%update` directly
selects between the `%monotonic_phi` or the step. We also limit the
descriptor to only matching cases where all users of the
`%monotonic_phi` are loads/stores that can be mapped to expandloads or
compresstores.
This is a continuation Sergey Kachkov's patch (#140720).
---------
Co-authored-by: Sergey Kachkov <sergey.kachkov at syntacore.com>
Commit: 4e865028f0563584bde4e54858855ba4f45946ad
https://github.com/llvm/llvm-project/commit/4e865028f0563584bde4e54858855ba4f45946ad
Author: David Tellenbach <dtellenbach at apple.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
Log Message:
-----------
[AArch64] Form CCMP for CBB and CBH (#221113)
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
form CCMP. However, in the case of CBB and CBH, splitting the fused
conditional branch in CmpBB could require the insertion of explicit
zero- or sign-extensions for both operands. In the Head block we can
cheaply fuse at least one of the extensions into cmp.
We therefore convert CBB and CBH unconditionally when we find them in
the Head block. In the CmpBB block, we only do the transformation if
neither operands needs an extension.
Commit: 2c30f74239871203b0a998cd4797e01c3338a9fa
https://github.com/llvm/llvm-project/commit/2c30f74239871203b0a998cd4797e01c3338a9fa
Author: PiJoules <leonardchan at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
A llvm/test/Transforms/RelLookupTableConverter/AArch64/dynamic_relocs.ll
M llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
R llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
A llvm/test/Transforms/RelLookupTableConverter/relative_lookup_table.ll
Log Message:
-----------
[llvm] Avoid PREL32 overflow to .data.rel.ro on AArch64 and re-enable (#222809)
Under the [AArch64 Small Code
Model](https://github.com/ARM-software/abi-aa/blob/main/sysvabi64/sysvabi64.rst#code-models),
the text segment (containing .text and .rodata) is limited to 2GB, but
the combined span of text and data segments can be up to 4GB.
When a relative lookup table is emitted in .rodata but references target
operands that require dynamic relocations (placed in .data.rel.ro in the
data segment), the distance between .rodata and .data.rel.ro can legally
exceed the 2GB range of signed 32-bit R_AARCH64_PREL32 relocations.
In this PR:
1. Ensure that on AArch64, lookup table operands do not need dynamic
relocations. If the lookup table were in `.rodata` (text segment), then
any of the target components would need to be in the data segment, so
the dynamic reloc check would suffice.
2. Re-enable RelLookupTableConverter for AArch64 (while keeping Darwin
disabled as before).
3. Limit the existing `AArch64/no_relative_lookup_table.ll` test to just
darwin aarch64.
4. Move the `X86/relative_lookup_table.ll` into the parent dir since
those checks are (mostly) generic, and allow those same checks to be run
for aarch64. That also includes a minor refactor for not checking the
`unnamed_addr` bit since `unnamed_addr` is
[dropped](https://github.com/llvm/llvm-project/blob/6959b7d081df5fb2349e67e0d8e8e87841fa10d9/llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp#L82)
for aarch64.
AI: Gemini was used to help make this patch and debug the issue. I
reviewed this PR to the best of my ability before submitting.
Commit: f471750e042c5da3daf947169c0125e58300df0d
https://github.com/llvm/llvm-project/commit/f471750e042c5da3daf947169c0125e58300df0d
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/docs/CIR/CleanupAndEHDesign.md
Log Message:
-----------
[CIR] Document dynamic exception specification design (#222451)
This change adds documentation for the CIR handling of dynamic exception
specification handling in pre-C++17 code. This is not yet implemented.
The implementation will follow in a series of changes based on this
design.
This documentation was generated by Claude Opus 5, based on an
interactive planning session in which I worked out the details of how I
want to implement this feature. I have carefully read the entire
document to verify that it correctly matches my intended implementation.
Commit: 5b1d7415a6cf8f4799b4f586417346abf0c56e84
https://github.com/llvm/llvm-project/commit/5b1d7415a6cf8f4799b4f586417346abf0c56e84
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A flang/include/flang/Optimizer/Builder/Runtime/CUDA/Support.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
A flang/lib/Optimizer/Builder/Runtime/CUDA/Support.cpp
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Synchronize context before finalization (#223058)
Commit: e471938cf2c9647a33458eed6ad5647b6323d153
https://github.com/llvm/llvm-project/commit/e471938cf2c9647a33458eed6ad5647b6323d153
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A llvm/test/Transforms/AggressiveInstCombine/RISCV/lit.local.cfg
Log Message:
-----------
[AggressiveInstCombine] Add lit.local.cfg to RISCV test directory. NFC (#223067)
To fix buildbot failures after #220310.
Commit: fe36473cb62cca28c14b7174c0797cb74bcdfc7e
https://github.com/llvm/llvm-project/commit/fe36473cb62cca28c14b7174c0797cb74bcdfc7e
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Let amdgcn_lerp and ds_swizzle use the generic codegen path (#222204)
__builtin_amdgcn_lerp and __builtin_amdgcn_ds_swizzle both map 1:1 onto
concrete (non-overloaded) intrinsics and carry the ClangBuiltin<> marker
in IntrinsicsAMDGPU.td, so EmitBuiltinExpr already lowers them
automatically by forwarding the arguments to the intrinsic.
Commit: bb962e790106c624e0668118d0b7d92c706c2da4
https://github.com/llvm/llvm-project/commit/bb962e790106c624e0668118d0b7d92c706c2da4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/bedrock/SocketHandle.h
M orc-rt/lib/bedrock/CMakeLists.txt
A orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/bedrock/SocketHandleTest.cpp
A orc-rt/test/unit/bedrock/SocketTestUtils.h
A orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
Log Message:
-----------
[orc-rt] Add SocketHandle, NativeSocketHandle APIs (#223114)
SocketHandle is an owning wrapper for a NativeSocketHandle value, and
closes the native socket on destruction.
NativeSocketHandle is a typedef for the platform's native socket handle
type.
Only POSIX is implemented in this patch (in sys/posix/SocketHandle.cpp).
Windows support will be added later.
This will be used for an upcoming SimpleRemote-based ControllerAccess
implementation that uses sockets for transport (SocketSimpleRemoteCA).
Commit: 25fe99bf939c50c7064e714a7edcbeb445bb9dc1
https://github.com/llvm/llvm-project/commit/25fe99bf939c50c7064e714a7edcbeb445bb9dc1
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
Log Message:
-----------
[ORC] Retire rt::SimpleExecutorMemoryManager* for sps_ci (#223113)
Move all clients to the sps_ci SimpleNativeMemoryMap / MemMgr
counterparts and retire the old rt::SimpleExecutorMemoryManager*
interface names.
Commit: 64a6af1666c9bbb63eb86c0697a3709a4cca8e50
https://github.com/llvm/llvm-project/commit/64a6af1666c9bbb63eb86c0697a3709a4cca8e50
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
A clang/test/CIR/IR/invalid-version.cir
A clang/test/CIR/IR/version.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
Log Message:
-----------
[CIR][OpenCL] Add OpenCL language version module attributes (#219687)
Add structured CIR module attributes for OpenCL and C++ for OpenCL
language versions. Verify their module-level placement and version
components so lowering can consume explicit source-language version
state.
Assisted-by: Codex / GPT-5.6 Sol
Commit: ba3010d7e4520b6aee926f878c5c1771f1c2a6f3
https://github.com/llvm/llvm-project/commit/ba3010d7e4520b6aee926f878c5c1771f1c2a6f3
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
A clang/test/CIR/CodeGenOpenCL/version.cl
M clang/test/CodeGenCUDASPIRV/kernel-cc.cu
M clang/test/CodeGenHIP/hipspv-kernel.cpp
A clang/test/SemaHIP/atomic-init.hip
Log Message:
-----------
[CIR][OpenCL] Emit OpenCL language version metadata in CIR (#219688)
Emit OpenCL and C++ for OpenCL language version attributes from CIRGen.
Preserve the compatible OpenCL version and the C++ for OpenCL version
separately so later lowering does not infer one from the other.
Assisted-by: Codex / GPT-5.6 Sol
Commit: 070455b3f2f77dbd1d5121a9d1bc3d9a3e3f65bc
https://github.com/llvm/llvm-project/commit/070455b3f2f77dbd1d5121a9d1bc3d9a3e3f65bc
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/readability/convert-member-functions-to-static.cpp
Log Message:
-----------
[clang-tidy] Fix convert-member-functions-to-static crash on attributed methods (#223007)
Fixes #222951
Commit: 78f557806dca9c81453e94c038409fb9ad49d063
https://github.com/llvm/llvm-project/commit/78f557806dca9c81453e94c038409fb9ad49d063
Author: shivaramaarao <58245296+shivaramaarao at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
A flang/test/Lower/OpenMP/omp-lib-integer-wrappers.f90
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M openmp/device/include/Interface.h
M openmp/device/src/State.cpp
M openmp/module/omp_lib.F90.var
M openmp/runtime/src/dllexports
M openmp/runtime/src/include/omp.h.var
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_csupport.cpp
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_ftn_os.h
M openmp/runtime/src/kmp_stub.cpp
A openmp/runtime/test/api/kmp_integer_8_apis.f90
Log Message:
-----------
[OpenMP] [Flang] Add Fortran integer(kind=8) overloads for omp_lib APIs (#221451)
Fortran code that uses integer(8) arguments, including
-fdefault-integer-8, did not match omp_lib interfaces declared with
omp_integer_kind (typically kind 4). Added *_8 specific procedures to
named generic interfaces in omp_lib, exported matching Fortran and C
runtime entry points, and implemented the *_8 functions as thin wrappers
that saturate-convert arguments to 32-bit and call the existing APIs.
Commit: a67c8f208e8710ad8b6b6e2ca4de57e4e0db7178
https://github.com/llvm/llvm-project/commit/a67c8f208e8710ad8b6b6e2ca4de57e4e0db7178
Author: Kaviya Rajendiran <67495422+kaviya2510 at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/frame-pointer-forwarding.f90
A flang/test/Transforms/function-attr-frame-pointer.fir
Log Message:
-----------
[Flang][Driver]Implemented support for option -momit-leaf-frame-pointer/-mno-omit-leaf-frame-pointer in flang (#216700)
Added support for `-momit-leaf-frame-pointer` /
`-mno-omit-leaf-frame-pointer` in the Flang compiler.
- The driver resolves the flags via `getFramePointerKind()` and forwards
`-mframe-pointer=<kind>` to flang -fc1, resulting in the LLVM IR
function attribute "frame-pointer"
- These options, used with `-fno-omit-frame-pointer`, control whether
leaf functions (functions that don't call other functions) retain or
omit the frame pointer.
- `fno-omit-frame-pointer -momit-leaf-frame-pointe`r : Keep the frame
pointer in non-leaf functions, but omit it in leaf functions (produces
"frame-pointer"="non-leaf").
- `fno-omit-frame-pointer -mno-omit-leaf-frame-pointe`r : Keep the frame
pointer in all functions, including leaf functions (produces
"frame-pointer"="all").
Commit: 4388400c3d0a95b75a36f81c7edd2eb95c6d63ea
https://github.com/llvm/llvm-project/commit/4388400c3d0a95b75a36f81c7edd2eb95c6d63ea
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/test/IR/invalid-builtin-types.mlir
M mlir/test/IR/parser.mlir
Log Message:
-----------
[mlir] Remove the memory space attribute restriction on memref types (#222995)
Follow-up to #187682. `isSupportedMemorySpace` only rejected builtin
attributes other than IntegerAttr/StringAttr/DictionaryAttr. This is a
leftover from when memory spaces were restricted to integers, and is now
inconsistent.
Commit: eff88db8f004bf74c54c65bd39a3fc2fb27969f0
https://github.com/llvm/llvm-project/commit/eff88db8f004bf74c54c65bd39a3fc2fb27969f0
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.h
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
M clang/test/CIR/CodeGenOpenCL/version.cl
A clang/test/CIR/Lowering/opencl-version-metadata.cir
Log Message:
-----------
[CIR][OpenCL] Lower OpenCL language version metadata to LLVM dialect (#219689)
Propagate CIR OpenCL language version module attributes as LLVM dialect
named metadata before LLVM IR translation.
Assisted-by: Codex / GPT-5.6 Sol
Commit: cebfe6c25f45c81f7be238c835828b97f48730ab
https://github.com/llvm/llvm-project/commit/cebfe6c25f45c81f7be238c835828b97f48730ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/Assembler/llvm.loop.align.ll
A llvm/test/Verifier/llvm.loop.align.ll
Log Message:
-----------
IR: Add verifier checks and LangRef for llvm.loop.align (#221933)
Verify the nested !{!"llvm.loop.align", i32 N} tag.
Require exactly two operands, an integer constant of type i32 or
smaller, and a positive power-of-two value
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 1f13035dd3bec940226402c59bbb086ab703caeb
https://github.com/llvm/llvm-project/commit/1f13035dd3bec940226402c59bbb086ab703caeb
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
A libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.verify.cpp
Log Message:
-----------
[libc++] Test LWG4113: Disallow `has_unique_object_representations<Incomplete[]>` (#169446)
We have been rejecting `has_unique_object_representations<Incomplete[]>`
since LLVM 6.
Some related change landed in Clang 19 due to
6451806ef73bb033be3f6e1599f3bcb224943206, and then a follow-up change
ae9990ed965118e7274a52399b43e3b9fb419a54 simplified error messages.
Test coverage for incomplete enumeration types is skipped for Clang-cl
mode, because an incomplete enumeration type is incorrectly considered
to be complete. See https://llvm.org/PR169472.
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 25728f8e380096df53f3aa966068ec3a24271b30
https://github.com/llvm/llvm-project/commit/25728f8e380096df53f3aa966068ec3a24271b30
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
A llvm/test/CodeGen/AArch64/misched-postra-only1.mir
Log Message:
-----------
[MISched] Fix post-RA pickOnlyChoice debug logs (#222927)
On the way, adding a stable test for `pickOnlyChoice()` scheduling paths
directly, which has been missing, while filechecking the fixed tracing.
Commit: cad1b33322a4000bad6974b4c40ee5bff987eb89
https://github.com/llvm/llvm-project/commit/cad1b33322a4000bad6974b4c40ee5bff987eb89
Author: lntue <lntue at google.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
Log Message:
-----------
[libc] Pass correct system include flag for macOS. (#223116)
Commit: e17b8cb5341d42f805c538236771edafa737a87e
https://github.com/llvm/llvm-project/commit/e17b8cb5341d42f805c538236771edafa737a87e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/TargetParser/Triple.cpp
A llvm/test/Assembler/module-flags-thread-model.ll
A llvm/test/Linker/module-flags-thread-model.ll
A llvm/test/Verifier/module-flags-thread-model.ll
Log Message:
-----------
IR: Introduce "thread-model" module flag (#222768)
Introduce the replacement for TargetOptions::ThreadModel, but
does not yet wire up the uses. This maintains the current values,
but I question if it makes sense to retain "posix" as the default.
POSIX sounds very target opinionated, but isn't used in a non-binary
way anywhere. Alternatively we could have a simple singlethread binary
flag, or name this something more general.
Follows the precedent of float-abi. It happens the triple default
is just POSIX, but theoretically targets like AVR should be defaulting
to singlethread.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2706780356665d560cc5a38dee91e7377a6d6002
https://github.com/llvm/llvm-project/commit/2706780356665d560cc5a38dee91e7377a6d6002
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
Log Message:
-----------
[InstCombine] support trunc condition in foldSelectICmpAndAnd (#223132)
Reland https://github.com/llvm/llvm-project/pull/220690 with the fix for
asan failure see fixup commit
Commit: d41121260c37b1be088995b375d074f198942114
https://github.com/llvm/llvm-project/commit/d41121260c37b1be088995b375d074f198942114
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/MC/RISCV/tail-call.s
Log Message:
-----------
[RISCV] Add PseudoTAILX7, PseudoTAILReg for cf-protection-branch (#220657)
Previously, PseudoTAIL selected between X6 and X7 at encode time by
checking the Zicfilp feature bit via getTailExpandUseRegNo. This is
incorrect for the codegen path because -fcf-protection=branch can emit
lpad without requiring Zicfilp to be enabled.
Add PseudoTAILX7 for codegen: when cf-protection-branch is active,
ISelLowering and the machine outliner now emit PseudoTAILX7 which
always expands using X7. The existing PseudoTAIL behavior is unchanged
— it still selects X6 or X7 based on Zicfilp at encode time, as
documented in the assembler manual.
Also add PseudoTAILReg ("tail address, register") assembly form that
lets users explicitly specify the scratch register for AUIPC+JALR
expansion, per the proposed syntax in
https://github.com/riscv-non-isa/riscv-asm-manual/pull/227.
Commit: 3569a1f1d2cee5616a15a992ca49646447efaa47
https://github.com/llvm/llvm-project/commit/3569a1f1d2cee5616a15a992ca49646447efaa47
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[AMDGPU] Fix placement of FeatureSupportsXNACK (#223111)
This can't be put into 12_50_Common because of conflict in downstream
code.
Commit: 5eff11f8e9b56b1653950409355d829f48547127
https://github.com/llvm/llvm-project/commit/5eff11f8e9b56b1653950409355d829f48547127
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
M orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
Log Message:
-----------
[orc-rt] Reduce SimpleRemoteCA to transport-independent utils (#223141)
Reduce SimpleRemoteCA to the transport-independent parts: opcodes, setup
and hang-up payload encoding, message validation and dispatch, and the
table of calls awaiting a result. Subclasses are now responsible for the
connection state and synchronization, since they'll usually want to
implement these things for their transports anyway (or the transport
will already manage connection-state/synchronization).
takePendingCall becomes pure virtual, since subclasses must synchronize
access to the pending-call table.
The header moves from orc-rt-internal/ to orc-rt/: with the transport a
subclass concern, there's no reason to preclude library clients from
writing one.
Commit: 1ae00a52bbe432ff8174664ce28fb33cc600f6f0
https://github.com/llvm/llvm-project/commit/1ae00a52bbe432ff8174664ce28fb33cc600f6f0
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/float80.h
Log Message:
-----------
[libc] Enable Float80-type for x86_32 (#221408)
Enables for x86_32 by using Uint<96>
```CPP
struct Float80 {
#if __SIZEOF_LONG_DOUBLE__ == 12
UInt<96> bits;
#else
UInt128 bits;
#endif
```
for testing it on x86_32
it needs -m32 and --msse2 extra flags other than your usual cmake for x86_32
Commit: 0adddbb3a5f7f57614e8c59c87d37cec5421e514
https://github.com/llvm/llvm-project/commit/0adddbb3a5f7f57614e8c59c87d37cec5421e514
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Move Remove unused CheckExtern prototype (#223146)
And add an overload taking only a Block.
Commit: 66573c1ecdc0ce1dc5f1cbd7d22974a7eb4ccf5d
https://github.com/llvm/llvm-project/commit/66573c1ecdc0ce1dc5f1cbd7d22974a7eb4ccf5d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/pointer-iv-addrec.ll
Log Message:
-----------
[SCEV] Directly form add recurrences for simple pointer IVs. (#222915)
Add support for PN = PHI(Start, gep Self, LoopInvariant) to
createSimpleAffineAddRec.
This allows to handle simple pointer IVs without going through the more
expensive createAddRecFromPHI machinery in many cases.
This is not completely NFC: previously we created SCEVUnknown for a
trivial AddRec with step 0, now we return the start value.
This gives a modest geomean compile-time decrease
* stage1-O3: -0.05%
* stage1-ReleaseThinLTO: -0.06%
* stage1-ReleaseLTO-g: -0.06%
* stage1-aarch64-O3: -0.07%
* stage2-O3: -0.05%
* clang build: -0.08%
With larger decreases for more SCEV-heavy workloads.
https://llvm-compile-time-tracker.com/compare.php?from=c1b661fde124399f0484c4b39501b37613cc4757&to=5cd19e23596c86eae9607286efe86b7a3e885a86&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/222915
Commit: e1b6027992df8846729ebfaacc9d3ac8573dd106
https://github.com/llvm/llvm-project/commit/e1b6027992df8846729ebfaacc9d3ac8573dd106
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/induction-cost.ll
Log Message:
-----------
[LV] Add test for cost of widened pointer induction (NFC). (#223153)
Add a cost test where the pointer induction is used as a value and
remains a VPWidenPointerInductionRecipe.
PR: https://github.com/llvm/llvm-project/pull/223153
Commit: 345d699de809ee2962307df4ae0bd95f791275b3
https://github.com/llvm/llvm-project/commit/345d699de809ee2962307df4ae0bd95f791275b3
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Remove dead functions and declarations (NFC) (#223126)
SelectionDAG::getStore (with Offset): Added on July 31, 2026 in commit
c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0 without a definition or any
callers.
SelectionDAG::getIndexedLoadVP, SelectionDAG::getIndexedStoreVP: Added
on August 31, 2021 in commit 524ded7d01a700aa6473d09a877be13fe45b85a3
without any callers.
SelectionDAG::getTruncStridedStoreVP: Added on March 10, 2022 in commit
28cfa764c2e3d36b856b3e70d49f17088b90c1f5 without any callers.
Assisted-by: Antigravity
Commit: d7d7992e58674a2e9ad1ae42e4a627b7fff24cef
https://github.com/llvm/llvm-project/commit/d7d7992e58674a2e9ad1ae42e4a627b7fff24cef
Author: Zhige Chen <zhige_chen at outlook.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/tools/llubi/fp_cast.ll
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Implement fast-math flags for `uitofp`/`sitofp` (#222858)
Closes #203773
Commit: eb9844b5ceee01c9d9fad92cbcd027c5798c5ed4
https://github.com/llvm/llvm-project/commit/eb9844b5ceee01c9d9fad92cbcd027c5798c5ed4
Author: Hamed <hamedghorbani17 at live.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/ms-setjmp.c
Log Message:
-----------
[clang][ARM] Use sponentry for setjmp on Windows ARM32 (#222366)
On Windows, _setjmp and _setjmpex take a second argument, the frame,
which the CRT stores in the jmp_buf and which longjmp later hands to
RtlUnwindEx as the frame to unwind. On aarch64, this is the stack pointer
on entry to the function, while x86_64 takes the function frame address.
ARM expects the same as aarch64 here, the stack pointer on entry.
Assisted-by: Claude Opus 5 (Anthropic)
Commit: 148ee2b266b73a49f1f31d0bd17d4818b91bee9f
https://github.com/llvm/llvm-project/commit/148ee2b266b73a49f1f31d0bd17d4818b91bee9f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps.ll
Log Message:
-----------
[SLP] Fix dep accounting when cancelling a bundle with copyable elements
Restore the parent-edge copyable data as a user of the instruction only
if the cancelled element displaced it at creation (chained copyable
self-use); otherwise the extra user dependency is never released and
scheduling asserts.
Fixes #223139
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223174
Commit: ca8f82b625494996d4f9f61f30d25b62a5660dca
https://github.com/llvm/llvm-project/commit/ca8f82b625494996d4f9f61f30d25b62a5660dca
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Support/KnownFPClass.cpp
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/unittests/Support/KnownFPClassTest.cpp
Log Message:
-----------
[KnownFPClass] Restrict KnownFPClass::bitcast/toKnownBits deductions to verified FP semantics (#221133)
`KnownFPClass::bitcast` and `KnownFPClass::toKnownBits` previously made
deductions for floating-point semantics whose bit representations had
not been verified.
I have made it so `KnownFPClass::bitcast` and
`KnownFPClass::toKnownBits` return `fcAllFlags`/unknown for any
`APFloat` semantics we have not verified. Currently, this prevents
potentially invalid deductions for `PPCDoubleDouble` (mostly in regards
to the signbit and endianess). It also allows these functions to be
"safely" used with the 4/6/8 bit floating point types since we
conservatively return unknown.
Currently the list of supported/verified semantics for both `bitcast`
and `toKnownBits` are:
```
IEEEhalf
BFloat
IEEEsingle
IEEEdouble
IEEEquad
x87DoubleExtended
```
Commit: d65afea7b5c25b7be41dd86eaedaac263f04cd40
https://github.com/llvm/llvm-project/commit/d65afea7b5c25b7be41dd86eaedaac263f04cd40
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 0f47e798205b (#223189)
Commit: b6ca452aea0d805fd1f2f98a609e30692184a5bf
https://github.com/llvm/llvm-project/commit/b6ca452aea0d805fd1f2f98a609e30692184a5bf
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 4214b4601f49 (#223190)
Commit: 5d188c401f7d64daf08b7aac887d93aa5073e1dd
https://github.com/llvm/llvm-project/commit/5d188c401f7d64daf08b7aac887d93aa5073e1dd
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
Log Message:
-----------
[ELF] Version scripts: simplify version suffix handling. NFC (#223194)
Use StringRef::split instead of index arithmetic.
Commit: 387c965bb013d14dbcee52098e714c27d6f98249
https://github.com/llvm/llvm-project/commit/387c965bb013d14dbcee52098e714c27d6f98249
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
R lld/test/ELF/dynamic-list-cpp.s
M lld/test/ELF/dynamic-list-glob.s
R lld/test/ELF/version-script-reassign-glob.s
A lld/test/ELF/version-script-wildcard-precedence.s
Log Message:
-----------
[ELF,test] Cover wildcard precedence in version scripts and dynamic lists (#223195)
version-script-wildcard-precedence.s, renamed from
version-script-reassign-glob.s, covers more cases.
dynamic-list-glob.s absorbs dynamic-list-cpp.s and adds an extern "C++"
wildcard, which had no --dynamic-list coverage.
Commit: 474b7358a90e4f22b04e6a0933381d239fb7044e
https://github.com/llvm/llvm-project/commit/474b7358a90e4f22b04e6a0933381d239fb7044e
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/tools/llc/CMakeLists.txt
R llvm/tools/llc/NewPMDriver.cpp
R llvm/tools/llc/NewPMDriver.h
A llvm/tools/llc/lib/CMakeLists.txt
A llvm/tools/llc/lib/NewPMDriver.cpp
A llvm/tools/llc/lib/NewPMDriver.h
A llvm/tools/llc/lib/llcdriver.cpp
R llvm/tools/llc/llcdriver.cpp
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[llc] Move LLVMLlcDriver implementation into lib (#222840)
Addressing comment
[here](https://github.com/llvm/llvm-project/pull/221896#discussion_r3982250858)
Commit: 745ff71c706f6a55c7fa1cda660860925e0b2739
https://github.com/llvm/llvm-project/commit/745ff71c706f6a55c7fa1cda660860925e0b2739
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Consistently use RISCVSubtarget::is64Bit() instead of isRV32/isRV64. (#223038)
99% of code uses RISCVSubtarget::is64Bit().
Maybe we should consider removing is64Bit(), and using isRV64() instead
but right now I think we should be consistent.
Commit: 7a7cea921c3e450903b57e5f4b2992f1dce4c410
https://github.com/llvm/llvm-project/commit/7a7cea921c3e450903b57e5f4b2992f1dce4c410
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
Log Message:
-----------
[ELF] Version script: simplify wildcard matching. NFC (#223202)
Replace a loop over non-"*" wildcard patterns and another loop over "*"
with a single loop that calls the inlined
`SymbolTable::assignWildcardVersion`.
Commit: 051c49202368a8478661548b5b8de03549d9d183
https://github.com/llvm/llvm-project/commit/051c49202368a8478661548b5b8de03549d9d183
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/test/SemaCXX/ms-ctor-closure.cpp
Log Message:
-----------
[clang][test] Remove an uninitialized read in a test case (#223120)
This test case was added in
https://github.com/llvm/llvm-project/pull/222212. Its purpose is to
check that explicit constructor calls work at compile time.
However, the test case left var.a uninitialized and the copy constructor
reads an unitialized value. MSVC diagnoses this, but clang currently
fails to do so.
Change the test case to remove the unrelated problem of an uninitialized
read.
Commit: 0d55d0bf81ce2e0d6d3c46b7835efb788bde634a
https://github.com/llvm/llvm-project/commit/0d55d0bf81ce2e0d6d3c46b7835efb788bde634a
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/ICF.cpp
Log Message:
-----------
[ELF] Parallelize ICF's section sort. NFC (#223216)
All candidate sections are sorted by a serial stable_sort, which is a
scalability bottleneck. Switch to parallel sort using Schwartzian
transform. Linking Chromium with --icf=all (--threads=8) drops from
4.47s to 3.18s.
Commit: 8ea78db3c1bf6522ccaf6d75e73a03d80f08a00b
https://github.com/llvm/llvm-project/commit/8ea78db3c1bf6522ccaf6d75e73a03d80f08a00b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/Driver/wasm-toolchain.c
Log Message:
-----------
clang/WebAssembly: Add -femscripten-exceptions driver flag (#221431)
Commit: c4628f0385efd0d0d3c9d9ee0b88f89fdd4bd1f3
https://github.com/llvm/llvm-project/commit/c4628f0385efd0d0d3c9d9ee0b88f89fdd4bd1f3
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] Disable linker version scripts for Emscripten (#221647)
Emscripten reports itself as a Unix-like CMake platform, causing LLVM to
set `LLVM_HAVE_LINK_VERSION_SCRIPT` and pass GNU/ELF `--version-script`
options when linking shared libraries.
Emscripten uses `wasm-ld`, which does not support GNU version scripts
and currently reports:
```
em++: warning: ignoring unsupported linker flag: `--version-script`
```
Treat Emscripten like the other platforms without version-script
support. This prevents LLVM and Clang shared-library targets from
passing an unsupported linker option.
This was encountered while building LLVM 23.1.0 for both wasm32 and
wasm64 with Emscripten 6.x in emscripten-forge.
```
[ 45%] Building CXX object tools/clang/lib/Sema/CMakeFiles/obj.clangSema.dir/SemaExceptionSpec.cpp.o
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
.....
[100%] Linking CXX shared library ../../lib/libLTO.so
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
.....
[100%] Linking CXX shared library ../../../../lib/libclang.so
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
```
Commit: 4dd595b99e4e0a9c7994726065ab99d6c2b071c2
https://github.com/llvm/llvm-project/commit/4dd595b99e4e0a9c7994726065ab99d6c2b071c2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Log Message:
-----------
Wasm: Remove incorrect assumption that intrinsics cannot throw (#221180)
A few intrinsics are marked as Throws
Commit: 709ef4b96668471c7be0bd67abece4ebfce62a22
https://github.com/llvm/llvm-project/commit/709ef4b96668471c7be0bd67abece4ebfce62a22
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
A llvm/test/CodeGen/ARM/cbz-no-kill-flag.mir
Log Message:
-----------
ARM: Avoid relying on kill flags for determining CPSR liveness (#222873)
When forming CBZ/CBNZ in ARMConstantIslands, check if CPSR is live-out
of the block instead of relying on the kill flag. Kill flags have been
soft deprecated for over a decade.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
Commit: 31a1c03fe67cccd917f11e5ab50cc425770c1400
https://github.com/llvm/llvm-project/commit/31a1c03fe67cccd917f11e5ab50cc425770c1400
Author: Brad Smith <brad at comstyle.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Unix/Path.inc
Log Message:
-----------
[Support] Implement getMainExecutable for OpenBSD with getexecpath() (#220141)
OpenBSD now has a proper function to retrieve the executable and path.
Commit: eae1ec7b1d6752d7d94214e4beaf724ce560aed2
https://github.com/llvm/llvm-project/commit/eae1ec7b1d6752d7d94214e4beaf724ce560aed2
Author: Pkuyo <miku_mi at foxmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
Log Message:
-----------
[SelectionDAG] Handle scalable INSERT_SUBVECTOR in ComputeNumSignBits (#221631)
Handle scalable INSERT_SUBVECTOR in SelectionDAG as a pre-fix for
#220976.
Add coverage for scalable subvectors and fixed subvectors inserted into
scalable vectors.
Commit: 3deeb018ed1d1c61ad9e1798161128e0202e7920
https://github.com/llvm/llvm-project/commit/3deeb018ed1d1c61ad9e1798161128e0202e7920
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps-2.ll
Log Message:
-----------
[SLP]Fix dep accounting when cancelling a bundle with repeated copyable users
Skip duplicate users instead of stopping at the first one when walking
the operand lanes; an early stop misses a trailing self-use lane, the
displaced parent-edge copyable data is never restored, and scheduling
asserts.
Fixes #223225
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223236
Commit: f8a96032096158c992ea4cd369e43068b2b072a7
https://github.com/llvm/llvm-project/commit/f8a96032096158c992ea4cd369e43068b2b072a7
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
Log Message:
-----------
[lldb] Bound Mach-O symtab allocation to the file size (#222955)
Opening a Mach-O file whose LC_SYMTAB claims far more symbols than the
file could possibly hold makes lldb ask for hundreds of gigabytes. A
128-byte file with LC_SYMTAB.nsyms = 0x80000000 (the new unit test's
input, built with yaml2obj) reproduces it through `lldb-target-fuzzer`,
the harness that found this bug:
```
==45515== ERROR: libFuzzer: out-of-memory (malloc(171798691840))
#8 std::__1::__split_buffer<lldb_private::Symbol,...>::__split_buffer(...)
#9 std::__1::vector<lldb_private::Symbol,...>::resize(unsigned long)
#10 lldb_private::Symtab::Resize(unsigned long)
#11 ObjectFileMachO::ParseSymtab(lldb_private::Symtab&)
```
`ParseSymtab()` sizes the destination `Symtab`'s `vector<Symbol>`
directly
from `nsyms` and `nindirectsyms`, two counts read from the file's
`LC_SYMTAB` and `LC_DYSYMTAB` commands. `nlist_data`, the view already
built earlier in the function from the bytes the file actually has at
`symoff`, is far smaller than what those counts claim; the guard gating
this code only checks that it is non-empty, not how many nlist records
it can back.
Bound both counts by what `nlist_data` and `indirect_symbol_index_data`
(already clipped to the available bytes) can hold, instead of trusting
the file's counts outright.
Add a unit test whose LC_SYMTAB claims about two billion symbols in a
128-byte file; completing quickly instead of reserving that much space
is the regression check.
Assited-by: claude
Commit: 3c77eb3a3f2793a75e0ce86d96076637d5989bea
https://github.com/llvm/llvm-project/commit/3c77eb3a3f2793a75e0ce86d96076637d5989bea
Author: Stanislav Bardyuk <6258615+kodlan at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
Log Message:
-----------
[DAGCombiner] Only fold shift+mask compare to rotate if the shift amount divides the bit width (#220743)
DAGCombiner::visitSETCC can turn `(X << S) == (X & -(1 << S))` (or the
srl variant) into `rotl(X, S) == X`, and the other way around, when the
target prefers one form over the other. The two forms are only equivalent when
S divides the bit width. The check used `isPowerOf2(S)`, which is the same
thing for i8/i16/i32/i64 but not for odd widths like i3, where S = 2 is a
power of two that does not divide 3. On x86, which prefers the rotate,
the reporter's i3 function returned the wrong value for two of its eight
inputs.
This changes the `MayTransformRotate` flag passed to
`preferedOpcodeForCmpEqPiecesOfOperand` to check `NumBits % S == 0`
(with S != 0) and fixes the two comments that described the old rule. For legal
scalar types nothing changes. On illegal non power of two widths this
also lets a non power of two amount that divides the width use the rotate
(like i6 with S = 3); that is correct for the same reason and legalizes
through the usual rotate promotion, same as i6 with S = 2 did before. The x86
hook already honors the flag in both directions, so the fix lives in the
target independent code.
Tests: the i3 shl and lshr cases from the issue (must stay shift+mask), an
i6 / S = 3 case (3 divides 6, so the rotate is still allowed), and the
reporter's function.
Fixes #220542
Commit: baec9c34d1ecdbabca0cc100ed6de73986174938
https://github.com/llvm/llvm-project/commit/baec9c34d1ecdbabca0cc100ed6de73986174938
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
Log Message:
-----------
[AMDGPU] Fix fneg fold with multi use fadd/fma (#217573)
Commit: db65ace07649b2beb8cdbdfd6af4901809df9966
https://github.com/llvm/llvm-project/commit/db65ace07649b2beb8cdbdfd6af4901809df9966
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
Revert "[Clang] Refactor instantiation of declarations within concepts" (#223235)
This reverts llvm/llvm-project#221707
This broke std::map as reported in
https://github.com/llvm/llvm-project/issues/223220
Commit: d283a555109576cd92b35a88b4d110166043fb77
https://github.com/llvm/llvm-project/commit/d283a555109576cd92b35a88b4d110166043fb77
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/test/OffloadTools/clang-nvlink-wrapper/nvlink-wrapper.c
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
Log Message:
-----------
[clang-nvlink-wrapper] Fix response file handling for the nvlink wrapper (#220249)
Summary:
Response files were not handled correctly because the copied support
used the `nvlink` argument which is not supported by the argument
parser. Pass to the nvlink wrapper using the canonical format and then
reconstruct it when we execute the sub jobs
Fixes: https://github.com/llvm/llvm-project/issues/219914
Commit: 3409d079b5b76d0cdd51526b29aebd4143ecca64
https://github.com/llvm/llvm-project/commit/3409d079b5b76d0cdd51526b29aebd4143ecca64
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
Log Message:
-----------
[SLP][NFC]Add a test with missed widened boolean optimization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223245
Commit: ca2424325cd9247ac0c11cd2d1c8ea3fb07ab16e
https://github.com/llvm/llvm-project/commit/ca2424325cd9247ac0c11cd2d1c8ea3fb07ab16e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Reject guaranteed tail calls in call lowering (#216260)
The FPDiff immediate was being written to the wrong operand, corrupting
the callee GlobalAddress
Reject required tail calls like SelectionDAG does, and fix the stale
index for the one path that still needs it (cs.chain lowering)
Commit: 0c324f10322b490d66de738d73458f6f65460cdb
https://github.com/llvm/llvm-project/commit/0c324f10322b490d66de738d73458f6f65460cdb
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/MathExtras.h
Log Message:
-----------
[Support] Fix the return type of AddOverflow, SubOverflow, and MulOverflow (#223217)
This patch fixes the return type of the 3-argument overloads of
AddOverflow, SubOverflow, and MulOverflow to bool.
Without this patch, these functions are declared with a return type
of T:
template <typename T>
std::enable_if_t<std::is_signed_v<T>, T> AddOverflow(T X, T Y, T
&Result);
even though they return a boolean indicating whether an overflow
occurred, as stated in the comment:
/// Add two signed integers, computing the two's complement truncated
result,
/// returning true if overflow occurred.
Assisted-by: Antigravity
Commit: 23f2e449afa0b0de43939a03ea241bc17dfe1141
https://github.com/llvm/llvm-project/commit/23f2e449afa0b0de43939a03ea241bc17dfe1141
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
Log Message:
-----------
[SelectionDAG] Remove unused float promotion in DAGTypeLegalizer (NFC) (#223219)
This patch removes PromotedFloats along with GetPromotedFloat and
SetPromotedFloat. The Mapped bitmask in PerformExpensiveChecks is
adjusted accordingly, shifting the bit for SoftPromotedHalfs.
The last uses of DAGTypeLegalizer::GetPromotedFloat and
DAGTypeLegalizer::SetPromotedFloat were removed on January 26, 2026 in
commit a7d48bd305ef3aa4bd543da6f4cd8682a3d35c32 when TypePromoteFloat
and its associated DAG machinery were removed.
With these accessors gone, DAGTypeLegalizer::PromotedFloats is no longer
populated.
Assisted-by: Antigravity
Commit: c67808cf4426290e259f2cd4bd1a48516f9b8d7b
https://github.com/llvm/llvm-project/commit/c67808cf4426290e259f2cd4bd1a48516f9b8d7b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[OpenMP] Change association of some directives from "none" to "explicit" (#222703)
Certain declarative directives are associated with base language
declarations by having the declared entities explicitly listed as
arguments.
Previously these had "none" in OMP.td. Change them to "explicit" to be
consistent with the spec. The existing code does not require any
changes, since the only potentially affected code would be that which
checked the assocation for "none", and the only such cases were applied
to executable directives.
Commit: 483af6c1be7ca13eda7cc5314bb93185d21b272a
https://github.com/llvm/llvm-project/commit/483af6c1be7ca13eda7cc5314bb93185d21b272a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M flang/include/flang/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[OpenMP] Add definitions for REDUCTION_KIND and SHIFT clauses (#222745)
This is a barebones change to introduce the enum identifiers for these
clauses.
Commit: 240670d0d5dcd649bd3728871087c938b5e097f2
https://github.com/llvm/llvm-project/commit/240670d0d5dcd649bd3728871087c938b5e097f2
Author: MaoJiaping <maojiaping1 at huawei.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/include/llvm/Transforms/Utils/SplitModuleCommon.h
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/SplitModule.cpp
A llvm/lib/Transforms/Utils/SplitModuleCommon.cpp
M llvm/test/tools/llvm-split/unnamed.ll
Log Message:
-----------
[NFC][ModuleUtils] Move externalize() from module splitting utilities (#221181)
`SplitModule.cpp` and `AMDGPUSplitModule.cpp` each carry an identical
static `externalize()` helper that promotes local-linkage globals to
external + hidden visibility and assigns a stable name to unnamed
entities, so they are named consistently across module partitions.
This patch removes the duplication by moving the helper into
`ModuleUtils` as `llvm::externalize`, and updates both users to call the
shared implementation. No functional changes are intended.
This also prepares for upcoming module splitting utilities to reuse a
single, canonical implementation.
Development of this patch was assisted by AI and reviewed by me.
Commit: 860fb775d3d626af6e4a45ea5d62039718957d26
https://github.com/llvm/llvm-project/commit/860fb775d3d626af6e4a45ea5d62039718957d26
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-booleanized-leaves.ll
Log Message:
-----------
[SLP]Reduce logical and/or reductions in the wide leaf type
Logical and/or reductions on i1 with booleanized wide leaves (truncs
of same-op chains, zero-tests of values from [0, 1]) are performed in
the wide type, exposing the underlying consecutive values to the tree;
bit 0 of the result is the final value. Fixes the fragmented reduction
and the gather-of-scalars regression for compile-time-expanded Boolean
reductions.
Fixes #221167
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/221321
Commit: 588304bdb9ee0a9c8229db8c702415e80d05ad33
https://github.com/llvm/llvm-project/commit/588304bdb9ee0a9c8229db8c702415e80d05ad33
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
Log Message:
-----------
[SLP]Model copyable lanes of idempotent binops as op(V, V) when the operand column has a constant lane
The op(V, identity) form lets the reorder move the lane out of the
joined column, breaking the opcode-peer node; the symmetric form is
reorder-proof.
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/220252
Commit: f4ecba36726d6bede2ab58890dfcc861c2bb28a9
https://github.com/llvm/llvm-project/commit/f4ecba36726d6bede2ab58890dfcc861c2bb28a9
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
Log Message:
-----------
[KnownFPClass] Unify and refine interested classes for `KnownFPClass::log` (#219751)
Previously, `ValueTracking` and `GISelValueTracking` only called
`KnownFPClass::log` when the requested classes included NaN or infinity.
As a result, narrowly interested queries could miss unconditional
deductions, for example, `log(x)` is never subnormal or negative zero
(With the exception of `PPCDoubleDouble`
https://github.com/llvm/llvm-project/issues/217658).
This change makes the interested-class handling consistent between
`ValueTracking` and `GISelValueTracking`. The source is queried only
when its classes are needed, but `KnownFPClass::log` is always called so
its unconditional deductions are preserved.
Future work:
- Fixing `KnownFPClass::log` for `PPCDoubleDouble`.
AI disclosure:
I used OpenAI Codex (sol 5.6) to help write the unit tests, which I
reviewed and ran locally.
Commit: c1f1a288ccd67f9b9dadefda9c510aa7568022e7
https://github.com/llvm/llvm-project/commit/c1f1a288ccd67f9b9dadefda9c510aa7568022e7
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Complete upstream vector saturating shift left NEON builtins (#221507)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for the vector saturating shift left intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left).
This completes the family.
Port tests from `clang/test/CodeGen/AArch64/neon-intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`.
Commit: 0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
https://github.com/llvm/llvm-project/commit/0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
Log Message:
-----------
RegisterCoalescer: Remove empty subranges after merging subranges (#222050)
Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.
Exposed with subregister liveness once LiveIntervals runs before
TwoAddress.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: cff226a5716e4bc3589d4869066ea6687ed142ce
https://github.com/llvm/llvm-project/commit/cff226a5716e4bc3589d4869066ea6687ed142ce
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
Log Message:
-----------
[ConstraintElim] Fold sadd.with.overflow with a constant op. (#223239)
Generalize the overflow-math simplification to also allow simplifying
sadd.with.overflow if the second operand is constant, using
makeGuaranteedNoWrapRegion.
Note that this partially overlaps with the flag strengthening logic.
I'll share a patch soon to try to unify the code more.
No improvements in llvm-opt-benchmarks-nightly. It improves end-to-end
optimizations for Swift (which emits a lot of checked arithmetic) and
also Clang + UBsan.
An end-to-end improvement with overflow intrinsics is
https://llvm.godbolt.org/z/6nrj7aodd.
PR: https://github.com/llvm/llvm-project/pull/223239
Commit: 979b374a7ca7adc936d9339c1db79b0d6cda06db
https://github.com/llvm/llvm-project/commit/979b374a7ca7adc936d9339c1db79b0d6cda06db
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
Log Message:
-----------
[AggressiveInstCombine] Fix terminology in a few comments (NFC) (#222327)
Fix the comments (and a debug print) that say "dominated by trunc"
rather than "post-dominated".
Also fixes a Doxygen syntax (use \p instead of /p) and fix
capitalization in the middle of a sentence.
Commit: d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
https://github.com/llvm/llvm-project/commit/d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
Author: Taimuraz Kaitmazov <5769345+atassis at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
Log Message:
-----------
[MIRParser] Reject a one-element fixed-length vector type (#213290)
MIParser accepts `<1 x sN>` and then asserts while building the LLT, so
llc aborts during parsing instead of reporting a parse error:
```
Assertion `!EC.isScalar() && "invalid number of vector elements"' failed.
```
LLT has no one-element fixed-length vector. `getLLTForType`,
`getLLTForMVT` and
`LLT::changeElementCount` all map a one-element `ElementCount` to the
element
type through `LLT::scalarOrVector`, nothing calls `LLT::fixed_vector(1,
...)`,
and no in-tree .mir test uses the syntax. `verifyVectorElementCount`
already rejects 0 and anything above 2^16, so 1 was the remaining hole; it now
gets the same diagnostic instead of aborting the parser.
Scalable vectors are unaffected: `<vscale x 1 x sN>` is a valid type and
stays legal through the `HasVScale` check.
AI assistance: drafted with AI help; reviewed and validated by me.
Commit: ce73dba9552c93d1cc3abc481dff63a4ab6d0579
https://github.com/llvm/llvm-project/commit/ce73dba9552c93d1cc3abc481dff63a4ab6d0579
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
Log Message:
-----------
[clang][SPIR-V][AMDGPU] Fix variadic aggregate ABI classification for AMDGCN (#216326)
Mirror AMDGPUABIInfo fixed/variadic split
AMDGCNSPIRVABIInfo::classifyArgumentType did not distinguish fixed from
variadic arguments, so aggregates passed through `...` were
misclassified as indirect byref instead of direct
Commit: d91624c19074e219d5a5c5af45f48afd4cd9052a
https://github.com/llvm/llvm-project/commit/d91624c19074e219d5a5c5af45f48afd4cd9052a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
Log Message:
-----------
[AMDGPU] Fix MAI hazard scan missing 19-instruction-old hazards (#222040)
The scan only looked back 19 instructions, but gfx950 can need a gap of
20 after some MFMAs
A hazard exactly 19 instructions back was missed, so no wait was
inserted
Commit: 8864a4bb996d6bb541b0974d34991da40a643c90
https://github.com/llvm/llvm-project/commit/8864a4bb996d6bb541b0974d34991da40a643c90
Author: neoto <48843913+neoto at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
Log Message:
-----------
[Mips] Handle division by zero trap on MIPS1 (#201133)
LLVM currently emits the `teq` instruction for every arch version, but
`teq` is unsupported on MIPS1.
This special cases MIPS1 so that `bne(z)` and `break` are emitted
instead.
Compared to https://github.com/llvm/llvm-project/pull/81311, this should
also handle liveness as far as I can tell.
I didn't want to add another bool to the argument list so I combined
`IsMicroMips` and what was supposed to be `IsMips1` into an enum, which
feels much nicer in this case.
Besides that and the main change, I also changed the `hasSideEffects`
bit for `PseudoSDIV` and `PseudoUDIV`,
which allows the delay slot to be usefully filled - well, at least with
`-O1`+. This seems to be in line with what GCC does:
https://godbolt.org/z/zqcG5ha35
Tested using clang directly and through Zig's LLVM backend.
Closes https://github.com/llvm/llvm-project/issues/80554
Supersedes https://github.com/llvm/llvm-project/pull/81311
Commit: 85f694b3eeafc07e5c586fa15715facefba71094
https://github.com/llvm/llvm-project/commit/85f694b3eeafc07e5c586fa15715facefba71094
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
Log Message:
-----------
[ASan] Convert pointer-pair operands based on type (#218494)
`CreatePointerCast` was being called on everything without checking what
it actually is, so if the operand came from ptrtoint ... to i32 it just
crashes (its not a pointer).
now it check the type first - pointers get pointer-cast, ints get
zext/trunc'd to intptr width.
Fixes #217544
also edited regression tests for this
Commit: 4098f568c46e06b6df470111868b4c165dd80f4d
https://github.com/llvm/llvm-project/commit/4098f568c46e06b6df470111868b4c165dd80f4d
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Don't fold in_bounds for negative constant indices (#219681)
`isInBounds` checked only that the transfer *ends* inside the source:
return cstOp.value() + vectorSize <= sourceSize;
The `in_bounds` attribute promises more than that. Its definition in
VectorOps.td says accesses "(including the starting point)" may run
out-of-bounds when it is "false", so setting it to "true" is a claim
about the start of the transfer as well as its end.
With a negative constant index the two disagree. For
vector.transfer_read %m[-1] : memref<8xf32>, vector<4xf32>
`-1 + 4 <= 8` holds, so the fold set `in_bounds = [true]`, even though
element -1 is read from outside `%m`.
The same expression also overflows for a large enough index: at `index =
2^63 - 1` the addition wraps and the fold again reports `in_bounds =
[true]`. Computing the bound as `sourceSize - vectorSize` instead avoids
the addition entirely; both operands are static, non-negative dimension
sizes, so the subtraction cannot overflow.
This is a spec-conformance fix, not a live miscompile report. A negative
index into a memref is already undefined behaviour, and the masked
lowering would not have caught it either: the guard
`generateInBoundsCheck` emits in VectorToSCF is `memrefDim > index +
iv`, an upper-bound check only.
Adds three regression tests, each of which fails without the change.
Assisted-by: Claude
Commit: b7877e01cb1087d81fd72eb320c3c7d3f8e03500
https://github.com/llvm/llvm-project/commit/b7877e01cb1087d81fd72eb320c3c7d3f8e03500
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
Log Message:
-----------
[ConstraintElim] Derive an unsigned IV bound from a signed relational latch. (#222762)
For a known non-negative backedge (either via isKnownNonNegative or
because the increment is increasing), 0 <=s PN <= B holds and implies
that B is non-negative as well.
Use that to translate a signed condition to the equivalent unsigned one.
Note that the general signed->unsigned rewrite cannot catch this,
because the precondition also needs rewriting to unsigned.
No llvm-opt-benchmark-nightly impact, but it can help remove runtime
checks generated by sanitizers or Swift code. An end-to-end C example is
https://clang.godbolt.org/z/vbd91MjaM.
Alive2 Proof: https://alive2.llvm.org/ce/z/G3Mv7t
PR: https://github.com/llvm/llvm-project/pull/222762
Commit: 914e15cd29f78e01e15378cfccff97d42e6e9e82
https://github.com/llvm/llvm-project/commit/914e15cd29f78e01e15378cfccff97d42e6e9e82
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Move the LLVMContext out of ReplaceableMetadataImpl. NFC (#222085)
No ReplaceableMetadataImpl method reads its LLVMContext reference, and
ValueAsMetadata reaches the context through the wrapped Value. Keep the
reference in a derived ReplaceableUsesWithContext, used by the two
owners with no other route to it: MDNode's on-demand RAUW support and
DIArgList.
Rename the base to ReplaceableUses: it is the use map behind RAUW for
the metadata kinds that support it, not a pimpl, and the name matches
ContextAndReplaceableUses and getReplaceableUses().
Make the base destructor protected, since getOrCreate() hands out
ReplaceableUses pointers that must never be deleted. Delete copy
assignment explicitly; the LLVMContext reference suppresses it
implicitly.
sizeof(ValueAsMetadata) 152 -> 144.
Aided by Opus 5
Commit: d44791d35a4b15f3da7855790203ca14f7953410
https://github.com/llvm/llvm-project/commit/d44791d35a4b15f3da7855790203ca14f7953410
Author: averne <45773016+averne at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
Log Message:
-----------
[AMDGPU] IGLP: Sanitize user schedule hints (#221256)
Fixes the following ICE:
```cpp
extern __shared__ int lds[];
__global__
void kern_ice() {
auto _ = lds[threadIdx.x];
__builtin_amdgcn_sched_barrier(~0x380); // Allow all except DS instructions
}
```
See: https://godbolt.org/z/oGfT1TTa4
Commit: cba24d6a935382154b0487d09c1d91a0e2bda04b
https://github.com/llvm/llvm-project/commit/cba24d6a935382154b0487d09c1d91a0e2bda04b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Generalize folding IV increment into phi start value (NFC). (#223260)
simplifyRecipe folds
X = phi(0, IVInc)
IVInc = X + Step
Def = IVInc + Y
into a phi starting at Y, but only if Y is a live-in. Also allow values
defined in the block the phi's start value is coming from, which is
where the value conservatively has to be available.
NFC today, but preparation for modeling the full epilogue skeleton in
VPlan.
Commit: 8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
https://github.com/llvm/llvm-project/commit/8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
Log Message:
-----------
[NFC][AMDGPU] Fix clang-tidy warnings in VOPD related files (#223261)
Commit: 86858de86cb28299ebc9c0ce8a06e5a61ed6b261
https://github.com/llvm/llvm-project/commit/86858de86cb28299ebc9c0ce8a06e5a61ed6b261
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/test/Headers/__clang_hip_math.hip
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[ValueTracking] Propagate non-negativity through fptosi (#217868)
Fixes #217442
`fptosi` is poison when the rounded value does not fit in the result
type, so `computeKnownBits` can assume the conversion rounds towards
zero without wrapping. Negative subnormals and negative zero always
round to 0, so only sources known to never be a negative normal or
negative infinity (i.e. values <= -1.0) can produce a negative result.
This lets InstCombine fold `(int)fabs(x) < 0` to `false`, matching GCC,
and also benefits other magnitude-clamping intrinsics such as sqrt.
Commit: 667efaee701ae5345f4cde42f8b3e5b7f98549ee
https://github.com/llvm/llvm-project/commit/667efaee701ae5345f4cde42f8b3e5b7f98549ee
Author: Benji Smith <6193112+Benjins at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
Log Message:
-----------
[InstCombine] Fix fold of comparison of rotates (#223263)
rotate(X, AmtX) == rotate(Y, AmtY) -> rotate(X, AmtX - AmtY) == Y
This fold is usually valid, but implicitly assumed that the bit width
was a power of two. This is now checked and the transform doesn't fire
if the bit width isn't a power of two.
Fixes https://github.com/llvm/llvm-project/issues/223262
Commit: 0485ad7e469a56443094872c0f57f2870eccb654
https://github.com/llvm/llvm-project/commit/0485ad7e469a56443094872c0f57f2870eccb654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGen/thread-model.c
Log Message:
-----------
clang: Emit the "thread-model" module flag (#223156)
Commit: eb5c148b1cbc89c75a57a505d2533ae52e5bde44
https://github.com/llvm/llvm-project/commit/eb5c148b1cbc89c75a57a505d2533ae52e5bde44
Author: zhouguangyuan0718 <zhouguangyuan.xian at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
Log Message:
-----------
[MachineScheduler] Order fixed-FI memory operations by object offset (#219669)
## Summary
- sort fixed frame-index memory operands by their explicit stack offsets
- preserve the existing frame-index ordering for ordinary stack objects
and as a tie-breaker
- add an AArch64 MIR regression with fixed objects created out of offset
order
## Background
`BaseMemOpClusterMutation` currently orders frame-index bases by
frame-index number, adjusted for the stack growth direction. Fixed frame
objects are different from ordinary stack objects: they carry explicit
offsets, and their creation order is not required to match address
order.
As a result, a target clustering hook can receive two fixed objects in
reverse address order. AArch64's `shouldClusterFI` expects the incoming
fixed-object offsets to be ordered and aborts with `Object offsets are
not ordered` in an assertions-enabled build.
When both operands refer to fixed frame objects, compare their
`MachineFrameInfo` object offsets first. The existing frame-index
comparison remains the fallback, so the ordering of ordinary stack
objects is unchanged.
Make the ordering between fixed and non-fixed frame-index bases
explicit: non-fixed bases precede fixed bases for downward-growing
stacks, while fixed bases precede non-fixed bases for upward-growing
stacks. This preserves the existing cross-category ordering without
relying on non-fixed object offsets before frame layout.
The regression deliberately creates two fixed objects in an order that
disagrees with their explicit offsets. It covers both the legacy and new
machine-scheduler pass forms.
## AI assistance
OpenAI Codex was used to assist with the investigation, patch
preparation, testing, and drafting this PR description.
Commit: a129f830b8727c51c087db8278035d2c6f08da25
https://github.com/llvm/llvm-project/commit/a129f830b8727c51c087db8278035d2c6f08da25
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Use BitVector for RegisterSet in AsmMatcherEmitter (NFC) (#222525)
This patch replaces std::set with BitVector for RegisterSet in
AsmMatcherEmitter.
Without this patch, RegisterSet is represented as
std::set<const Record *, LessRecordByID>. On targets with large
register files like AMDGPU (~3,000 registers), repeatedly computing set
intersections and subset checks using std::set nodes incurs
significant overhead.
This patch assigns each register record a dense bit index ordered by
LessRecordByID. This allows us to represent RegisterSet as a
BitVector, enabling fast bitwise operations for set intersections and
subset checks.
This reduces the wall-clock time of generating AMDGPUGenAsmMatcher.inc
from 39.53s to 31.32s (a 20.8% speedup) across 3 runs while producing
bit-for-bit identical output across all targets.
Assisted-by: Antigravity
Commit: ac8aca03372551f8a8c999e86e5cb6cbfae3e307
https://github.com/llvm/llvm-project/commit/ac8aca03372551f8a8c999e86e5cb6cbfae3e307
Author: Yousef <yousef.idris01 at bcmail.cuny.edu>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
Log Message:
-----------
[GlobalISel] Add KnownBits support for G_INSERT_SUBVECTOR (#215048)
## Summary
Add KnownBits support for `G_INSERT_SUBVECTOR` in GlobalISel value
tracking.
The implementation splits the demanded elements between the original
vector and inserted subvector, ignores overwritten source elements, and
intersects the KnownBits information from the contributing operands.
Part of #150515.
## Testing
- `llvm-lit
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir`
- `llvm-lit llvm/test/CodeGen/AArch64/GlobalISel/knownbits-*.mir`
- 40/40 passed
Commit: 8497b7a259bbc8239d7358dc7bf83eb04b363c76
https://github.com/llvm/llvm-project/commit/8497b7a259bbc8239d7358dc7bf83eb04b363c76
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
Log Message:
-----------
[AMDGPU] Support TFE D16 format buffer loads on gfx8/10/11/12 (#211465)
gfx90a has no hardware encoding for TFE D16 format buffer loads, so
reject the combination there with a diagnostic. Other targets
(gfx8/10/11/12) do have real encodings, so add codegen support for them
instead of rejecting unconditionally.
Commit: 89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
https://github.com/llvm/llvm-project/commit/89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
Log Message:
-----------
[VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
No-op casts get folded to the input operand, which caused applyFlags to
crash if that was not a cast. Fix by avoiding creating such trivial
casts in the first place.
Commit: 82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
https://github.com/llvm/llvm-project/commit/82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
M clang/test/Driver/mingw.cpp
Log Message:
-----------
[Clang][MinGW] Link default-manifest.o if exists (#223084)
Some MinGW distributions provide a pre-compiled manifest xml to disable
the UAC escalation dialog.
Link automatically the manifest only if it exists when linking an
executable.
Do the same as Cygwin (#220875) and align with GCC.
Commit: 9bf40ce33523745e19328924593134e4510bfa5f
https://github.com/llvm/llvm-project/commit/9bf40ce33523745e19328924593134e4510bfa5f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
Log Message:
-----------
[AMDGPU] Fix s_buffer_load crash for illegal result types (#215483)
i1, i4, v2i1, v3i16, v6i8, and i128 had no SBUFFER_LOAD selection
pattern and crashed
Load a legal i32/vNi32 carrier instead and narrow/bitcast down to the
requested type
Commit: cf530065be1fccbd9ac1d5ccc7d55d80681de41d
https://github.com/llvm/llvm-project/commit/cf530065be1fccbd9ac1d5ccc7d55d80681de41d
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
Log Message:
-----------
[lldb][Process/FreeBSD-Kernel-Core] Dereference stoppcbs based on target kernel version (#222977)
As of `__FreeBSD_version 1400089` stoppcbs is a pointer to the pcbs
array. Dereference stoppcbs on sufficiently new kernels.
Obtained-from:
https://cgit.freebsd.org/src/commit/?id=0f2bb40bc7ddee7ba329d9b344623e2a186b4046
Commit: 4b08871f7ffe6ad818147145f8b6103e6c9b2c95
https://github.com/llvm/llvm-project/commit/4b08871f7ffe6ad818147145f8b6103e6c9b2c95
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
Log Message:
-----------
[SSAF][SourceEdit] Wire in 'clang-ssaf-src-edit-merge' and add multi-TU tests (#220372)
With 'clang-ssaf-src-edit-merge', we can test source edits over multiple
translation units: their Replacements are merged before apply. This
covers both clean merges and conflicts.
Commit: e476e76df9b17ace8d12f85616482718901d4854
https://github.com/llvm/llvm-project/commit/e476e76df9b17ace8d12f85616482718901d4854
Author: David Green <david.green at arm.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Make ImmInsnModel operands optional. NFC (#223280)
This helps make sure we do not use them incorrectly, and should allow
them to
be checked for values in the future.
Commit: e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
https://github.com/llvm/llvm-project/commit/e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
Log Message:
-----------
[VPlan] Add tests for narrowing users of a widened induction (NFC). (#223277)
Add additional narrowing tests for wide IV including pointer inductions
and FP inductions.
Commit: cc6d78e8eea21e0ddc5376b1700af00e33a77e17
https://github.com/llvm/llvm-project/commit/cc6d78e8eea21e0ddc5376b1700af00e33a77e17
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[VPlan] Fold shifts by zero. (#223276)
Add trivial folds of shifts by zero. This allows us to match IR SCEV
behavior (which looks through trivial shifts), w/o explicitly handling
those in getSCEVExprForVPValue.
Commit: 0c4e1a6b8941babd458e803041abc4d5186361e8
https://github.com/llvm/llvm-project/commit/0c4e1a6b8941babd458e803041abc4d5186361e8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Set the containing plan when creating blocks (NFC). (#223269)
Now that we funnel all VP block creation through VPlan helpers, make
sure the Plan field is set for each block. This means we can remove the
CFG walk to find a Plan's entry.
Also drop an assertion in VPSlotTracker::getOrCreateName: a block now
knows its plan as soon as it is created.
This has a very small positive compile-time impact.
Commit: 462535b1455c639bfb1875b71720d94586a5f650
https://github.com/llvm/llvm-project/commit/462535b1455c639bfb1875b71720d94586a5f650
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[InstCombine][NFC] Move bitcast from float tests into their own file (#223196)
Commit: c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
https://github.com/llvm/llvm-project/commit/c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
Log Message:
-----------
[lldb] Test undefined return addresses in signal frames (#223046)
Signal-frame CFI can explicitly mark its return-address register
undefined to represent a terminal synthetic context. This is useful for
contexts such as newly created FreeBSD kernel threads that do not have
an interrupted caller.
Verify that LLDB keeps the signal frame in the backtrace and terminates
the unwind without creating a caller.
Assisted-by: GPT
Commit: bce20f538caf18619a825c689883f652471091d3
https://github.com/llvm/llvm-project/commit/bce20f538caf18619a825c689883f652471091d3
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Add experimental Smidctrl, Ssidctrl, Smnip, and Ssnip support (#218108)
Add experimental MC support for Smidctrl, Ssidctrl, Smnip, and Ssnip
extensions.
This completes MC support for the ACLIC v0.20 extensions.
Commit: 63d2e62707e8ec6c070a3b258ea81f320920525c
https://github.com/llvm/llvm-project/commit/63d2e62707e8ec6c070a3b258ea81f320920525c
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Lex/PPMacroExpansion.cpp
Log Message:
-----------
[clang][Lex] Unique ModuleMacros with a UniquingSet (NFC) (#223270)
This patch migrates ModuleMacros in Preprocessor from llvm::FoldingSet
to llvm::UniquingSet.
ModuleMacro keys on a pair of Module * and const IdentifierInfo *.
Switching to UniquingSet allows us to look up macros with a typed key,
eliminating FoldingSetNodeID serialization at lookup sites and removing
ModuleMacro::Profile.
Assisted-by: Antigravity
Commit: 6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
https://github.com/llvm/llvm-project/commit/6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
A llvm/test/Transforms/InstCombine/uitofp.ll
Log Message:
-----------
[InstCombine] Fold uitofp of masked truncations (#222592)
Fold an unsigned integer-to-floating-point conversion of a masked
truncation by widening the mask and eliminating the truncation:
`uitofp((trunc X) & C)` → `uitofp(X & zext(C))`
Apply the fold when the intermediate instructions have one use and
widening the integer operation is desirable.
This reduces the instruction count on both AMDGPU and NVPTX.
AMDGPU example: https://godbolt.org/z/rTYhM61ce
NVPTX example: https://godbolt.org/z/fWhsrne19
Commit: 9e70d8f070ba046b8e09388fa84b3a65eb2073e3
https://github.com/llvm/llvm-project/commit/9e70d8f070ba046b8e09388fa84b3a65eb2073e3
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/blocks.cpp
Log Message:
-----------
[Clang][NFC] add additional test coverage for default argument parsing errors (#222556)
Fixes #115280
Commit: 291b60a5bc416c8dd81731954680ebd41f599ab5
https://github.com/llvm/llvm-project/commit/291b60a5bc416c8dd81731954680ebd41f599ab5
Author: wanglei <wanglei at loongson.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
Log Message:
-----------
[LoongArch][test] Test 1- and 2-byte subtraction relocations. NFC (#222825)
Add MC tests for 1- and 2-byte subtraction relocations enabled by
#211754.
Commit: dbac421efa19a5901f2511958040e18e8188b112
https://github.com/llvm/llvm-project/commit/dbac421efa19a5901f2511958040e18e8188b112
Author: lntue <lntue at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/utils/mathtools/wc_to_bin.py
Log Message:
-----------
[libc][math] Fix fast path with small inputs for double precision sin/cos. (#221012)
https://github.com/llvm/llvm-project/pull/201748 added a fast branch for
small inputs to double precision sin/cos,
but the Ziv error bounds were too tight.
Fixes in this PR:
- Updating the Ziv error bounds to accommodate rounding errors.
- Copy binary64 sin/cos hard-to-round cases from the CORE-MATH project.
- Add python tool to convert textual hard to round cases to binary
files, and add those binary files.
- Add hard-to-round tests for double precision sin/cos in the exhaustive
test folder.
Fixes https://github.com/llvm/llvm-project/issues/220934.
Assisted-by: Gemini is used to generate the worst-case text-to-binary
tool.
Commit: a92db5feb9eb78ae7bf37d969391d9f94f181afb
https://github.com/llvm/llvm-project/commit/a92db5feb9eb78ae7bf37d969391d9f94f181afb
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen] Declare <TargetName>RegClassByHwModeTables in MC header (#223292)
When a target uses RegClassByHwMode in CompressPat, the generated
functions reference <TargetName>RegClassByHwModeTables.
Declare it under GET_INSTRINFO_MC_HELPER_DECLS (<Target>MCTargetDesc.h)
so it is visible to MC-layer users such as RISCVBaseInfo.cpp.
Fixes: 700d1f029d00 ("[TableGen] Support RegClassByHwMode in
CompressPat")
Commit: 10b2437880e6d3365f973174f6bce8e07f54f549
https://github.com/llvm/llvm-project/commit/10b2437880e6d3365f973174f6bce8e07f54f549
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Build RTTICrossDylibTestLib with ORC_RT_COMPILE_FLAGS (#223144)
Without ORC_RT_COMPILE_FLAGS, the test library builds with C++ RTTI on
by default. This leads to link errors when the ORC runtime is built with
C++ RTTI turned off.
Commit: 72d03332c0cd0579ad09d00f9086c7cb6035fce0
https://github.com/llvm/llvm-project/commit/72d03332c0cd0579ad09d00f9086c7cb6035fce0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/tools/ogre/CMakeLists.txt
Log Message:
-----------
[orc-rt] Add ORC_RT_BEDROCK_LIBRARY_TYPE (STATIC/SHARED) (#223288)
Add CMake options to build bedrock as either a static or shared library.
Default is static.
This is CMake infrastructure only. Shared library builds aren't actually
useable yet: bedrock doesn't export its C++ API, and its C API is
insufficient to do anything interesting. Tools and test code are updated
to link against the -object libraries directly, since they use the
(unexported) C++ API.
Commit: 5fa83314adddbd13e4347ec8fc22e235d5710978
https://github.com/llvm/llvm-project/commit/5fa83314adddbd13e4347ec8fc22e235d5710978
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/test/Driver/sparc-as.c
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M llvm/lib/Target/Sparc/Sparc.td
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
Log Message:
-----------
[SPARC] Add LEON5 processor (#222912)
Same target exists in GCC.
Commit: f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
https://github.com/llvm/llvm-project/commit/f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve EHFrame registration symbols via lookupAndApply (#223304)
EHFrameRegistrationPlugin::Create resolved its register/deregister
alloc-action addresses with EPC.getBootstrapSymbols. For consistency,
switch to lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
https://github.com/llvm/llvm-project/commit/bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
Log Message:
-----------
[libc] Implement pthread_attr_[gs]etschedparam (#222991)
This patch implements pthread_attr_setschedparam and
pthread_attr_getschedparam.
Like the schedpolicy patch, this commit only operates on the
pthread_attr_t object and does not attempt to install scheduling
parameters when creating a new thread.
I also don't attempt to validate the priority value here. The valid
priority range depends on the scheduling policy (which may not even be
set yet or could change later), and we can let the kernel validate the
parameters when creating the thread or setting scheduler settings.
While in there:
- update the file headers to the modern llvm format
- use proxy headers instead of direct pthread.h inclusion
Assisted-by: Gemini
Commit: aeefb10b01fb7cf11a1917230f10b663d5ec109b
https://github.com/llvm/llvm-project/commit/aeefb10b01fb7cf11a1917230f10b663d5ec109b
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/IR/Metadata.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Simplify ValueAsMetadata::handleRAUW. NFC (#223301)
Metadata refers to a Value through its unique ValueAsMetadata wrapper.
When a Value is RAUW'd, handleRAUW reuses the old value's wrapper for
the new value if the new value has none yet; otherwise it moves the uses
to the new value's wrapper, with special cases for a local becoming a
constant, a constant becoming a local, and a value moving to another
function.
Always move the uses (or drop them in the last two cases) and delete the
old wrapper, so that a ValueAsMetadata wraps the same value for its
whole life.
Instruction counts for SLPVectorizer.cpp and X86ISelLowering.cpp at -O2
-g are unchanged (-0.04%, -0.01%).
Aided by Opus 5
Commit: 9a7c7f2b3a40c32e53dcaf2637087851d694cc60
https://github.com/llvm/llvm-project/commit/9a7c7f2b3a40c32e53dcaf2637087851d694cc60
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
Log Message:
-----------
[Clang][RISCV] Add packed widening add accumulate intrinsics (#221622)
Add Clang header intrinsics for the RISC-V P-extension packed widening
add accumulate operations:
- __riscv_pwadda_i16x4
- __riscv_pwadda_i32x2
- __riscv_pwaddau_u16x4
- __riscv_pwaddau_u32x2
The header wrappers use generic LLVM IR. RV32 selects the direct
`pwadda.*` / `pwaddau.*` instructions. RV64 lowers the generic IR to the
decomposition specified by the P-extension intrinsic spec, including
`zip16p + pli.h + pm2adda.h/pm2addau.h` for the halfword forms.
Commit: f8c52ad174682e05e222c1456a9f3ad177cf464b
https://github.com/llvm/llvm-project/commit/f8c52ad174682e05e222c1456a9f3ad177cf464b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
Log Message:
-----------
[TargetInstrInfo] Enable instruction size verification by default (#221687)
Enable verification for instruction sizes by default. When emitting
machine code, this checks that the reported instruction size is not
smaller than the actual instruction size. Not under-reporting
instruction sizes is critical for any target that does branch relaxation
(or similar) on MIR.
The default allows over-estimating the size. Targets can opt-in to
precise instruction sizes if they want.
Exclude two instructions on ARM, which report incorrect sizes, but
fixing those sizes breaks the constant islands pass for some reason.
Commit: a9253c774aae777f5c0135d063a3a044612ae48f
https://github.com/llvm/llvm-project/commit/a9253c774aae777f5c0135d063a3a044612ae48f
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/Allocator.h
M llvm/unittests/Support/AllocatorTest.cpp
Log Message:
-----------
[Allocator] Don't overestimate alignment for operator new (#223300)
On many platforms with alignof(max_align_t)=16, when sizeof(T) == 24,
The placement new overestimates the alignment to 16:
`std::min(llvm::bit_ceil(Size), alignof(std::max_align_t)) = min(32, 16) = 16`.
We can use a better estimate: `min(countr_zero(Size),
alignof(max_align_t))`, which is hand-optimized to the form in the code.
Commit: 93d89033cddd47fc512dbe14917fd62d302f4f1d
https://github.com/llvm/llvm-project/commit/93d89033cddd47fc512dbe14917fd62d302f4f1d
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
Log Message:
-----------
[GlobalOpt] Fix assertion failure with CallInst user (#221955)
By removing the unnecessary assertion, which can get
out of sync with GlobalStatus.
Fixes: #221589
Commit: b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
https://github.com/llvm/llvm-project/commit/b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
Log Message:
-----------
[RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 (#222829)
i64 is not a legal type on RV32, so f16 to i64 conversions used to be expanded to a __fixhfdi/__fixunshfdi libcall, which compiler-rt does not provide. f16 is the only FP type whose finite values always fit in an i32 after truncation towards zero, so custom expand them to an i32 conversion plus an extension instead; out of range values and NaN are poison, so the fcvt clamping is acceptable. With only Zfhmin/Zhinxmin the i32 conversion promotes f16 to f32, and both imply F/Zfinx so f32 is always legal. Other FP source types keep using the libcall.
Commit: bc985edd777ff8efab9f161444d4a9ff00c25574
https://github.com/llvm/llvm-project/commit/bc985edd777ff8efab9f161444d4a9ff00c25574
Author: Chris Copeland <chris at chrisnc.net>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
Log Message:
-----------
[CodeGen][test] use -float-abi=soft in 2009-03-29-SoftFloatVectorExtract.ll (#223122)
In #221434, using +soft-float with a hard-float ABI is now an error on
ARM.
This test does not specify a target triple, so it will fail when the
default triple is hard-float ARM. Explicitly specify -float-abi=soft
so the test will continue to use the host triple but force the
soft-float ABI
where applicable.
Commit: badec9b619f3f7d6090d5ae84a60adf416139a15
https://github.com/llvm/llvm-project/commit/badec9b619f3f7d6090d5ae84a60adf416139a15
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve unwind-info alloc-actions via lookupAndApply (#223312)
UnwindInfoRegistrationPlugin::Create resolved its register- /
deregister-section alloc-actions with EPC.getBootstrapSymbols. For
consistency, switch to lookupAndApply/recordAddr on the bootstrap
JITDylib instead.
Commit: 109f29a7c0a3910a768fa7dd490ac8f51708b858
https://github.com/llvm/llvm-project/commit/109f29a7c0a3910a768fa7dd490ac8f51708b858
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
Log Message:
-----------
[SPIR-V] Print group operation of uniform group instructions as enum (#222540)
Opcodes typed `$groupOp` as i32imm, so the printer emitted 0 instead of
"Reduce" and spirv-as rejected the output
Commit: 20b53106931742d2e5e64132f06994980fe94d7d
https://github.com/llvm/llvm-project/commit/20b53106931742d2e5e64132f06994980fe94d7d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Avoid use of ConstantExpr::getSizeOf() (#223323)
This will not be supported in ptradd representation. Directly
create a constant with the type size instead.
Commit: a872c86cf07ad71cc4e05a98c5169a27d600d16c
https://github.com/llvm/llvm-project/commit/a872c86cf07ad71cc4e05a98c5169a27d600d16c
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Parser/cxx-extra-semi.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for extra semicolons in parameter lists (#222572)
Fixes #112377
Commit: 61519bf9fa07fed0546c2985a6884b60ca71ca2b
https://github.com/llvm/llvm-project/commit/61519bf9fa07fed0546c2985a6884b60ca71ca2b
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/enum.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for parameter declaration errors (#222562)
Fixes #113465
Commit: ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
https://github.com/llvm/llvm-project/commit/ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
Log Message:
-----------
[CGP] Clear poison generating flags when freezing icmp of constants (#223326)
Followup to https://github.com/llvm/llvm-project/pull/222314. That
PR only dropped the flags for the case where a new freeze instruction
was created, but of course we also need to do this if both operands
are constant and the freeze is dropped entirely.
Commit: fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
https://github.com/llvm/llvm-project/commit/fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[lldb-dap] Fix logpoint to breakpoint conversion (#222906)
When user sets logpoint and after that removes `logMessage`, which
implicitly converts it to usual breakpoint, breakpoint still has
`BreakpointHitCallback`, which leads to missed stops.
Commit: 0f89e7a6027b9fc93032aa4d154028045ed9018f
https://github.com/llvm/llvm-project/commit/0f89e7a6027b9fc93032aa4d154028045ed9018f
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
Log Message:
-----------
[Flang][OpenMP] Show warning for -fdoconcurrent-to-openmp in SIMD only mode (#220943)
The OpenMP feature is considered enabled if either `-fopenmp` or
`-fopenmp-simd` have been passed. However, full OpenMP support is
required in order for the `-fdoconcurrent-to-openmp` option to take
effect.
A warning message that wasn't shown when SIMD-only OpenMP support was
enabled is fixed.
Commit: 860d945db8787845349096521157eabf09be81cb
https://github.com/llvm/llvm-project/commit/860d945db8787845349096521157eabf09be81cb
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223328)
Commit: 6e071ab17caa0058a83cdd1580026259fdaecb4f
https://github.com/llvm/llvm-project/commit/6e071ab17caa0058a83cdd1580026259fdaecb4f
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
Log Message:
-----------
[RISCV] Rewrite ADD to SUB to reuse a materialized negated constant (#221027)
When an ADD needs a large constant whose negation is already
present in the DAG, rewrite (add X, C) into (sub X, -C) so both
share one materialization of -C instead of building it twice.
selectNegImm already does a related rewrite, but only when -C is
strictly cheaper than C and during instruction selection, where the
sibling constant may already have been selected into instructions.
Do it in PreprocessISelDAG instead, before selection, while both are
still ConstantSDNodes that getConstant can unique together. The
rewrite only fires when -C is no more expensive than C and a node
holding -C already exists, so it never adds a materialization.
Fixes https://github.com/llvm/llvm-project/issues/220555
Assisted-by: TRAE CLI (Opus 4.8)
Commit: 6d4ad3383e9b235c0f07a82be141bb57278650af
https://github.com/llvm/llvm-project/commit/6d4ad3383e9b235c0f07a82be141bb57278650af
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
Log Message:
-----------
[AMDGPU] Model waterfall loop EXEC update as a terminator (#219519)
Defining a register normally disqualifies an instruction from being a
terminator, so mark it unspillable instead
Skip this at -O0, since RegAllocFast ignores that and spills right after
the def
Commit: 6b5912a441c2236859a7cfe1e5ce3e02a547b588
https://github.com/llvm/llvm-project/commit/6b5912a441c2236859a7cfe1e5ce3e02a547b588
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
Revert "[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC)" (#223341)
Reverts llvm/llvm-project#223328 (looking into buildbot error, e.g.
https://github.com/llvm/llvm-project/pull/223328#issuecomment-5661919431)
Commit: 1042f3cd8299003876babb567d78540d30c019aa
https://github.com/llvm/llvm-project/commit/1042f3cd8299003876babb567d78540d30c019aa
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[mlir][ComplexToStandard] Use negf/subf instead of multiplying by -1 (#222877)
Commit: e8d2def7e7ed18f22a493b72435468225c1047ba
https://github.com/llvm/llvm-project/commit/e8d2def7e7ed18f22a493b72435468225c1047ba
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
Log Message:
-----------
[libc++] Provide aligned allocation function iff the compiler claims support (#219199)
There isn't much of a point to providing declarations for aligned
allocation functions but not allowing the compiler to use them. So
either aligned allocations should be allowed to be used via
`-faligned-allocation` or not provided at all.
Commit: 1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
https://github.com/llvm/llvm-project/commit/1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/docs/OpenMP-declare-target.md
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
Log Message:
-----------
[MLIR][OpenMP] DeclareTargetInterface and DeclareTargetAttr cleanup (#217295)
The changes introduced by this patch are intended to avoid triggering
multiple by name lookups to the "omp.declare_target" attribute every
time any data from the `DeclareTargetInterface` is queried, remove the
need for keeping multiple default values for the same data, clean up the
assembly format and generally improve the usage of the interface.
List of changes:
- `DeclareTargetInterface` only provides `setDeclareTarget` and
`getDeclareTarget` methods to handle the "omp.declare_target" attribute,
maintaining a single canonical way of accessing it.
- `DeclareTargetAttr` provides direct access to the capture clause and
device type enums, rather than wrapping them into an `Attribute`. These
are now mandatory as well. Both changes together make accessing them
more straightforward and simplify the attribute representation.
Commit: 37fe7024f2944f71d58b8608d209bda3254fa43a
https://github.com/llvm/llvm-project/commit/37fe7024f2944f71d58b8608d209bda3254fa43a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/read_image.ll
Log Message:
-----------
[SPIR-V] Add missing read_imageh builtin mapping (#222549)
Commit: c4c4bbaf14303d3e5399487c16ec6a0ff4754386
https://github.com/llvm/llvm-project/commit/c4c4bbaf14303d3e5399487c16ec6a0ff4754386
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__charconv/to_chars_integral.h
Log Message:
-----------
[libc++][NFC] Remove some unused functions from to_chars_integral.h (#223130)
Commit: d873afedebd0726700ba7f42a5d6e54dba288557
https://github.com/llvm/llvm-project/commit/d873afedebd0726700ba7f42a5d6e54dba288557
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
Log Message:
-----------
[libc++] Optimize string copy construction (#222021)
We know that the string size provided to `__init_copy_ctor_external` is
less than or equal to `max_size()`, so we don't need to do that check
again. Removing that check allows the compiler to ShrinkWrap the small
size path and also removes some unnecessary work in the allocating path.
Commit: 1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
https://github.com/llvm/llvm-project/commit/1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
Log Message:
-----------
[libc++] Move _LIBCPP_HAS_COND_CLOCKWAIT into condition_variable.h (#222904)
`_LIBCPP_HAS_COND_CLOCKWAIT` is only used inside
`<__condition_variable/condition_variable.h>`, so we might as well move
it there.
Commit: 59f4a867528eeb8cd8823afb0ee4e5c4d2843741
https://github.com/llvm/llvm-project/commit/59f4a867528eeb8cd8823afb0ee4e5c4d2843741
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
Log Message:
-----------
[X86] Fix `"Cannot select"` for `bf16` vector selects on a scalar condition under `AVX10.2` (#222854)
Fixes #222673
A `select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b` failed instruction
selection with `+avx10.2-512` on a `v8bf16 X86ISD::CMOV`. Selects on a
scalar condition are lowered to the `CMOV_VR*` pseudos and expanded to a
branch, but those pseudos only have patterns for integer and f16
vectors. Before #101603 bf16 vectors were treated as "soft" everywhere,
so `LowerSELECT` bitcast them to `v8i16` first and never produced a bf16
CMOV. That PR made bf16 non-soft under AVX10.2 to enable native
arithmetic, which silently removed the only bf16-aware path in
`LowerSELECT` without adding a replacement. `v16bf16` and `v32bf16` hit
the same thing.
`LowerSELECT` now takes the integer-bitcast path for every bf16 vector,
using the existing `isBF16orSoftF16` helper, so the select is lowered
exactly as it is on every other bf16 target and as `v8f16` is on FP16
targets. Scalar `bf16` is soft-promoted to `f32` before lowering, so it
is unaffected. Added `pseudo_cmov_lower-bf16.ll` alongside the f16
sibling, covering the reproducer plus `v8/v16/v32bf16` on both
`+avx512bf16,+avx512vl` and `+avx10.2-512`.
Commit: 1b97c0daeb67ef7895034a1702ccc04562283ecc
https://github.com/llvm/llvm-project/commit/1b97c0daeb67ef7895034a1702ccc04562283ecc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
Log Message:
-----------
[ORC] Resolve JITLoaderGDB alloc actions via lookupAndApply (#223325)
ELFDebugObjectPlugin resolved its RegisterJITLoaderGDB alloc-action
address with EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: eb6d5dd90eb596f8b82632d03d2ad8517df2d764
https://github.com/llvm/llvm-project/commit/eb6d5dd90eb596f8b82632d03d2ad8517df2d764
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223346)
Commit: f477555c212d2eddd65f5a791b19efe075e2c708
https://github.com/llvm/llvm-project/commit/f477555c212d2eddd65f5a791b19efe075e2c708
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Memory.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Target/Memory.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Memory cache: no overlap and read across cache entries (#222688)
The memory cache keeps two collections of cached bytes, L1 and L2, which
are named confusingly. L2 holds cache lines at aligned addresses, but
each line size is less than or equal to the fixed line size. L1 holds
pieces from arbitrary addresses with arbitrary lengths. This caused two
problems:
1. A lookup had to find every byte it wanted inside a *single*
entry. A range that spanned two adjacent entries missed even when the
two collections together already held every byte of it. The lookup
rejected such a read rather than take part of it from each entry.
2. The pieces could also overlap each other, which made the lookup
incomplete as well as ambiguous. It examined only the piece starting at
or below the address, so a short piece hid a longer one that covered the
whole read. The read missed with the bytes resident.
This change fixes these problems by introducing these properties to the
cache:
- At most one collection holds any given address.
- The line collection holds only whole, aligned lines (`LineCache`).
- The piece collection holds only fragments smaller than a line, and
they never overlap each other (`ChunkCache`).
- A read takes what it needs from consecutive entries in turn until a
miss (`ReadFromCaches`).
- `AddCacheData` (renamed from `AddL1CacheData`) splits incoming bytes
at line boundaries and drops bytes already held, so callers no longer
pick the cache tier.
Disjoint entries make the cache simple to reason about:
- A read no longer depends on which copy of an address is found first,
because there is only one.
- Probing one candidate is now complete. Since entries cannot
overlap, the entry starting at or below an address is the only one
that can hold it. No byte is stored twice.
- Invalidating an address touches one entry, with no second copy
elsewhere to find and drop.
- Callers of the cache need no knowledge of cache internals.
`ReadRanges` also uses `ReadFromCaches`. Previously, each requested
range had to fit entirely within a single cache entry. Ranges can now
be served across multiple entries and line boundaries. For example,
`Process::ReadCStringsFromMemory` reads strings in 256-byte windows.
Because strings start at arbitrary offsets, these windows frequently
span
two adjacent cache lines. Under the old lookup, such a window missed in
`ReadRanges` even when both lines were resident. It now hits from cache
across the line boundary.
`Flush` now drops all cached entries that intersect the range instead of
erasing only the entry matching the start address. It uses saturating
addition to prevent address wraparound. Its runtime is bounded by the
number of cached entries rather than the range size.
`GrowReadRange` isolates the read-ahead policy from `Read`. It aligns
the read address down to the line base so fetches land in `LineCache` as
whole lines. It caps read-ahead to two lines, skips the last line if
already resident, and clips the read at invalid ranges.
Assited-by: claude
Commit: 9271a73e189508743b4b2ad4393f12d5a8132fa9
https://github.com/llvm/llvm-project/commit/9271a73e189508743b4b2ad4393f12d5a8132fa9
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
Log Message:
-----------
[AMDGPU] Mark `SI_WATERFALL_LOOP` as divergent in `hasDivergentBranch` (#218969)
When a vector instruction takes an SGPR source operand, sinking it out
of a loop with divergent exit would cause the vector instruction to only
get the value from the last iteration in the SGPR. However, in a
divergent loop the value of the SGPR operand may vary across iterations,
so the instruction cannot be sink out of the loop as only using the last
value is incorrect. Before this change `SI_LOOP` was marked as divergent
but `SI_WATERFALL_LOOP` was not, allowing such incorrect sinking for
waterfall loops.
Assisted-by: Claude Code
Commit: 611db63efe0456cca4745930977fcdfe64cc25a9
https://github.com/llvm/llvm-project/commit/611db63efe0456cca4745930977fcdfe64cc25a9
Author: MarkVeerasingam <122292447+MarkVeerasingam at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
Log Message:
-----------
[dfsan] Fix big-endian origin mask (#223247)
Fix the mask used when loading wide shadows on big-endian targets.
The previous expression used a 32-bit integer for the shift, producing
an incorrect zero mask for 64-bit wide shadows. Changed the expression
to use 1ULL so that a 64-bit mask is constructed correctly. The
resulting mask keeps the upper 32 bits and clears the lower 32 bits.
Previously, the big-endian path generated:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, 0
```
With this change, it generates:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, -4294967296
```
Added a SystemZ big-endian regression test.
cc: @uweigand @anoopkg6
Commit: c46d8f243727b467d8803c4b2430534b348daed1
https://github.com/llvm/llvm-project/commit/c46d8f243727b467d8803c4b2430534b348daed1
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
Log Message:
-----------
[SLP]Booleanize logical and/or nodes in the wide leaf type
i1 and/or tree nodes with booleanized wide leaves (one-use truncs of
wide values, zero-tests of values from [0, 1]) are registered in MinBWs
and emitted in the wide type; bit 0 of the result is the final value.
Reviewers: bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/223250
Commit: 27c38b80934067471d7aa7477f894bcb8461a4f3
https://github.com/llvm/llvm-project/commit/27c38b80934067471d7aa7477f894bcb8461a4f3
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16 (#221960)
Use the high 16 bits of a VGPR directly instead of shifting.
Before:
```
v_lshrrev_b32_e32 v1, 16, v0
v_add_f16_e32 v0.l, v0.l, v1.l
```
After:
```
v_add_f16_e32 v0.l, v0.l, v0.h
```
Example: https://godbolt.org/z/c7bE46hzb
Commit: e9d50d35104db2a3ac87e1280e043a0e7f4f7e4d
https://github.com/llvm/llvm-project/commit/e9d50d35104db2a3ac87e1280e043a0e7f4f7e4d
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/Analysis/explicit-lambda-capture.cpp
Log Message:
-----------
[analyzer] Resolve lambda captures for explicit object parameters (#219726)
Currently explicit object parameters are not modeled in the
`VisitCommonDeclRefExpr` function in `ExprEngine`. Because of this when
a lambda has an explicit object parameter and a possible division by
zero the `core.DivideZero` checker does not emit warning. This PR solves
that issue by deciding if the lambda has an explicit object parameter
and then records the binding (if the parameter has the reference type)
between the parameter and the argument's expression otherwise it returns
the captured field's lvalue.
This PR fixes #218708
Commit: eaab447acac971ed7fbcb51c11343db899ad5ffe
https://github.com/llvm/llvm-project/commit/eaab447acac971ed7fbcb51c11343db899ad5ffe
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/Host/common/XML.cpp
Log Message:
-----------
[lldb] Parse XML files without the deprecated SAX1 API (#222974)
SAX1 is deprecated, switch to SAX2 instead.
Commit: 9fda68e41dcb8d19751bc042508eeee8bd9c596a
https://github.com/llvm/llvm-project/commit/9fda68e41dcb8d19751bc042508eeee8bd9c596a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[Clang] Document the interaction of malloc_span and alloc_size (#216967)
The `malloc_span` attribute is intended to be used for
`allocate_at_least`-like functions. Part of that interface is a
guarantee that the number of bytes returned are actually
dereferenceable. Document that, so that we can optimize on it in the
future.
Commit: e9f9afc6042da7cbbf1252702e86783f07cb46f4
https://github.com/llvm/llvm-project/commit/e9f9afc6042da7cbbf1252702e86783f07cb46f4
Author: John Brawn <john.brawn at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
A llvm/test/Transforms/SROA/large-alloca.ll
Log Message:
-----------
[SROA] Use SparseBitVector for splittable offsets (#222306)
Doing this means we consume memory proportional to the number of
offsets, not the size of the alloca as before. Inverting the logic so
that rather than initially marking all offsets as splittable then
removing those that aren't, we instead initially have all offsets
unsplittable and only add those that are splittable, means we should
take time proportional to the number of slices, not to the combined size
of slices.
This means we can remove the limit on alloca size, and this approach
should also be faster.
Commit: 0eaa2e690c85224b0afb700e2e33bbf242e55192
https://github.com/llvm/llvm-project/commit/0eaa2e690c85224b0afb700e2e33bbf242e55192
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llc/lib/BUILD.gn
Log Message:
-----------
[gn] port 474b7358a90e4f2 (llvm/tools/llc/lib) (#223370)
Commit: 77a26fadb88bdc523ef82bcaec8c7e6217701a57
https://github.com/llvm/llvm-project/commit/77a26fadb88bdc523ef82bcaec8c7e6217701a57
Author: Hung-Kuan Tseng <tseng.tim096 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
Log Message:
-----------
[mlir][memref] Keep memref.load attributes when eliding reinterpret_cast (#221314)
`RewriteLoadFromReinterpretCast` rebuilds the load on the source of the
`memref.reinterpret_cast` with the indices remapped to the non-unit
dimensions, but the rebuilt load carries none of `nontemporal`,
`alignment` or `invariant`:
```mlir
%rc = memref.reinterpret_cast %src to offset: [0], sizes: [1, 1, 8], strides: [8, 8, 1] : memref<1x8xf32> to memref<1x1x8xf32>
%0 = memref.load %rc[%c0, %c0, %i] alignment(16) nontemporal(true) invariant(true) : memref<1x1x8xf32>
// -memref-elide-reinterpret-cast today
%0 = memref.load %src[%c0, %i] : memref<1x8xf32>
```
The rewrite only changes how the same element is addressed, so the three
attributes describe the same access. This forwards them. Same shape of
fix as #221312 for `gpu-decompose-memrefs`.
Commit: 26b9d50cbdff788b70a743da97be30c278c5d79b
https://github.com/llvm/llvm-project/commit/26b9d50cbdff788b70a743da97be30c278c5d79b
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Select the GFX80 encoding family from the subtarget. NFCI. (#219190)
pseudoToMCOpcode() used the D16Buf TSFlag to switch individual instructions to
the GFX80 encoding family on subtargets with UnpackedD16VMem. Select GFX80 for
the whole subtarget instead, and fall back on VI when a pseudo has no GFX80
real. That is what the flag was encoding anyway: only buffer instructions with
unpacked D16 data have a GFX80 encoding.
D16Buf is now unused, so remove it and free up TSFlags bit 50.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 7b579a91dc6b7df584f021e283004043a402571c
https://github.com/llvm/llvm-project/commit/7b579a91dc6b7df584f021e283004043a402571c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port 240670d0d5dc (#223371)
Commit: 1adf54c67fff78a552e5554f0f8fd783511f8334
https://github.com/llvm/llvm-project/commit/1adf54c67fff78a552e5554f0f8fd783511f8334
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port d873afedebd0 (#223372)
Commit: dbe4e7e799bc5e5707334e31dfbc19542388c2ac
https://github.com/llvm/llvm-project/commit/dbe4e7e799bc5e5707334e31dfbc19542388c2ac
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll
Log Message:
-----------
[X86] zero-call-used-regs-simd.ll - add baseline test coverage from #212147 (#223339)
Commit: c013403e8eace0714ded0202be1a220c358233d8
https://github.com/llvm/llvm-project/commit/c013403e8eace0714ded0202be1a220c358233d8
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/CodeGen/AArch64/sve/dup.c
Log Message:
-----------
[clang][cir] Updates SVE tests for dup intrinsics (#222681)
Updates tests for dup intrinsics to match the tests used for classical
code-gen in
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c.
This is in preparation for merging the two files.
Commit: 900b3d6aae5735ba040951d0029161c42da52417
https://github.com/llvm/llvm-project/commit/900b3d6aae5735ba040951d0029161c42da52417
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/C/C23/n2508.c
M clang/test/C/C2y/n3259.c
M clang/test/C/C2y/n3260.c
M clang/test/C/C2y/n3273.c
M clang/test/C/C2y/n3298.c
M clang/test/C/C2y/n3353.c
M clang/test/C/C2y/n3409.c
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/Lexer/cxx2c-raw-strings.cpp
M clang/test/Lexer/hexfloat.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Parser/cxx2c-delete-with-message.cpp
M clang/test/Sema/c2x-attr.c
M clang/test/Sema/fixed-enum.c
M clang/test/Sema/for.c
M clang/test/Sema/pre-c2x-restrict-qualifier.c
M clang/test/SemaCXX/cxx98-compat-pedantic.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/reinterpret-fn-obj-pedantic.cpp
Log Message:
-----------
[Clang] Put compat diagnostics in the pedantic group iff ext_warn==false (#220670)
The `compat-pedantic` groups are supposed to be used if a given
extension is only diagnosed in `-Wpedantic`. Update the compat
diagnostics to reflect this and move various diagnostics that already
adhere to this pattern to compat diagnostics.
Commit: bc5c36113551b13e41606573da58334ea17db1ab
https://github.com/llvm/llvm-project/commit/bc5c36113551b13e41606573da58334ea17db1ab
Author: Bastian Hagedorn <bhagedorn at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/ex2_invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
Log Message:
-----------
[mlir][NVVM] Add packed EX2 operations (#220501)
Add NVVM dialect operations for the public packed EX2 PTX instructions:
* `nvvm.ex2.f16x2` lowers to `ex2.approx.f16x2`
* `nvvm.ex2.bf16x2` lowers to `ex2.approx.ftz.bf16x2`
The existing scalar `nvvm.ex2` operation is unchanged. Includes LLVM IR
translation tests for both overloads.
Commit: 7421fba54dea2d03ea7b756cc4f0ba248c4e30b3
https://github.com/llvm/llvm-project/commit/7421fba54dea2d03ea7b756cc4f0ba248c4e30b3
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/lib/Core/Relocation.cpp
A bolt/test/RISCV/relr.s
Log Message:
-----------
[BOLT][RISCV] Support reading RV64 RELR relocations (#222265)
Clang linked with packed relative dynamic relocations aborts when the
RELR reader requests the target relative relocation type. Return
`R_RISCV_RELATIVE` for RV64, preserving the RV32 restriction and other
targets.
Assisted by GPT-6.
Commit: fe72b9678b037eaa71627a503dcc17288f9c3811
https://github.com/llvm/llvm-project/commit/fe72b9678b037eaa71627a503dcc17288f9c3811
Author: Yoni Katzuv <yoni.katzuv at quantum-machines.co>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Analysis/DataFlowFramework.h
M mlir/lib/Analysis/DataFlowFramework.cpp
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
M mlir/test/Analysis/test-foo-analysis.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
Log Message:
-----------
[mlir][dataflow] Deduplicate data-flow solver worklist items (#221983)
The solver enqueues a work item every time a state it depends on
changes, so the same item can appear in the worklist many times.
A duplicate work item is re-processed even though its inputs have not
changed since the previous processing. For example, a dense analysis can
visit a join point with N predecessors up to N times in a row.
To deduplicate the worklist, pending items are tracked using a
`DenseSet`, and an item that is already pending is not pushed again.
Items are removed from the set when dequeued, before being visited, so
an analysis can still re-enqueue the point it is currently visiting.
Since analyses already have to be monotone to reach a fixed point, this
change does not affect analysis results, only the number of visits until
convergence. The test `FooState` used XOR for the join operation, which
is not monotone; the join operation was switched to OR and dependent
tests were updated.
A test that counts how many times a join block with several predecessors
is visited was added to check the deduplication.
Commit: b18c59ead34b97b087146cce7513a060d9ea1b85
https://github.com/llvm/llvm-project/commit/b18c59ead34b97b087146cce7513a060d9ea1b85
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Improve array index and offset add/sub bounds checks wrt. opaque pointers (#223353)
We were previously causing an assertion since the index had more than 64
bits.
Commit: 013599011a6cc2f5a9d4cbeefc24ee44f3023317
https://github.com/llvm/llvm-project/commit/013599011a6cc2f5a9d4cbeefc24ee44f3023317
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
Log Message:
-----------
[CIR][X86] Emit cir.clz/cir.ctz for lzcnt/tzcnt builtins (#222669)
These x86 builtins were lowered through cir.call_llvm_intrinsic even
though dedicated CIR bit-count ops already exist.
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: f196f6a12bf431a28f76d873e4bdeb3dceac679c
https://github.com/llvm/llvm-project/commit/f196f6a12bf431a28f76d873e4bdeb3dceac679c
Author: Matteo Di Iorio <104271382+splicer3 at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
Log Message:
-----------
[libc][Bazel] Add missing F16 math targets (#222937)
Addresses #221799 by adding all existing F16 tests that were missing
Bazel targets.
Validated by running all 184 F16 tests with bazel test.
Commit: b8c7806bd5e3a40ce3fabd8743d73d77e7a417ab
https://github.com/llvm/llvm-project/commit/b8c7806bd5e3a40ce3fabd8743d73d77e7a417ab
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
A flang/test/Lower/OpenMP/target-data-use-device-addr-descriptor.f90
Log Message:
-----------
[Flang][OpenMP] Fix use_device_addr descriptor types (#222961)
Fix invalid FIR for assumed-shape arrays in use_device_addr by using
matching descriptor-reference types and loading the descriptor inside
the region. Added tests.
Co-authored-by: Codex <codex at openai.com>
Commit: 26462ac6c2b0a5932a4354957e6e0ba8f4824383
https://github.com/llvm/llvm-project/commit/26462ac6c2b0a5932a4354957e6e0ba8f4824383
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/unittests/Core/BinaryContext.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
M bolt/unittests/Profile/PerfScripts.cpp
Log Message:
-----------
[BOLT][RISCV] Add basic RISC-V initialization support for unit tests (#222883)
This change addresses the uninstantiated test suite failures in
RISC-V-only builds discussed in #217604. That PR proposed a temporary
workaround using GTEST_ALLOW_UNINSTANTIATED_PARAMETERIZED_TEST.
Add the basic setup needed to instantiate and initialize the existing
test suites for riscv64, including the correct ELF machine type and
subtarget features, and remove the temporary allowances.
Commit: 67397010eb5541f08fcdbb8be86b8b799ca88142
https://github.com/llvm/llvm-project/commit/67397010eb5541f08fcdbb8be86b8b799ca88142
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
Log Message:
-----------
[ORC] Use lookupAndApply for EPCGenericRTDyldMemoryManager (#223377)
EPCGenericRTDyldMemoryManager::CreateWithDefaultBootstrapSymbols
resolved its memory-manager and EH-frame symbol addresses with
EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: 9008f496e3dd414cb25aedd47168bc83bf52f470
https://github.com/llvm/llvm-project/commit/9008f496e3dd414cb25aedd47168bc83bf52f470
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
Log Message:
-----------
AMDGPU: Use subarch triples in new tests added since all were converted (#223385)
Commit: 004d5960e8e187b1e2b4a55e6221399aa076c258
https://github.com/llvm/llvm-project/commit/004d5960e8e187b1e2b4a55e6221399aa076c258
Author: Zihao Wang <rekind133 at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-bf16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-f16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-smla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
A llvm/test/Transforms/LoopVectorize/X86/CostModel/partial-reduce-dot-product.ll
Log Message:
-----------
[X86][CodeGen] Support partial-reduce dot products (#205373)
Part of #187779
Lower the llvm.vector.partial.reduce dot product shapes onto the X86 dot
product instructions:
i8 x i8 -> i32: vpdpbusd (AVX512-VNNI, AVX-VNNI)
vpdpbssd / vpdpbuud (AVX-VNNI-INT8, AVX10.2)
i16 x i16 -> i32: vpdpwssd (AVX512-VNNI, AVX-VNNI)
vpdpwsud / vpdpwuud (AVX-VNNI-INT16, AVX10.2)
bf16 x bf16 -> f32: vdpbf16ps (AVX512-BF16)
f16 x f16 -> f32: vdpphps (AVX10.2)
The 128/256-bit shapes, and the 512-bit shapes on targets using 512-bit
registers, are registered as Custom. 512-bit shapes for which only the
VEX
encoding exists are split into two 256-bit dot products, and the
128/256-bit
shapes are widened to 512 bits on targets without VLX.
Teach X86TTIImpl::getPartialReductionCost about these shapes, costing
one
dot product per legal accumulator vector and otherwise falling back to
the
generic expansion cost, so that LoopVectorize can form partial
reductions
for them.
The DAG combiner forms partial reductions with narrower-than-legal types
when the widened shape is supported, so also widen the integer
PARTIAL_REDUCE_*MLA results the same way as PARTIAL_REDUCE_FMLA (expand,
then widen).
Commit: a55e86582aeac1d4af64fa315ed49764c3981fad
https://github.com/llvm/llvm-project/commit/a55e86582aeac1d4af64fa315ed49764c3981fad
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN permlane builtins (#223161)
Adds codegen for the following AMDGCN permlane builtins:
- __builtin_amdgcn_permlane_bcast
- __builtin_amdgcn_permlane_up
- __builtin_amdgcn_permlane_down
- __builtin_amdgcn_permlane_xor
These are lowered to the corresponding `llvm.amdgcn.permlane.*`
intrinsics.
Assisted by: Claude Opus 5
Commit: 1af17ef01973f915ccbd168c01da1718097fd7f8
https://github.com/llvm/llvm-project/commit/1af17ef01973f915ccbd168c01da1718097fd7f8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.h
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
A llvm/unittests/ExecutionEngine/Orc/SimpleRemoteEPCUtilsTest.cpp
Log Message:
-----------
[ORC] Carry out-of-band errors in SimpleRemoteEPC results (#223378)
ORC Wrapper functions may produce out-of-band error results (e.g. due to
serialization errors), but SimpleRemoteEPC / SimpleRemoteEPCServer never
handled these cases (they incorrectly asserted that they never
appeared).
Update the SimpleRemote protocol to use the TagAddr field (previously
unused for result messages) to encode Result message kinds: either a
Value, or an OutOfBandError. This allows out-of-band errors to flow
across the wire and be passed as results to their callers.
encodeResultMessage and decodeResultMessage implement the format /
handling: out-of-band errors (or failures to deserialize out-of-band
errors) are now passed to handlers as out-of-band error results. An
invalid Result message kind in the TagAddr field results in an
llvm::Error, ending the session.
SimpleRemoteEPCUtilsTest covers both kinds' round-trips, an unrecognized
kind, and a malformed out-of-band payload.
Commit: ea4b78c309418a395d3a36e3319d65c4cfd9f2b4
https://github.com/llvm/llvm-project/commit/ea4b78c309418a395d3a36e3319d65c4cfd9f2b4
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
Log Message:
-----------
[analyzer] Chain checkers in runCheckersForEndFunction (#220970)
The function `runCheckersForEndFunction` had an unusual behavior that it
invoked the callbacks in parallel (introducing a new execution path for
each checker callback that produced a transition), unlike all other
analogous functions, which "chained" the checkers, executing them after
each other.
This behavior was introduced before 2011, when this callback was called
`check::EndPath`, to ensure that the `EndPath` callbacks are _final_ and
nodes created by them end up at the end of the execution path. When
interprocedural analysis (inlining functions) was introduced in 2013,
the callback was renamed to `EndFunction` (to reflect that it also
activates at the end of inlined functions), but the unusual behavior was
preserved.
There were 8 "real" checkers with `check::EndFunction` callbacks, but
most of them only created error nodes or did "nice to have" cleanup, so
the irregular behavior of this callback did not cause visible trouble.
However, none of the checkers actually _relies_ on the parallel
execution of the callbacks and the unusual transition pattern seriously
violates the established patterns of the analyzer; so this commit
rewrites `runCheckersForEndFunction` to follow the standard logic.
This may slightly perturb the analysis results (because it changes the
"shape" of the exploded graph), but -- based on my review of the
upstream EndFunction checkers -- should not cause any directed
functional changes.
For more background details see also the github review comments at
https://github.com/llvm/llvm-project/pull/217319#discussion_r3812950071
Commit: d57b857099bddf47c83317e64195d795015cabbd
https://github.com/llvm/llvm-project/commit/d57b857099bddf47c83317e64195d795015cabbd
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] Deduplicate compare expressions creation (NFC) (#223389)
Minor opportunity to create GVN expressions for cmp instructions via
existing dedicated `createCmpExpr` handler.
Commit: 8ab8773287c30cedd6e4cd60d044c73243f3e64f
https://github.com/llvm/llvm-project/commit/8ab8773287c30cedd6e4cd60d044c73243f3e64f
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
Log Message:
-----------
[llvm-jitlink] Use lookupAndApply for SharedMemoryMapper syms (#223379)
createSharedMemoryManager resolved the SharedMemoryMapper instance and
wrapper addresses with EPC.getBootstrapSymbols. For consistency, switch
to lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: af6169a51a30d46ff5daaca3f7d4e7cf41a17ce4
https://github.com/llvm/llvm-project/commit/af6169a51a30d46ff5daaca3f7d4e7cf41a17ce4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Interpreter/IncrementalExecutor.cpp
Log Message:
-----------
[clang-repl] Resolve mapper symbols via lookupAndApply (#223383)
IncrementalExecutor's createSharedMemoryManager resolved the
SharedMemoryMapper instance and wrapper addresses with
EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: 4df93e3b7b1ece75ec6b93971fc1d86fb093a72d
https://github.com/llvm/llvm-project/commit/4df93e3b7b1ece75ec6b93971fc1d86fb093a72d
Author: robertvirany <robertvirany at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
A llvm/test/CodeGen/NVPTX/clmad.ll
Log Message:
-----------
[NVPTX] Add clmad instruction selection (#216412)
Add instruction selection for the PTX 9.3 `clmad.{lo,hi}.u64`
instructions on SM80 and newer targets.
Select `clmad` for `i64` carryless multiply-add expressions represented
as an XOR of `ISD::CLMUL` or `ISD::CLMULH` with an accumulator.
Standalone carryless multiplies are selected as `clmad` with an
immediate zero-accumulator.
The first commit precommits tests showing the existing SelectionDAG
expansion.
Commit: 41a620da5a34d3e6256dc25e0c7c51c4afa8576d
https://github.com/llvm/llvm-project/commit/41a620da5a34d3e6256dc25e0c7c51c4afa8576d
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/Target/Memory.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Fix 32-bit narrowing conversions in the memory cache (#223402)
#222688 broke the 32-bit Arm bots. `lldb-arm-ubuntu` fails to
build `Memory.cpp`:
```
lldb/source/Target/Memory.cpp:187:49: error: non-constant-expression cannot be narrowed from type 'lldb::offset_t' (aka 'unsigned long long') to 'size_t' (aka 'unsigned int') in initializer list [-Wc++11-narrowing]
187 | InsertData(addr, {data_buffer_sp->GetBytes(), data_buffer_sp->GetByteSize()});
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
`DataBuffer::GetByteSize` returns `lldb::offset_t`, which is always 64
bits wide, while the `llvm::ArrayRef` constructor takes a `size_t`.
Where
`size_t` is 32 bits the conversion narrows, and a braced initializer
list
rejects a narrowing conversion that is not a constant expression. The
same code compiles on a 64-bit host because there `size_t` is just as
wide
as `offset_t` and nothing narrows.
`DataBuffer::GetData` already returns the whole buffer as an
`llvm::ArrayRef<uint8_t>`, so use it rather than build the same
`ArrayRef`
from a pointer and a length.
`MemoryTest.cpp` has eight more of the same error, which the bot never
reported because the build stopped at the first one. They share a single
cause: `line` holds the cache line size, but it was declared `addr_t`
and
the `Chunk` field it initializes is a `size_t`. Give it the type
`MemoryCache::GetMemoryCacheLineSize` returns, `uint32_t`, which is also
the right domain for a size rather than an address.
Assisted-by: claude
Commit: 6fd0ee2150ab3297ae89cbc64e98f588886906c9
https://github.com/llvm/llvm-project/commit/6fd0ee2150ab3297ae89cbc64e98f588886906c9
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
Log Message:
-----------
[SCEV] Return a SCEVUse from getAddExpr and propagate use flags. (#220007)
Add option to pass SCEVUse-specific flags to getAddExpr and propagate
them through, if valid conservatively. That is, the final expression
adds the same operands (potentially in different order). For example, it
is not valid to propagate the use flags if other (sub-)expressions have
been inlined.
It also includes a few mechanical changes, to update users that still
expected const SCEV *.
This slightly simplifies
https://github.com/llvm/llvm-project/pull/217378, which introduces the
first end-to-end user of SCEVUse.
PR: https://github.com/llvm/llvm-project/pull/220007
Commit: 16884524477d711aabd67b9d4417667463f62603
https://github.com/llvm/llvm-project/commit/16884524477d711aabd67b9d4417667463f62603
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
M llvm/test/CodeGen/SystemZ/zos-align-constpool.ll
Log Message:
-----------
[SystemZ][z/OS] Align constant pool (#222980)
Follow-up to #222128: The call to emit the alignment was places on the
wrong line but the test did not catch it because it checked only the
textual output (which never emits the error message). Fix is to move the
call and update the test.
Commit: 59f5719cac1c1781988255aca7d598a8a48651f9
https://github.com/llvm/llvm-project/commit/59f5719cac1c1781988255aca7d598a8a48651f9
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
A clang-tools-extra/test/clang-tidy/checkers/readability/function-cognitive-complexity-alias.cpp
Log Message:
-----------
[clang-tidy] Fix function-cognitive-complexity crash on aliases (#222965)
Only match function definitions that have a body, since declarations
with the alias attribute satisfy `isDefinition()` without providing one.
Fixes #222958
Commit: 68a20cedb4548b5d8c89f4676bd80cb480ae3591
https://github.com/llvm/llvm-project/commit/68a20cedb4548b5d8c89f4676bd80cb480ae3591
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/Pointer.h
Log Message:
-----------
[clang][bytecode] Simplify Pointer::getByteOffset() (#223382)
Return `Offset` directly, except for block pointers. This also allows us
to remove `getRawOffset()`.
Commit: b3aa937cf54fe348a550cb6017f825d63af7dd49
https://github.com/llvm/llvm-project/commit/b3aa937cf54fe348a550cb6017f825d63af7dd49
Author: Xu <1483685464 at qq.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/PowerPC/popcnt-zext.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/X86/ctpop-mask.ll
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[CodeGen] Optimize ctpop expansion using computeKnownBits (#221671)
The current SWAR popcount implementation always uses the full register
width for the final accumulation step. Even when the input type is much
smaller, such as when counting the bits of an `i8` value, we still use
32-bit operations to extract the result. This patch uses
`computeKnownBits` to determine the minimum number of bits actually
needed to represent the popcount result, and uses this information to
optimize the SWAR popcount expansion.
Commit: 8e6039458ad08d5ed7aaaac08a7db19499a98882
https://github.com/llvm/llvm-project/commit/8e6039458ad08d5ed7aaaac08a7db19499a98882
Author: Hung-Kuan Tseng <tseng.tim096 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir
A mlir/test/Integration/GPU/CUDA/TensorCore/wmma-transposed-store-f16.mlir
Log Message:
-----------
[mlir][vector-to-gpu] Lower transposed transfer_write to a transposed MMA store (#221248)
`convert-vector-to-gpu` lowers a `vector.transfer_read` whose
permutation
map puts the most minor dimension first to a `transpose` MMA load since
18ecdbfe6c74, but still rejects the same shape of
`vector.transfer_write`:
```mlir
// Lowered to gpu.subgroup_mma_load_matrix ... leadDimension 3 transpose
%0 = vector.transfer_read %a[%c0, %c0], %f {in_bounds = [true, true], permutation_map = affine_map<(d0, d1) -> (d1, d0)>} : memref<5x3xf16>, vector<3x5xf16>
// Left alone
vector.transfer_write %1, %b[%c0, %c0] {in_bounds = [true, true], permutation_map = affine_map<(d0, d1) -> (d1, d0)>} : vector<3x5xf16>, memref<5x3xf16>
```
The TODO in `transferWriteSupportsMMAMatrixType` waits for a transpose
attribute on the GPU dialect op. `gpu.subgroup_mma_store_matrix` has had
one since 3d35546cd168, and both the NVVM and the SPIR-V lowerings
honour
it, so this classifies the write the same way as the read and sets the
attribute. `leadDimension` already comes from the position of the map
dimensions, so the stride helper is unchanged.
Tests: the existing `no_convert_write_transpose` becomes a positive
test,
plus the 3-D and 4-D strided cases and a not-last-dim negative case,
mirroring the read side. A tensor core integration test runs a
transposed
`transfer_write` through `convert-vector-to-gpu` and the NVVM pipeline
and
checks the stored matrix; it passes on an RTX 3070 (sm_86).
Commit: 1fc9d6f0272f5bd6213170b0b50ac745b14c5b18
https://github.com/llvm/llvm-project/commit/1fc9d6f0272f5bd6213170b0b50ac745b14c5b18
Author: Owen Anderson <resistor at mac.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/test/CodeGen/RISCV/cheri-global-bounds.ll
Log Message:
-----------
[CHERI][RISCV] Do not attempt to pass in an alignment granule for globals with explicit sections. (#218189)
This can break existing code where that depends on the lack of padding
between variables, e.g. linker sets.
Commit: 86204df4a5d7eeb28b017ac3ebe9a07a7a088e28
https://github.com/llvm/llvm-project/commit/86204df4a5d7eeb28b017ac3ebe9a07a7a088e28
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-parse-ir-input.ll
M clang/test/Driver/ir-exception-model.c
M clang/test/Driver/wasm-toolchain.c
M llvm/include/llvm/Support/CodeGen.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
Log Message:
-----------
WebAssembly: Introduce ExceptionHandling::EmscriptenEH model (#221443)
Add a dedicated EmscriptenEH exception model so the control uses
the standard exception model control, instead of relying on a backend
specific cl::opt. This will later migrate to a module flag and
remove -enable-emscripten-cxx-exceptions
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: beffe43b9edbf24b2066b9e556263eec19d51ba9
https://github.com/llvm/llvm-project/commit/beffe43b9edbf24b2066b9e556263eec19d51ba9
Author: LU-JOHN <John.Lu at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
Log Message:
-----------
[AMDGPU][GISel] Do not scalarize uniform v2f16/v2bf16 operations (#222359)
Previously, register bank legalization would scalarize uniform v2f16 and
v2bf16
floating-point operations on targets with hasSALUFloat (GFX12+) using
the ScalarizeToS16 action. This approach had two problems:
1. It fails for v2bf16 types because there are no scalar bf16
instructions - the scalarization produces illegal bf16 operations
that cannot be selected.
2. Scalar f16 instructions exist, but scalarization is suboptimal.
Packed instructions
like v_pk_add_f16, v_pk_mul_f16, etc. are more efficient than
unpacking to two separate s16 operations.
This patch removes the ScalarizeToS16 rules and instead adds
unconditional .Uni(V2S16) rules that always use
packed VGPR operations for uniform cases.
Operations modified:
- G_FADD, G_FMUL, G_STRICT_FADD, G_STRICT_FMUL
- G_FSUB, G_STRICT_FSUB
- G_FMA, G_STRICT_FMA
- G_FNEG, G_FABS
---------
Signed-off-by: John Lu <John.Lu at amd.com>
Commit: 9f3417b8e4ef6dfdfe3cdadf9447d7e108f9410f
https://github.com/llvm/llvm-project/commit/9f3417b8e4ef6dfdfe3cdadf9447d7e108f9410f
Author: laoshd <shandong.lao at hpe.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Semantics/check-omp-structure.cpp
M flang/test/Semantics/OpenMP/clause-validity01.f90
Log Message:
-----------
[FLANG][OMP] Add error message for invalid dependence type in taskwait construct (#219234). (#220837)
This PR is to fix #219234.
Commit: c4a8bda414e835652b3a75a83660e70419d0c8af
https://github.com/llvm/llvm-project/commit/c4a8bda414e835652b3a75a83660e70419d0c8af
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-sret-res-attrs.c
A clang/test/CIR/Transforms/abi-lowering/dropped-return-res-attrs.cir
Log Message:
-----------
[CIR] Drop res_attrs when a rewritten return has no result (#222465)
An Indirect return moves the value to an sret pointer argument the pass
inserts, and an Ignore return drops it, so the rewritten func or call
has no result for the per-result `res_attrs` array to describe. The
function rewrite and both call rewrites now remove it.
Assisted-by: Cursor / claude-opus-5
Commit: 0e8fd3609aae9dab8e24953a126c1a97871cc7fc
https://github.com/llvm/llvm-project/commit/0e8fd3609aae9dab8e24953a126c1a97871cc7fc
Author: Liza Burakova <liza at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lld/MachO/SyntheticSections.cpp
Log Message:
-----------
[lld-macho] Parallelize ObjFile::sourceFile() during STABS emission. (#222087)
This is part of the ld64.lld performance improvements tracked by #222068
Currently, SymtabSection::emitStabs() calls emitBeginSourceStab() it
passes in file->sourceFile(), which will call
ObjFile::sourceFile(). This method reads the component's root DIE, which
is a bottleneck when done serially as at this stage the DWARF sections
have not been parsed yet.
This commit parallelizes the calls to ObjFile::sourceFile(), as we
already have the file ids stable sorted.
AI tool use: this is one of the commits that was prototyped by AI. I
rewrote this commit and ran the benchmarking myself.
**Benchmark for mac_debug_component_sym_2**
LLD Baseline
Time (mean ± σ): 8.630 s ± 0.479 s [User: 7.170 s, System: 2.012 s]
Range (min … max): 8.147 s … 9.661 s 20 runs
LLD Optimized
Time (mean ± σ): 8.149 s ± 0.373 s [User: 7.410 s, System: 2.206 s]
Range (min … max): 7.804 s … 9.507 s 20 runs
LLD Baseline 2
Time (mean ± σ): 8.365 s ± 0.347 s [User: 7.097 s, System: 1.922 s]
Range (min … max): 8.036 s … 9.146 s 20 runs
Commit: c9e11e5cfa1216f2eebb2f11eaf84cd081790926
https://github.com/llvm/llvm-project/commit/c9e11e5cfa1216f2eebb2f11eaf84cd081790926
Author: Hung-Kuan Tseng <tseng.tim096 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/test/Dialect/GPU/decompose-memrefs.mlir
Log Message:
-----------
[mlir][gpu] Keep memref.load/store attributes in decompose-memrefs (#221312)
`gpu-decompose-memrefs` rewrites a `memref.load`/`memref.store` inside a
`gpu.launch` into a `reinterpret_cast` to the linearised offset plus a
0-d access, but rebuilds the op from the new memref only. `nontemporal`,
`alignment` and `invariant` are dropped from the load, `nontemporal` and
`alignment` from the store:
```mlir
%res = memref.load %arg0[%tx, %ty, %tz] alignment(16) nontemporal(true) invariant(true) : memref<?x?x?xf32>
// becomes
%1 = memref.load %reinterpret_cast[] : memref<f32, strided<[], offset: ?>>
```
The rewrite accesses the same element with the same type, so all of
them still hold on the new op. Pass them to the builder; the attribute
form is the one that also carries `invariant`.
Tests: a load and a store case next to the existing `@decompose_load`
and `@decompose_store`.
AI tool use: I worked on this patch together with an AI assistant
(Claude Code).
Every line of the change and the tests was reviewed and verified by me,
and I am
accountable for it.
Assisted-by: Claude Code
Commit: 00904375820021cc66686504b861f9c0f428a960
https://github.com/llvm/llvm-project/commit/00904375820021cc66686504b861f9c0f428a960
Author: Hugo Pompougnac <tech at hugo-pompougnac.fr>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
M mlir/lib/Dialect/MemRef/Utils/CMakeLists.txt
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
A mlir/test/Dialect/Linalg/hoist-redundant-vector-transfers.mlir
M mlir/test/Dialect/Linalg/hoisting.mlir
Log Message:
-----------
[mlir][linalg] Hoist transfer pairs through disjoint subview slices (#220244)
`hoistRedundantVectorTransfers` previously bailed whenever a transfer
pair was based on a view like `memref.subview`, since another view of
the same buffer could alias it. This patch replaces that blanket bail
with an actual aliasing check: the pair is hoisted when no other access
to the base's underlying buffer in the loop conflicts with it, i.e.
every other access is either the matching read/write or a slice provably
disjoint from the base's static per-dimension footprint. When the base
has no static footprint (e.g. a dynamic subview offset or a
collapse_shape root), the pair still hoists as long as nothing else in
the loop touches the buffer; otherwise it conservatively bails.
The check is implemented as a reusable utility
`memref::hasNoAliasingAccessInScope` in MemRefUtils, and the existing
lone-read path (noAliasingUseInLoop) is unified onto it.
Adds lit tests: positive cases for disjoint static subviews, a dynamic
(loop-invariant) offset, and a collapse_shape root; negative cases for
overlapping subviews and an aliasing non-transfer memory effect.
Assisted-by: Claude Code (Anthropic)
Commit: be6a2b4fddb62515049789e292fa166790a5707b
https://github.com/llvm/llvm-project/commit/be6a2b4fddb62515049789e292fa166790a5707b
Author: Utpal Bora <utpal.bora at cl.cam.ac.uk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
A llvm/test/Transforms/LoopVectorize/AArch64/sve-non-native-interleaved-accesses.ll
Log Message:
-----------
[AArch64] Prohibit vectorizing non-native [de]interleaved pattern for fixed-length SVE (#219244)
This patch prevents LoopVectorize from using non-native interleaved
memory access groups with wider fixed-length SVE.
For wider fixed-length SVE, non-native factors produce awkward wide
shuffles that lower poorly with extra permutes, scalar lane moves, and
sometimes stack traffic. Native interleave factors and NEON-sized fixed
vectors remain allowed.
Commit: 09be00c800cf9ae03a2c8fbdc215c259ac39f30f
https://github.com/llvm/llvm-project/commit/09be00c800cf9ae03a2c8fbdc215c259ac39f30f
Author: David Green <david.green at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AArch64/fptrunc.ll
A llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerTypes.td
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
Log Message:
-----------
[GlobalISel][AArch64] Do not remove dst type predicates from pattern children nodes. (#221576)
Given an instruction with a non-concrete type (G_CONCAT_VECTOR), with a
child pattern instruction with a concrete type (G_FPTRUNC), the concrete
type check for the child would incorrectly be removed. This patch makes
sure they remain. This makes the match table a little larger, but many
should be able to be optimized away (providing that the two operands
with the same type can be matched up).
Fixes #221458
Commit: dcb540e0f268e0de3f22940bd854d079be24415d
https://github.com/llvm/llvm-project/commit/dcb540e0f268e0de3f22940bd854d079be24415d
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-variant.cpp
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[OpenMP] Rename Assocation::LoopSeq to Association::LoopSequence, NFC (#223405)
This will match the name used in spec.
Commit: bb3861e8e155eee3f403e290f633d5a4a04570db
https://github.com/llvm/llvm-project/commit/bb3861e8e155eee3f403e290f633d5a4a04570db
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 0090437 (#223437)
This fixes 00904375820021cc66686504b861f9c0f428a960 (#220244).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=00904375820021cc66686504b861f9c0f428a960
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 3b8919bc85f33419acd3ac096a4265db3f41a32f
https://github.com/llvm/llvm-project/commit/3b8919bc85f33419acd3ac096a4265db3f41a32f
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AMDGPU] Add `getLocalMemorySize` and `getAddressableLocalMemorySize` to TargetParser (#220718)
The number of SIMDs a work-group runs on is a per-kernel mode rather
than a property of the GPU, so it stays a parameter.
Commit: 4eba5bce282ded21bb912b22aae4aa91e27818da
https://github.com/llvm/llvm-project/commit/4eba5bce282ded21bb912b22aae4aa91e27818da
Author: Paweł Bylica <pawel at hepcolgum.band>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AArch64/cgp-usubo.ll
M llvm/test/CodeGen/X86/subcarry.ll
Log Message:
-----------
[DAGCombiner] Require a 0/1 carry-in when rebuilding a borrow chain (#223396)
combineOrOfSetCCToUSUBOCarry (aae871ba1224) rewrites
carry_out = (A <u B) | ((A == B) & carry_in)
to USUBO_CARRY(A, B, carry_in), accepting any value as carry_in.
USUBO_CARRY's third operand is specified as "1 if and only if there is
an incoming carry/borrow", so 0 and 1 are its only meaningful values.
Unlike SADDO_CARRY/SSUBO_CARRY it does not fall back to
getBooleanContents for wider types. The matched `and` is bitwise against
a 0/1 setcc, so only bit 0 of carry_in reaches carry_out and nothing
else constrains it; a carry_in with any other bit set is outside the
operand's contract and miscompiles.
Require carry_in to be known 0/1. Check known bits rather than look for
an `and carry_in, 1`: only bit 0 is demanded inside the `and`, so such a
mask is usually folded away before this combine runs. An i1 carry_in,
which is what a real borrow chain produces, passes trivially.
Fixes #222839.
Assisted-by: Claude Code
Commit: b3f2a866c206f2976cb2c3b551f6f3e3e261516d
https://github.com/llvm/llvm-project/commit/b3f2a866c206f2976cb2c3b551f6f3e3e261516d
Author: Ebuka Ezike <e_ezike at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/Makefile
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/TestStepThroughTrampolineWithSymbol.py
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/add.c
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/add.h
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/main.c
Log Message:
-----------
[lldb] Fix library step-in when the binary is linked with MOLD (#178695)
The mold linker adds a function symbol to the symbol table (.symtab) for
every shared library exported function.
So if we try to step into a library, lldb will fail because the symbol
at the address is not a trampline function.
Example:
```cpp
// lib.c
int lib_add(int a, int b);
```
when we link the library to an executable, mold will create the normal
trampoline functions in the .plt section but add an extra symbol in
symbol table `lib_add$plt`.
Commit: 688119653fd40fa46244e1c300e728677a4f001a
https://github.com/llvm/llvm-project/commit/688119653fd40fa46244e1c300e728677a4f001a
Author: jon-gibney <jonathon.gibney at hpe.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/CodeGen/CGPasses.td
M flang/include/flang/Optimizer/CodeGen/CodeGen.h
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
A flang/test/Fir/convert-to-llvm-unsafe-fp-conversion.fir
Log Message:
-----------
[flang] Respect math flags during conversions (#214311)
We normally use saturating intrinsics when converting from fp to
integers, but when running with -ffast-math we can just use
fptosi/fptoui, which avoids generating expensive overflow/NAN checks.
Assisted-by: Claude Opus
Commit: 3d91765f54e9c461c3f979a5ea7c302f59303489
https://github.com/llvm/llvm-project/commit/3d91765f54e9c461c3f979a5ea7c302f59303489
Author: Rohan Shenoy <RohanRadhesh.Shenoy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd-fadd.ll
Log Message:
-----------
[X86] Fold FMSUBADD + FADD into VFCMADDC for fp16 (#222896)
Complex multiply by conjugate and accumulate fp16 (c += a * ~b) is
lowered into vfmsubadd + vaddph, failing to emit native vfcmaddcph in
avx512fp16. We can reuse the pattern for FSUBADD and extend
combineFaddCFmul to perform this fold.
Fixes #216290
Commit: 21f4aca751cd2e3ff81b0d96c0450f82c26db1b8
https://github.com/llvm/llvm-project/commit/21f4aca751cd2e3ff81b0d96c0450f82c26db1b8
Author: Kai Nacke <kai.peter.nacke at ibm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
A llvm/test/CodeGen/SystemZ/zos-section-readonlywithrel.ll
Log Message:
-----------
[SystemZ][z/OS] Handle constants with initializers with relocations (#223055)
When the initializer of a constant needs relocations, the constant
cannot be placed into the code section, because the loader needs a
writable section to fixup the relocation.
This change
- sets the relocation model for z/OS to `DynamicNoPIC`, which better
fits the relocation handling than `Static`, and
- treats section kind `ReadOnlyWithRel` like a variable.
Assisted by IBM Bob.
Commit: f90096de56d7864cfda3554403f1ef0b8edcb20a
https://github.com/llvm/llvm-project/commit/f90096de56d7864cfda3554403f1ef0b8edcb20a
Author: Joe Nash <joseph.nash at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
A llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err-fake16.s
A llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/literals.s
Log Message:
-----------
[AMDGPU][MC] Diagnose bf16 inline constants without op_sel in the ass… (#223035)
…embler
GFX1250 generates a bf16 inline constant in the high half of the
corresponding fp32 inline constant. The VOP1 bf16 opcodes therefore only
read it correctly in the VOP3 encoding with op_sel[0] set:
v_cvt_f32_bf16, v_rcp_bf16, v_sqrt_bf16, v_rsq_bf16, v_log_bf16,
v_exp_bf16, v_sin_bf16, v_cos_bf16 and v_tanh_bf16.
Codegen has applied this workaround since 57a9c4f939e5, but hand-written
assembly and inline asm had no protection at all and silently assembled
to instructions that read the wrong half. Reject those forms in the
assembler.
Only single-source bf16 opcodes are affected. Multi-source and packed
bf16 instructions such as v_fma_mix*_bf16, which also have a scalar bf16
src0, are explicitly excluded.
GFX1310 has the same FeatureBF16InlineConstFromUpperFP32 behaviour, so
the gfx1250 and gfx13 MC tests are updated together.
Assisted-by: Claude Code:claude-opus-5[1m]
Commit: e4315a87a4128cc36470b2cb5c6009672df5f447
https://github.com/llvm/llvm-project/commit/e4315a87a4128cc36470b2cb5c6009672df5f447
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.cpp
M clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
Log Message:
-----------
[CIR] Accept a union covered only by a bit-field's declared type (#222108)
The size of a union is calculated by its largest member. When that
member is a bit-field, the unit storing it can be narrower than the type
it was declared with, and it is the declared type that accounts for the
union's bytes. BitFieldType gains a query for that declared type, and
the x86_64 union rule reads it rather than the stored size, so `union {
int x : 3; }` and `union { int x : 3; char c; }` now both pass as i32.
A union larger than one eightbyte still needs a member covering it
outright, since the coerce basis skips the entry carrying the
declaration.
Assisted-by: Cursor / claude-opus-5
Commit: 9fb47eebc6c5e03de72a46f74b3d583156f7dfad
https://github.com/llvm/llvm-project/commit/9fb47eebc6c5e03de72a46f74b3d583156f7dfad
Author: Valery Pykhtin <valery.pykhtin at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
Log Message:
-----------
[AMDGPU] Make custom AsmParser matchers alignment aware (#221988)
Currently custom matchers accept registers belonging to unaligned classes, leaving the alignment check and its diagnostic to validateVGPRAlign. The problem is that validateVGPRAlign does not account for the operand register class, which may have a different alignment requirement on mixed-alignment targets.
The fix is to add a custom matcher that resolves the operand's `_AlignTarget` class via HwMode and uses that resolved class to accept a register. The drawback is that this changes the diagnostic from the more specific "error: invalid register class: vgpr tuples must be 64 bit aligned" to the generic "error: invalid operand for instruction" — but keeping the specific one doesn't seem worth the effort.
This commit converts the input-mods and DP-ALU DPP matchers. The no-modifier reg-or-inline operands come next. validateVGPRAlign stays as a catch-all until every operand is converted.
Co-Authored-By: Claude [noreply at anthropic.com](mailto:noreply at anthropic.com)
Commit: 788ae654bebaff36741220c613fb413bb569bc1f
https://github.com/llvm/llvm-project/commit/788ae654bebaff36741220c613fb413bb569bc1f
Author: Evgenii Podkorytov <epodkorytov at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
A llvm/test/Transforms/InferAddressSpaces/infer-address-spaces-overlapping-dead.ll
Log Message:
-----------
[InferAddressSpaces] Safely delete duplicate dead instructions (#222115)
Track deletion candidates with WeakTrackingVH so recursive deletion
cannot leave dangling pointers in later duplicate or overlapping
worklist entries.
Commit: 8c50e52593d6d8f7eb01962d7a6f43a4dae2f4e8
https://github.com/llvm/llvm-project/commit/8c50e52593d6d8f7eb01962d7a6f43a4dae2f4e8
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
Log Message:
-----------
[mlir][NFC] Prune unused copyArrayRefInto template (#222365)
`copyArrayRefInto` has internal linkage, so it is only reachable from
MLIRContext.cpp, and it has no callers there. It is the only mention of
the name in the MLIR tree.
An unused internal-linkage template fires -Wunused-template. That
warning is not in -Wall on main today, having been reverted by
8710728e0418, but it did ship enabled in clang 23.1.0, so building MLIR
with that released compiler under -Werror fails here:
mlir/lib/IR/MLIRContext.cpp:379:20: error: unused function template
'copyArrayRefInto' [-Werror,-Wunused-template]
This is the same deletion as one hunk of #221480, which cleans up the
same warning across 21 MLIR files and is still open. Landing that PR is
the better outcome; this is split out only because the file blocks a
release/23.x build today.
Assisted-by: Claude
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: 7fcd868fff7a6b06fd51c7d3b24220d23ac061f7
https://github.com/llvm/llvm-project/commit/7fcd868fff7a6b06fd51c7d3b24220d23ac061f7
Author: Adrian Prantl <aprantl at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Utility/XcodeSDK.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
Log Message:
-----------
[LLDB] fix a crash when dealing with prefix-remapped sysroot attributes (#223085)
rdar://165704312
Commit: 90f36e05255e9ca5906f21c188f8562b397ed60f
https://github.com/llvm/llvm-project/commit/90f36e05255e9ca5906f21c188f8562b397ed60f
Author: Abid Qadeer <haqadeer at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
Log Message:
-----------
[OpenMP] Remove the LocationDescription constructor that dropped the location. (#221949)
LocationDescription had an implicit conversion from a bare insertion
point, so `ompBuilder->emitSomething(someInsertPoint, ...)` compiled
happily and silently produced an empty debug location. Because
updateToLocation() installs the location unconditionally, this was worse
than a missing assignment: it cleared whatever the builder was carrying,
and the emitted runtime call ended up with no !dbg. On the device those
calls are inlinable, so the verifier rejects them once the runtime
carries debug info -- which is how this kept turning up as bug reports
rather than as anything visible at the callsite.
With the callers in OMPIRBuilder, OpenMPOpt, the MLIR translation and
clang all converted, the constructor can go, and the compiler will now
refuse the shape that caused the problem. Callers have to say which
location they mean: pass the IRBuilder to take its current one, or spell
out the insertion point and location as a pair.
Co-authored-by: Cursor <cursoragent at cursor.com>
Commit: 8eec838ca247c411c30b3452bc403b42e6d521e2
https://github.com/llvm/llvm-project/commit/8eec838ca247c411c30b3452bc403b42e6d521e2
Author: Amit Tiwari <Amit.Tiwari at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M openmp/docs/Building.md
M openmp/libompd/gdb-plugin/CMakeLists.txt
M openmp/libompd/gdb-plugin/README.txt
R openmp/libompd/gdb-plugin/ompdDLService.c
A openmp/libompd/gdb-plugin/ompdDLService.cpp
M openmp/libompd/test/lit.cfg
M openmp/libompd/test/lit.site.cfg.in
M openmp/libompd/test/ompd_dl_service.c
Log Message:
-----------
[OpenMP][OMPD] Load `libompd` with LLVM dynamic lib (#222455)
OMPD loads `libompd.so` through a small helper, but that helper still
uses `dlopen/dlsym` under the hood. We have already laid the foundation
by making libraries load behind helpers in the current state; this one
is simply a cleanup that moves helpers to LLVM's loader, which is LLVM's
standard.
The current state has few issues:
1: Still tied to Unix-style APIs.
2: Windows support has to separately deal with loader differences.
3: Future shared-lib work would need more loader changes later.
This patch keeps the same OMPD API and call sites, but replaces the
implementation with LLVM's DynamicLibrary. Error handling remains
unchanged.
Commit: 797d62d47c361d2658c57523f8a2de4d42906ff4
https://github.com/llvm/llvm-project/commit/797d62d47c361d2658c57523f8a2de4d42906ff4
Author: Miguel A. Arroyo <miguel.arroyo at rockstargames.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/Other/print-on-crash.ll
Log Message:
-----------
[llvm][test] Extend -print-on-crash testing granularity (#222725)
* Extends the testing for `-print-on-crash` based on the additional
granularity of `trigger-crash` introduced by
https://github.com/llvm/llvm-project/pull/220073
Commit: d86120d1b83e8ff36ced6c2379f07efeacfa040c
https://github.com/llvm/llvm-project/commit/d86120d1b83e8ff36ced6c2379f07efeacfa040c
Author: Kunal Pathak <kunalspathak at hotmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
Log Message:
-----------
Add reference of llvm.pseudoprobe in LangRef.md (#223065)
The reference for `llvm.pseudoprobe` intrinsic was missing in `LangRef.md`. Added it.
Assisted-by: Claude
Commit: 9bb24f0654921737fd07b3ac4b2efc03eac8f359
https://github.com/llvm/llvm-project/commit/9bb24f0654921737fd07b3ac4b2efc03eac8f359
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/driver.test
R lld/test/ELF/early-exit-for-bad-paths.s
M lld/test/ELF/map-file.s
Log Message:
-----------
[ELF] Remove tryCreateFile probe for -o/-Map/--why-extract (#222831)
https://reviews.llvm.org/D31603 added an error to fail early for slow
links. However, it would incorrectly reject links that would succeed in
a library use: `--mmap-output-file -o /proc/self/fd/N`.
It also creates and unlinks a temporary file in the output directory for
each of the three paths, and it would mask any change to the output file
strategy, such as rewriting the existing output in place.
Commit: 6ad887ba7827245de1a438cb6dd9149d39ab027d
https://github.com/llvm/llvm-project/commit/6ad887ba7827245de1a438cb6dd9149d39ab027d
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
Log Message:
-----------
[ELF] Parallelize version script and dynamic list matching (#223208)
scanVersionScript and handleDynamicList make one serial pass over
symVector per wildcard pattern, which is inefficient when there are
multiple wildcard patterns.
Parallelize this process: for each symbol, match against all wildcard
patterns and take the first match. This drops the TensorFlow link from
4.8s to 1.8s (--threads=8; its version script has 24 `*foo*` and most
time was in scanVersionScript).
Commit: 298b7a4b8c5a61302634bd657e1d1e471a257f4c
https://github.com/llvm/llvm-project/commit/298b7a4b8c5a61302634bd657e1d1e471a257f4c
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
Log Message:
-----------
[RISCV] Don't use VL node when lowering scalable mask reductions (#223392)
Using ISD::XOR gives us the generic not (setcc cc) -> setcc inverse-cc
combine. With the VL optimizer we still get the same VL propagated.
Restricted to just scalable vectors since some fixed vector patterns
break without the VL node.
The VP test doesn't improve because
1) VP reductions get legalized during regular op legalization, not
vector legalization
2) so generic DAGCombines don't get a chance to run before the
(splat_vector 1) is legalized to vmset_vl.
We can fix this by keeping the (splat_vector 1) legal, but this is left
to another PR.
Commit: f016371f8339c37c7e8f228324a56a15a66ac21b
https://github.com/llvm/llvm-project/commit/f016371f8339c37c7e8f228324a56a15a66ac21b
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/mem2reg.mlir
Log Message:
-----------
[flang] Promote scalar slots reached through fir.convert and fir.declare (#219314)
Neither `fir.declare` nor `fir.convert` implements
`PromotableAliaserInterface`, so mem2reg does not see accesses made
through them as touching the slot behind. A cast anywhere in the chain
blocks promotion outright, even when it only changes the flavor of a
reference to the same scalar. So a scalar slot reached as `memref.alloca
-> fir.convert -> fir.declare -> fir.convert -> store/load` stays in
memory today.
This patch implements `PromotableAliaserInterface` for both operations.
mem2reg collects defining blocks from the alias map, so writes through a
`fir.declare` are now seen and the single-block restriction from
https://github.com/llvm/llvm-project/pull/182933 is no longer needed. An
operation reports an alias only when it carries the pointee through
unchanged, so that the default value projections of the interface apply;
for a `fir.convert` that limits it to a reference or a rank-0 memref of
a simple scalar with an identity layout and no memory space, and never
when either side is volatile.
A `fir.convert` additionally requires every read of the slot to be
preceded, in its own block, by a write. A read that no write reaches
takes the default value of the allocation, which is `fir.undefined` for
`fir.alloca` but poison for the memref allocations a cast can reach.
Without this requirement, promoting through a cast would change what
reading an uninitialized variable produces.
Commit: 8347fb3908a17762f8c0b604a5f25a7d10f6acb6
https://github.com/llvm/llvm-project/commit/8347fb3908a17762f8c0b604a5f25a7d10f6acb6
Author: Joe Nash <joseph.nash at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
Log Message:
-----------
[AMDGPU] Add gfx1310 coverage to the bf16 transcendental tests (#223054)
57a9c4f939e5 made codegen emit the VOP3 encoding with op_sel[0] set when
a bf16 inline constant reaches one of the single-source VOP1 bf16
opcodes, because the hardware generates the constant in the high half of
the corresponding fp32 inline constant.
GFX1310 has the same FeatureBF16InlineConstFromUpperFP32 behaviour.
Mirror the enabled gfx1250 SelectionDAG RUN lines with gfx1310 ones so
the workaround is covered there too. Test-only change, no functional
change.
Assisted-by: Claude Code:claude-opus-5[1m]
Commit: 6e551ef78bd85e71f364f890b245061d394d66a8
https://github.com/llvm/llvm-project/commit/6e551ef78bd85e71f364f890b245061d394d66a8
Author: DeanSturtevant1 <dsturtevant at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc][bazel] Expose public inline memory headers and generic/builtin.h in string_memory_utils (#223439)
Following commit 041300fa05151b3819478f33daa4384922b4b74e (#192079),
`libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h` includes
`src/string/memory_utils/inline_memcpy.h`.
In the Bazel overlay, `string_memory_utils` declared inline memory
dispatcher headers under `textual_hdrs` rather than `hdrs`, preventing
transitive consumers from accessing them. Additionally,
`src/string/memory_utils/generic/builtin.h` was missing from
`string_memory_utils`.
This patch:
- Moves public inline memory headers from `textual_hdrs` to `hdrs` in
`string_memory_utils`:
- `src/string/memory_utils/inline_bcmp.h`
- `src/string/memory_utils/inline_bzero.h`
- `src/string/memory_utils/inline_memcmp.h`
- `src/string/memory_utils/inline_memcpy.h`
- `src/string/memory_utils/inline_memmem.h`
- `src/string/memory_utils/inline_memmove.h`
- `src/string/memory_utils/inline_memset.h`
- `src/string/memory_utils/inline_strcmp.h`
- Adds `src/string/memory_utils/generic/builtin.h` to `textual_hdrs`.
Commit: 2bd15245d5ce07145ddd7e7363ae8552a560db3d
https://github.com/llvm/llvm-project/commit/2bd15245d5ce07145ddd7e7363ae8552a560db3d
Author: Bar Soloveychik <barsolo at meta.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/test/API/functionalities/gdb_remote_client/TestBatchedBreakpointStepOver.py
Log Message:
-----------
[lldb] Fix batched breakpoint step-over mock (#223000)
This PR fixes the test that printed an `UnexpectedPacketException`
because its mock GDB server did not handle LLDB’s final continue packet.
It adds a normal exit response for that packet and verifies that the
process exits successfully with status zero.
Before:
```
An exception happened when receiving the response from the gdb server. Closing the client...
Traceback (most recent call last):
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
694, in run
self._receive(data)
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
714, in _receive
self._handlePacket(packet)
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
807, in _handlePacket
response = self.responder.respond(packet)
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
218, in respond
response = self._respond_impl(packet)
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
231, in _respond_impl
return self.cont()
File "/home/barsolo/llvm-sand/external/llvm-project/lldb/packages/Python/lldbsuite/test/gdbclientutils.py", line
383, in cont
raise self.UnexpectedPacketException()
lldbsuite.test.gdbclientutils.MockGDBServerResponder.UnexpectedPacketException
PASS: LLDB (...) :: test (TestBatchedBreakpointStepOver.TestBatchedBreakpointStepOver.test)
----------------------------------------------------------------------
Ran 1 test in 0.070s
OK
```
After:
```
PASS: LLDB (...) :: test (TestBatchedBreakpointStepOver.TestBatchedBreakpointStepOver.test)
----------------------------------------------------------------------
Ran 1 test in 0.065s
OK
```
Co-authored-by: Bar Soloveychik <barsolo at fb.com>
Commit: 28844a2fcb7ad1a078047b90a286a3ecf02ded5d
https://github.com/llvm/llvm-project/commit/28844a2fcb7ad1a078047b90a286a3ecf02ded5d
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
Log Message:
-----------
[SelectionDAG] Remove dead functions and declarations (NFC) (#223318)
DAGTypeLegalizer::WidenVecOp_ExpOp: Added on April 26, 2023 in commit
eece6ba283bd763e6d7109ae9e155e81cfee0651 without a definition or any
callers.
ScheduleDAGRRList::AddPred: The last uses were removed on April 17, 2019
in commit 258a425c69f0f611ae237ad507252ad18048d2ab when callers were
switched to AddPredQueued.
RegsForValue::append: The last use was removed on January 18, 2019 in
commit 0a45bf0e558e93205a514c856d543fd667099496 when inline asm output
handling was refactored.
Assisted-by: Antigravity
Commit: c5c0b83e6691634bc4ea4dca4303ab8e1deddfd3
https://github.com/llvm/llvm-project/commit/c5c0b83e6691634bc4ea4dca4303ab8e1deddfd3
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
Log Message:
-----------
[gn build] Port 1af17ef01973 (#223467)
Commit: 2a6bd296a0e90bd579ec1874c964781916ec26e9
https://github.com/llvm/llvm-project/commit/2a6bd296a0e90bd579ec1874c964781916ec26e9
Author: Zhen Wang <zhenw at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Support/AllocationPolicy.h
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Optimizer/Support/AllocationPolicy.cpp
M flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/test/Lower/CUDA/cuda-allocatable.cuf
A flang/test/Lower/CUDA/cuda-allocation-policy.cuf
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
M flang/test/Lower/CUDA/cuda-cdevloc.cuf
M flang/test/Lower/CUDA/cuda-cluster.cuf
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/CUDA/cuda-mod.cuf
M flang/test/Lower/CUDA/cuda-module-use.cuf
M flang/test/Lower/CUDA/cuda-proc-attribute.cuf
M flang/test/Lower/CUDA/cuda-shared.cuf
M flang/test/Lower/CUDA/cuda-synchronization.cuf
M flang/test/Transforms/allocation-policy-precedence.fir
A flang/test/Transforms/stack-arrays-policy-opt-out.fir
Log Message:
-----------
[flang][cuda] do not honor -fstack-arrays in device procedures (#223040)
The device stack is far smaller than the host one, so an automatic array
that fits the host stack easily overflows it. With `-fstack-arrays`
(implied by `-Ofast`) automatic arrays in CUDA Fortran `global` and
`device` procedures were kept on the device stack and overflowed it at
runtime.
Lowering now records a `fir.allocation_policy` with `stack_arrays`
disabled on those procedures, and `getAllocationPolicy` honors a policy
on the enclosing function instead of only the one on the module. The
size based part of the policy is unchanged, so small constant size
arrays still go on the device stack. Host procedures, including the host
copy of `attributes(host,device)`, are unaffected.
Commit: a02146be15a8a44aac0e202bcdb449835ebf06f0
https://github.com/llvm/llvm-project/commit/a02146be15a8a44aac0e202bcdb449835ebf06f0
Author: Luke Lau <luke at igalia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
Log Message:
-----------
[RISCV] Consider vmandn.mm in hasAndNot (#223408)
There's a few generic combines that we can take advantage of if we
return true for hasAndNot, e.g. not (setcc x, y, cc) -> setcc x y !cc.
Found with Opus 5
Commit: b16a0c1d3488ddc7d0e406288aae2e363a8af537
https://github.com/llvm/llvm-project/commit/b16a0c1d3488ddc7d0e406288aae2e363a8af537
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
M mlir/test/Dialect/LLVMIR/rocdl.mlir
M mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
Log Message:
-----------
[mlir][ROCDL] Add `rocdl.xnack` and `rocdl.sramecc` module attributes (#222444)
Since 27eeb7370281, the AMDGPU backend takes the xnack
and sramecc target-ID settings from the `amdgpu.xnack` and
`amdgpu.sramecc` module flags instead subtarget features, making the
old usage a hard error.
This commit adds `rocdl.xnack` and `rocdl.sramecc` module attributes
to the discardable attribute list the ROCDL dialect defines in order
to represent these flags and adds translations for them.
Omitting them means to leave these modifiers at
their default "either" state, which isn't the same as setting them to
false.
AI disclosure: Claude wrote this code and I reviewed it and tried to
reword the comments to something better.
Commit: d5104593c0b17a961fb1de465a5fd881a52ebc54
https://github.com/llvm/llvm-project/commit/d5104593c0b17a961fb1de465a5fd881a52ebc54
Author: Aman Maurya <amanmaurya9209 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member.cpp
Log Message:
-----------
[CIR] Support pointer-to-data-member binary operators for aggregates (#221784)
Implement support for pointer-to-data-member binary operators (`.*` and
`->*`) when the result is an aggregate type.
Issue #221783
Commit: 37c1f3fcd867587ccd2a1845d685d8bb4ab105bb
https://github.com/llvm/llvm-project/commit/37c1f3fcd867587ccd2a1845d685d8bb4ab105bb
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/test/CIR/CodeGen/bitint-split-storage-nyi.c
M clang/test/CIR/CodeGen/bitint.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-bitint.c
M clang/test/CIR/CodeGenBuiltins/builtin-bit.cpp
M clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-int-nyi.cir
Log Message:
-----------
[CIR] Accept `_BitInt` wider than 128 bits in x86_64 callconv lowering (#223069)
With byval in place, a `_BitInt` wider than 128 bits can classify
Indirect and flow through the same byval/sret path as an oversized
aggregate.
That turned up a latent bug, fixed here since it was not reachable or
testable before: the byval/sret pointee type was using the raw declared
width instead of the padded storage width (e.g. `i200` instead of
`i256`), understating the copy size.
Widths whose padded storage integer is not a whole number of 16 bytes,
such as `_BitInt(129)` at `i192`, still have no in-memory layout in CIR
and now reach that gap through the byval and sret pointee instead of
through the classifier. They stay NYI.
Drop the opt-out from the three CIR lit tests gated on this.
Assisted-by: Cursor / claude-opus-5
Depends on #222465
Commit: e012338b436a8c7933d3c99924bbbb4cdbcb12d8
https://github.com/llvm/llvm-project/commit/e012338b436a8c7933d3c99924bbbb4cdbcb12d8
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/bindings/interface/SBValueDocstrings.i
M lldb/include/lldb/API/SBExpressionOptions.h
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/Target/Target.h
M lldb/source/API/SBExpressionOptions.cpp
M lldb/source/API/SBValue.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/Makefile
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/TestCreateValueFromExpression.py
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/main.cpp
Log Message:
-----------
[lldb] Speed up `SBValue::CreateValueFromExpression` by using DIL (#222192)
The goal of this patch is to significantly speed up the evaluation of
expressions in the SB API call `SBValue::CreateValueFromExpression`. DIL
is called first and attempts to evaluate the expression, and if it
fails, the function falls back to full expression evaluator. The call to
DIL can be disabled by setting
`target.experimental.use-DIL-for-creating-values` to `false`.
The need for this change comes from `SBValue::CreateValueFromExpression`
often being used in Python data formatters for other projects, where
running the full expression evaluator even for some simple expression
dramatically slows down the entire formatter. The performance overhead
if DIL fails to evaluate the expression is only marginal.
Commit: 46072765883ed39743a16d59cf4303e7f2e23f04
https://github.com/llvm/llvm-project/commit/46072765883ed39743a16d59cf4303e7f2e23f04
Author: Ilia Kuklin <ikuklin at accesssoftek.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/ValueObject/DILEval.cpp
M lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/TestCreateValueFromExpression.py
Log Message:
-----------
[lldb] Fix DIL losing StackFrame context after casting to pointer (#222386)
When casting to pointer type, `CreateValueObjectFromAddress` is called
with Target context only, so the resulting `ValueObject` doesn't have
StackFrame context anymore, which can cause problems when it is returned
as a final result from DIL. This patch fixes the issue.
Commit: 5f653742770a13e3f2b8428b31df7bc226406739
https://github.com/llvm/llvm-project/commit/5f653742770a13e3f2b8428b31df7bc226406739
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/test/HLFIR/simplify-hlfir-intrinsics-eoshift.fir
Log Message:
-----------
[Flang][HLFIR] Bail out of EOSHIFT simplification for polymorphic arrays (#223118)
Consider the following code
```
module m
type Base
integer :: i = 8
end type
type, extends(Base) :: Child
integer :: j = 9
end type
end module
program argumentKeyword002
use m
class(*), pointer :: b1(:,:,:), boundVal
allocate(b1(3,2,2), SOURCE=reshape((/(i,i=1,12)/), &
(/3,2,2/)))
allocate (boundVal, source=0)
select type(name1=>eoshift(SHIFT=reshape((/1,-2,2,-1/),(/2,2/)), &
ARRAY=b1,DIM=1, BOUNDARY=boundVal))
type is (integer)
print *, name1
print *, shape(name1)
class default
ERROR STOP(1_4)
end select
end
```
it passed at `-O0` but failed at `-O3` as
```
argumentKeyword002.f":38:5): error: 'fir.result' op types mismatch between result op and its parent
error: Lowering to LLVM IR failed
```
The reason is that the `SimplifyHLFIRIntrinsics` is trying to inline
`EOSHIFT` of a `CLASS(*)` array as an `hlfir.elemental` produces a
`fir.if` with mismatched types on the branches (e.g., `!fir.class<none>`
vs. pointer-qualified `!fir.class<!fir.ptr<none>>`).
By looking at the code, we currently bail-out derived type array so it
falls back to the runtime code. Polymorphic array should be bailed-out
also for now and handled with derived type together in the future.
Commit: e226b9ea3e4c2e87ab36209f3c1dd83faa98e429
https://github.com/llvm/llvm-project/commit/e226b9ea3e4c2e87ab36209f3c1dd83faa98e429
Author: Alexey Samsonov <vonosmas at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/src/unistd/linux/sysconf.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/msync_test.cpp
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
Log Message:
-----------
[libc] Restrict sysconf/confstr to full-build mode. (#223103)
`sysconf` (and its sibling `confstr`) from `<unistd.h>` return some
values specific to the kernel/environment,
and some values specific to the system library (e.g. features available
in system library's pthread implementation).
Using LLVM-libc sysconf in overlay mode is inherently problematic - we
don't know what features host libc has,
and trying to reverse-engineer it would be brittle. Since we include
host libc's `<unistd.h>`, we can't even know in
advance what `_SC_` values or what macros would be available there, so
the portable implementation of `sysconf`
will be convoluted, and there's little benefits to it anyway.
Conversely, making sure that our `sysconf` implementation only compiles
against LLVM-libc's own headers will allow
us to precisely handle macro / features that we know are available /
supported.
Migrate four tests from sys/mman.h to use `getpagesize()` function
instead of generic `sysconf` to ensure those
tests won't be auto-excluded in overlay mode.
Remove the workarounds for overlay-mode added to sysconf(), since those
are no longer needed.
Commit: 45e9b1a1baea960e4a0d549df558ee0333c9edd4
https://github.com/llvm/llvm-project/commit/45e9b1a1baea960e4a0d549df558ee0333c9edd4
Author: Bar Soloveychik <barsolo at meta.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/include/lldb/Core/DumpRegisterValue.h
M lldb/source/Commands/CommandObjectRegister.cpp
M lldb/source/Core/DumpRegisterValue.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterVector.py
Log Message:
-----------
[lldb] Display GDB remote register vector values (#222724)
This completes GDB remote vector support in LLDB’s CLI.
- `register read <vector>` prints the raw register followed by typed
lanes.
- Supports direct, nested, three lane, byte, bool, and pointer vectors.
- Handles target byte order correctly.
- Explicit `--format` continues to show only the requested format.
- Bulk register reads remain compact.
- Unsupported flag widths safely remain raw.
Examples:
```
(lldb) register read v0
v0 = {0x00 0x00 0xc0 0x3f 0x00 0x00 0x20 0x40 0x00 0x00 0x60 0x40 0x00 0x00 0x90 0x40}
= ([0] = 1.5, [1] = 2.5, [2] = 3.5, [3] = 4.5)
(lldb) register read nested
nested = {0x00 0x00 0xc0 0x3f 0x00 0x00 0x20 0x40 0x00 0x00 0x60 0x40 0x00 0x00 0x90 0x40}
= {
[0] = ([0] = 1.5, [1] = 2.5)
[1] = ([0] = 3.5, [1] = 4.5)
}
(lldb) register read v3
v3 = {0x00 0x00 0xc0 0x3f 0x00 0x00 0x20 0x40 0x00 0x00 0x60 0x40}
= ([0] = 1.5, [1] = 2.5, [2] = 3.5)
(lldb) register read bytes
bytes = {0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f}
= ([0] = 0x00, [1] = 0x01, [2] = 0x02, [3] = 0x03, [4] = 0x04, [5] = 0x05, [6] = 0x06, [7] = 0x07, [8] = 0x08, [9] = 0x09, [10] = 0x0a, [11] = 0x0b, [12] = 0x0c, [13] = 0x0d, [14] = 0x0e, [15] = 0x0f, [16] = 0x10, [17] = 0x11, [18] = 0x12, [19] = 0x13, [20] = 0x14, [21] = 0x15, [22] = 0x16, [23] = 0x17, ...)
(lldb) register read bools
bools = {0x00 0x00 0xc0 0x3f 0xff 0xff 0xff 0xff 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}
= {
[0] = false
[1] = false
[2] = true
[3] = true
[4] = true
[5] = true
[6] = true
[7] = true
[8] = false
[9] = false
[10] = false
[11] = false
[12] = false
[13] = false
[14] = false
[15] = false
}
(lldb) register read ptrs
ptrs = {0x00 0x00 0xc0 0x3f 0x00 0x00 0x20 0x40 0x00 0x00 0x60 0x40 0x00 0x00 0x90 0x40}
= ([0] = 0x402000003fc00000, [1] = 0x4090000040600000)
(lldb) register read -f hex v0
v0 = 0x4090000040600000402000003fc00000
```
---------
Co-authored-by: Bar Soloveychik <barsolo at fb.com>
Commit: 9fdb3bbd29ea03834f325373efe5ee0ea9fe4061
https://github.com/llvm/llvm-project/commit/9fdb3bbd29ea03834f325373efe5ee0ea9fe4061
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
[SandboxVec][VecUtils][NFC] BndlRef helper class (#223074)
During debugging we need to be able to easily print a bundle of
instructions or values. Up until now we would use VecUtils::dump(Bndl).
But a much nicer API would be Bndl.dump().
To support such an API this patch is introducing BndlRef, a subclass of
ArrayRef with the additional feature of supporting print(OS) and dump()
for Value and Instruction contents.
Commit: 7b8bb9d1f379da437eacfa7f4de96957e41956c6
https://github.com/llvm/llvm-project/commit/7b8bb9d1f379da437eacfa7f4de96957e41956c6
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Expose remapRegClassByHwMode() helper in AsmMatcher
This is useful to map from a ByHwMode MCK_* value to the actual resolved
MCK_* type. This is needed for #177073 where we would otherwise have to
add the manual logic to do this remapping (which is the approach I
previously used). Move RegClassByHwModeMatchTable to file scope and
provide a remapRegClassByHwMode() helper function in the generated
AsmMatcher. Currently only used for RISC-V, but I assume other targets
could also make use of this in the future. But even if not, I think it's
cleaner to have this as a helper rather than an inline array inside the
matcher function.
This change was created with the help of AI tools.
Reviewed By: arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/223302
Commit: 1d073217b664263f62ff01db623ed7542fde6fda
https://github.com/llvm/llvm-project/commit/1d073217b664263f62ff01db623ed7542fde6fda
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
Revert "[SandboxVec][VecUtils][NFC] BndlRef helper class" (#223483)
Reverts llvm/llvm-project#223074
Reason: unittest failure in NDEBUG
Commit: 2a51b6c31ba45a3be70001b71f7f7dc517288bca
https://github.com/llvm/llvm-project/commit/2a51b6c31ba45a3be70001b71f7f7dc517288bca
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/Other/print-on-crash.ll
Log Message:
-----------
[llvm][test] Quote args in -print-on-crash test (#223472)
Passing `-passes=cgscc(trigger-crash-cgscc)` in lit works because of its
shell handling, but fails when passing directly to a shell: ` syntax
error near unexpected token '('`.
Commit: 9ee32f72f4415b3e2b7acbf4237b8cc0daa3c8b7
https://github.com/llvm/llvm-project/commit/9ee32f72f4415b3e2b7acbf4237b8cc0daa3c8b7
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
[NFC] Hoist DiagOpts.showColors(OS.has_colors()) out of emitSnippet's per-character loop (#223095)
The result of DiagOpts.showColors(OS.has_colors()) does not change while
printing a single source snippet, so recomputing it for every character
is unnecessary. Compute it once per snippet instead.
rdar://186469856
Co-authored-by: Fred Riss <friss at apple.com>
Commit: faae30dc2c7aab136b366b5ee1b2adfcf4c2021b
https://github.com/llvm/llvm-project/commit/faae30dc2c7aab136b366b5ee1b2adfcf4c2021b
Author: Akira Hatanaka <ahatanak at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/FormattedStream.h
M llvm/unittests/Support/formatted_raw_ostream_test.cpp
Log Message:
-----------
[Support] Make formatted_raw_ostream::has_colors() delegate to the wrapped stream (#223092)
Without this override, has_colors() falls back to is_displayed(), which
isn't always expected to give the same answer as the underlying stream's
has_colors().
This also fixes a compile-time regression when the underlying stream is
a raw_fd_ostream: raw_fd_ostream::has_colors() memoizes its result, but
without this override that memoization was bypassed in favor of the
uncached is_displayed(), issuing an isatty() syscall on every call.
#202441 is what surfaced this, by adding a has_colors() call to
TextDiagnostic's per-character hot loop.
rdar://186469856
Co-authored-by: Fred Riss <friss at apple.com>
Commit: 18795f5c5596f783c18f8483848b632084885756
https://github.com/llvm/llvm-project/commit/18795f5c5596f783c18f8483848b632084885756
Author: Laxman Sole <lsole at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
A llvm/test/CodeGen/NVPTX/inline-asm-line-info-per-inst-compiler-generated.ll
Log Message:
-----------
[DebugInfo][NVPTX]Avoid adding per line .loc in the ptx output for the compiler-generated inline ptx block. (#222764)
`NVPTXAsmPrinter::emitInlineAsm` splits the asm string on newlines and
emits a `.loc` per PTX instruction, incrementing the source line for
every physical line of the block. For a compiler-generated block, this
attributes the generated code to unrelated source lines, and for a long
enough block, to lines beyond the end of the file.
A DSL frontend can lower one source-level construct -- an assert, a
barrier, an intrinsic -- into a single block of inline PTX. The
individual lines of that block have no source correspondence; they all
belong to the one construct.
This change adds a check for isImplicitCode on the inline asm's
DILocation and skips the per-line path when it is set.
Commit: b3000bf61b40b945c196e76bfa7cd722adf09dac
https://github.com/llvm/llvm-project/commit/b3000bf61b40b945c196e76bfa7cd722adf09dac
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
M compiler-rt/lib/ubsan/CMakeLists.txt
A compiler-rt/lib/ubsan/offload/CMakeLists.txt
A compiler-rt/lib/ubsan/offload/hsa.h
A compiler-rt/lib/ubsan/offload/ubsan_offload.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa_interceptors.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_report.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_rpc.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_rpc.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_symbolize.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_symbolize.h
M compiler-rt/lib/ubsan/ubsan_diag.cpp
M compiler-rt/lib/ubsan/ubsan_diag.h
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
A compiler-rt/lib/ubsan/ubsan_handlers_internal.h
M compiler-rt/lib/ubsan/ubsan_interface.inc
A compiler-rt/lib/ubsan/ubsan_offload.cpp
A compiler-rt/lib/ubsan/ubsan_offload_checks.inc
A compiler-rt/lib/ubsan/ubsan_offload_packet.h
M compiler-rt/lib/ubsan/ubsan_value.h
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/ubsan/AMDGPU/abort.hip
A compiler-rt/test/ubsan/AMDGPU/dedup.hip
A compiler-rt/test/ubsan/AMDGPU/host-and-device.hip
A compiler-rt/test/ubsan/AMDGPU/lit.local.cfg.py
A compiler-rt/test/ubsan/AMDGPU/openmp-overflow.cpp
A compiler-rt/test/ubsan/AMDGPU/overflow-i128.hip
A compiler-rt/test/ubsan/AMDGPU/overflow.hip
A compiler-rt/test/ubsan/AMDGPU/shift.hip
M compiler-rt/test/ubsan/CMakeLists.txt
A compiler-rt/test/ubsan/Inputs/hip.h
M compiler-rt/test/ubsan/lit.common.cfg.py
M compiler-rt/test/ubsan/lit.site.cfg.py.in
M llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn
Log Message:
-----------
[compiler-rt] Add AMDGPU Device UndefinedBehaviorSanitizer runtime (#219972)
Summary:
This adds support for full UBSan on the AMDGPU target. The GPU build of
`compiler-rt` will now build `libclang_rt.ubsan_standalone.a` and the
host build will now provide `libclang_rt.ubsan_offload.a` for the
host-side formatting.
The **core** approach is to simply gather arguments from the device and
replay them on the host. The RPC interface acts as the narrow shim to
pass data between the CPU and GPU.
The changes to the core runtime are kept minimal, only exposing a few
needed hooks to re-run and symbolize reports coming from an external
caller. The device archive is a side-library which will only be present
for GPU offloading builds.
Putting this in `compiler-rt` via interceptors avoids an ABI edge
between many consumers, (OpenMP, HIP, Pytorch, etc). The runtime code is
specifically built around HSA, but as more features grow this could be
refactored into a shim layer for SPIR-V / CUDA and factored out to a
common sanitizer utility. Leaving that as future work.
```console
clang -xhip -fsanitize=undefined --offload-arch=native app.hip
clang -fopenmp -fsanitize=undefined --offload-arch=native app.cpp
```
---
Tested using the HIP suite in https://github.com/ORNL/HeCBench. Ran
against 162 programs on my gfx1030 vs an unsanitized `-O3` baseline:
| Metric | Geomean |
| ----------------- | ------: |
| Kernel time | 2.12x |
| Wall time | 1.58x |
| Device image size | 3.22x |
| Host binary size | 20.43x |
| Compile time | 1.19x |
| Resource | Change |
| ---------------------- | -----: |
| VGPR | +19 |
| SGPR | +32 |
| Scratch (B/lane) | 52/140 |
| Occupancy (waves/SIMD) | 11/140 |
The tool identified three instances of UB on the HIP device with zero
false positives.
```
atomicAggregate (6 reports)
Device: main.cu:29 signed overflow -2147483648 - 1 (int)
background-subtract (6 reports)
Device: main.cu:75 259.48 does not fit in unsigned char
particlefilter (39 reports)
Device: kernel_likelihood.h:37 signed overflow in the LCG (1103515245 * …)
```
---
<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Commit: 83cb8bd4c9b17d031d6a4519d74c76650e850427
https://github.com/llvm/llvm-project/commit/83cb8bd4c9b17d031d6a4519d74c76650e850427
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Driver/CommonArgs.h
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/UEFI.cpp
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.ubsan_standalone.a
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/x86_64-unknown-linux-gnu/libclang_rt.ubsan_offload.a
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/x86_64-unknown-linux-gnu/libclang_rt.ubsan_standalone.a
A clang/test/Driver/fsanitize-undefined-offload.c
Log Message:
-----------
[Clang] Enable UBSan for AMDGPU device offload (#219973)
Summary:
This enables the device UBSan runtime for AMDGPU devices. Primarily this
required modifications to the `addSanitizerRuntime` interface so we can
query the compilation's offload status. Also need to forward it through
the linker wrapper interface. Works on all AMDGPU offload, slight hacks
around the other targets as they do not advertise sanitizer
runtimes properly.
This is linked in via a new `-u __ubsan_offload_init` hook to pull
in the side library. This is standard behavior and keeps the core logic
mostly unchanged and re-used.
---
<sub>Stack created with <a
href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a
href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
Commit: 23dac5c4f996a314184ab5edb0bbadad93e32f6b
https://github.com/llvm/llvm-project/commit/23dac5c4f996a314184ab5edb0bbadad93e32f6b
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M offload/ci/hip-tpl.py
Log Message:
-----------
[HIP] Use new spelling in buildbot script (#223491)
This adds the new spelling to enable HIP Kokkos tests in the buildbot
script.
The old spelling will be removed.
Commit: 20fe9f35da9952f60188212c5f51debb07af24ca
https://github.com/llvm/llvm-project/commit/20fe9f35da9952f60188212c5f51debb07af24ca
Author: Roland McGrath <mcgrathr at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/src/__support/macros/properties/cpu_features.h
M libc/src/string/memory_utils/op_generic.h
Log Message:
-----------
[libc] Don't declare vector_size types that cannot be compiled (#221119)
On machines where [[gnu::vector_size(N)]] types are generally
supported, each given N can only be used when the corresponding
CPU features are enabled by the particular -m switches et al.
Don't make any use of a type that's not enabled for native
register use according to the predefines reflecting -m switches.
Even inline and template functions that wind up being unused can
make the compiler give errors about the use of a type whose use
is disabled for ABI or ISA configuration reasons.
Commit: 198cabe1180311b0ec9c1969632e9647c316729c
https://github.com/llvm/llvm-project/commit/198cabe1180311b0ec9c1969632e9647c316729c
Author: jiel-nv <37816794+jiel-nv at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.h
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/Dialect/FIRCG/CMakeLists.txt
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/test/Fir/declare-codegen.fir
A flang/test/Transforms/debug-cuf-device-variable.fir
Log Message:
-----------
[flang][cuda] Exclude device variables from host debug info (#222241)
Commit: def780a5607b989a7a0b665418beb945f2474ef9
https://github.com/llvm/llvm-project/commit/def780a5607b989a7a0b665418beb945f2474ef9
Author: Petr Hosek <phosek at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/cookie_io_functions_t.h
M libc/src/stdio/fopencookie.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fopencookie_test.cpp
Log Message:
-----------
[libc] Change cookie_seek_function_t to take off_t argument (#223306)
cookie_seek_function_t is defined as taking off_t rather than off64_t
for offset argument in all C library implementations that support
fopencookie.
Commit: 724968e60fcf2a0dca3c18a9faa2b639185f7656
https://github.com/llvm/llvm-project/commit/724968e60fcf2a0dca3c18a9faa2b639185f7656
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
Log Message:
-----------
[Offload] Link against specific HSA library and then fallback (#223454)
Summary:
HSA uses a versioning system, the `.1` is usually a more specific
release while one without is a generic or untested version. We should
use the specific one and fall back.
Commit: aa261b730fe1dd212160de5ba64ed2a71a20b72c
https://github.com/llvm/llvm-project/commit/aa261b730fe1dd212160de5ba64ed2a71a20b72c
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
Log Message:
-----------
[NFC][AMDGPU] Move i64 int to fp narrowing tests into their own file (#223463)
Commit: e219016c1903fe0f4877ef0f6f2f9ce1f4351d5c
https://github.com/llvm/llvm-project/commit/e219016c1903fe0f4877ef0f6f2f9ce1f4351d5c
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M compiler-rt/test/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Fix host-only AMDGPU tests being added to GPU build (#223505)
Summray:
We do have AMDPGU tests, but these are for the standalone / minimal
configurations that don't require any host runtime. The tests added in
the previous patch are for offloading, i.e. HIP or OpenMP, not C/C++
compiled fro the GPU.
Commit: 9fad63f308b5a6e1cf0b1599e606732915201cac
https://github.com/llvm/llvm-project/commit/9fad63f308b5a6e1cf0b1599e606732915201cac
Author: Domenic Nutile <domenic.nutile at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
Log Message:
-----------
[AMDGPU][True16][GlobalISel] Update True16 handling for FMA_MIX instructions in GlobalISel (#205431)
The FMA_MIX instructions can extend 16-bit input values, but must have
32-bit registers as operands. This patch handles cases in True16 mode
where the 16-bit input value lives in a VGPR-16 and must be widened.
Commit: 54ce74d9a41991b2a00eb4d373aa3b8d45b34851
https://github.com/llvm/llvm-project/commit/54ce74d9a41991b2a00eb4d373aa3b8d45b34851
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn
Log Message:
-----------
[gn build] Port b3000bf6 (#223509)
Commit: f7028e8a2ef42f26e89a5938bc6b2e7b3fcb4504
https://github.com/llvm/llvm-project/commit/f7028e8a2ef42f26e89a5938bc6b2e7b3fcb4504
Author: Bhavesh M <85327930+beamandala at users.noreply.github.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/execv.cpp
Log Message:
-----------
[libc] Use execve syscall wrapper in execv.cpp (#223181)
Use the existing execve syscall wrapper in `execv.cpp` instead of
invoking SYS_execve directly.
Commit: 80cbdafb4f39ef539366c13436b266398176af6d
https://github.com/llvm/llvm-project/commit/80cbdafb4f39ef539366c13436b266398176af6d
Author: Bhavesh M <85327930+beamandala at users.noreply.github.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/execve.cpp
Log Message:
-----------
[libc] Use execve syscall wrapper in execve.cpp (#223186)
Use the existing execve syscall wrapper in `execve.cpp` instead of
invoking SYS_execve directly.
Commit: a3c0080c816b0225a20a3c3aac3da5d91391f1e7
https://github.com/llvm/llvm-project/commit/a3c0080c816b0225a20a3c3aac3da5d91391f1e7
Author: jiel-nv <37816794+jiel-nv at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Dialect/FIRCG/CMakeLists.txt
Log Message:
-----------
[flang][cuda][NFC] Link FIRCodeGenDialect against CUFAttrs (#223511)
Fix the build issue triggered by #222241. Add the missing link
dependency.
Commit: 70f2f92830622086356f59a462c1d362c329be2a
https://github.com/llvm/llvm-project/commit/70f2f92830622086356f59a462c1d362c329be2a
Author: PiJoules <leonardchan at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
R llvm/test/Transforms/RelLookupTableConverter/relative_lookup_table.ll
Log Message:
-----------
[RelLookupTableConverter] Restore X86/relative_lookup_table.ll and add AArch64 test (#223494)
Move relative_lookup_table.ll back to X86/ and restore the original
assertions, undoing manual edits to generated check lines and addressing
post-commit review feedback on #222809. Note that PR already added a
test which checks for the minor `unnamed_addr` difference between x86
and arm.
Commit: 1ce16b4a5fd640ba44518980e3391789d3ab30fa
https://github.com/llvm/llvm-project/commit/1ce16b4a5fd640ba44518980e3391789d3ab30fa
Author: Quentin Colombet <quentin.colombet at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
Log Message:
-----------
[RegAllocEvictionAdvisor] Make the local reassign option more useful (#223115)
Prior to this patch the CLI option for the local reassignment heuristic
could only force enabling the local reassignment heuristic. In other
words, there was no way to disable the heuristic if the target hook said
otherwise, which defeated the purpose of the option.
Fix this by ensuring that when the option is set it takes precedence
over the target hook. This makes experimenting with the local
reassignment heuristic much easier.
The patch is NFC unless you set the option.
Test by: Daniil Fukalov <daniil.fukalov at amd.com> assisted by GPT-6 Astra
Commit: 46f16a308de7b933bbeb83e69d1b8bac2d2889c9
https://github.com/llvm/llvm-project/commit/46f16a308de7b933bbeb83e69d1b8bac2d2889c9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M compiler-rt/lib/ubsan/offload/ubsan_offload_hsa_interceptors.cpp
Log Message:
-----------
[compiler-rt] Do not intercept 'dlsym' for PowerPC due to musttail (#223516)
Summary:
musttail is not supportedi n PPC but it required to faithfully implement
RTLD_NEXT, so just disable intercepting `dlsym`, means that
Offload-brand ubsan usage will not work on PPC without dictating direct
linking.
Commit: c115db8da9fe007bd7804c12bb7bb62a9ca569ba
https://github.com/llvm/llvm-project/commit/c115db8da9fe007bd7804c12bb7bb62a9ca569ba
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
R libcxx/test/libcxx/diagnostics/unused_variables.compile.pass.cpp
R libcxx/test/libcxx/diagnostics/unused_variables.verify.cpp
A libcxx/test/libcxx/unused_variables.compile.pass.cpp
A libcxx/test/libcxx/unused_variables.verify.cpp
Log Message:
-----------
[libc++][test-suite][NFC] Move `unused_variables` tests (#223234)
`[diagnostics]` is a section in The Standard
https://wg21.link/diagnostics. According to libc++ test-suite
organization `libcxx/test/libcxx/diagnostics/` should contain related
tests.
The following tests:
- `unused_variables.compile.pass.cpp`
- `unused_variables.verify.cpp`
should live in:
- `libcxx/test/libcxx/`
This is a follow-up to the re-organization of `nodiscard.verify.cpp`
tests, which initially were also placed in `diagnostics`.
---------
Co-authored-by: Hristo Hristov <zingam at outlook.com>
Commit: 1e089918fca00a683921f0f45b32cce8d1f9026b
https://github.com/llvm/llvm-project/commit/1e089918fca00a683921f0f45b32cce8d1f9026b
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/src/__support/big_int.h
M libc/src/__support/math_extras.h
Log Message:
-----------
[libc][baremetal][BigInt] fix codegen issue for UInt128 (#220389)
`BigInt::operator*` always computes the full 2N-word product (`ful_mul`,
i.e. `multiword::multiply_with_carry`) and then truncates. In order to
scalarize the process to generate efficient code, the loop needs to be
fully unrolled, which fails on 32-bit targets for int128 due to LLVM's
default threshold. This patch adjust the hint to allow int128 to be
unrolled while gating larger integers away.
### 64-bit targets: roughly okay
aarch64 is byte-identical before/after; x86-64 gets one `mov` shorter.
After the patch, 128×128→128 (lo/hi in memory):
```asm
; aarch64 ; x86-64
ldp x8, x12, [x0] movq (%rdi), %r9
ldp x9, x10, [x1] movq (%rsi), %r8
mul x10, x10, x8 movq %r8, %rax
mul x11, x9, x8 mulq %r9
umulh x8, x9, x8 imulq 8(%rsi), %r9
madd x9, x9, x12, x10 imulq 8(%rdi), %r8
add x8, x9, x8 addq %r9, %r8
stp x11, x8, [x2] addq %rdx, %r8
ret ...
```
### 32-bit targets (e.g. cortex-m85): badly bloated
A 64-byte stack frame, carry selection through IT blocks, and a call
into an outlined `ful_mul`. Kernel is the folded multiply (`lo ^ hi` of
the `UInt<128>` product):
```asm
; before ; after
sub sp, #64 umull r12, lr, r2, r0
mov.w r12, #0 umull r2, r4, r2, r1
strd r12, r12, [sp, #24] umull r0, r5, r3, r0
orrs.w lr, r0, r1 umaal r4, r5, r3, r1
it ne adds.w r1, lr, r2
strdne r0, r1, [sp, #16] adcs r2, r4, #0
... (5 more stores) adc r3, r5, #0
bl BigInt<128>::ful_mul adds r0, r0, r1
ldm r3, {r0, r1, r2, r3} adcs r2, r2, #0
eors r1, r3 adc r1, r3, #0
eors r0, r2 eors r1, r0
add sp, #64 eor.w r0, r2, r12
```
llvm-mca (cortex-m85): **114 → 11 cycles** per folded multiply.
### Benchmarks
| environment | before | after | speedup |
|---|---|---|---|
| EK-RA8M2 (Cortex-M85 r1p1, DWT cycle counter, I-cache on) | 250
cyc/mul | 20 cyc/mul | 12.5× |
| wasm32 under wasmer 7.3, `-U__SIZEOF_INT128__` (see notes) | 0.70 s /
100M muls | 0.28 s | 2.5× |
Bench kernel (dependent chain, identical results before/after):
```cpp
using B = LIBC_NAMESPACE::BigInt<128, false, uint64_t>;
B x = (B(a) << 64) | B(~a);
B y = (B(b) << 64) | B(~b);
for (int i = 0; i < n; i++) {
x = x * y;
y.val[0] ^= x.val[1];
}
return x.val[0] ^ x.val[1];
```
### Carry builtin dispatch fix
Additionally, fix a typo in the `add_with_carry` / `sub_with_borrow`
builtin dispatch: the `#if`/`#elif` chain over `__has_builtin`.
### Notes
1. Another workaround for such targets is to force-enable native 128-bit
integers (clang's `-fforce-enable-int128`)
2. The wasm number above is benched with 128-bit integers forcibly
disabled (`-U__SIZEOF_INT128__`), just to check its effect.
---
Guided and reviewed by human
Co-Authored-By: Claude Fable 5 <noreply at anthropic.com>
---------
Co-authored-by: Claude Fable 5 <noreply at anthropic.com>
Commit: 199ade2027a2f0b20504d288db6388aa11332a40
https://github.com/llvm/llvm-project/commit/199ade2027a2f0b20504d288db6388aa11332a40
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/induction-cost.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
Log Message:
-----------
[VPlan] Use VPlan-based costs for pointer inductions. (#223394)
Drop the last legacy induction fallback in precomputeCosts, completing
the migration of induction costs to be VPlan-based.
The fallback charged the cost of the IV phi. The cost of the GEP
incrementing the IV was considered free.
VPWidenPointerInduction::computeCost now charges the cost of the phi
plus a TODO to also consider cost of the increment and wide pointer add.
For scalarized pointer inductions, we do not charge any cost for the
scalar GEPs, like before, assuming they can be folded into the
addressing mode.
Test changes are due to the fact that scalarized pointer inductions do
not require an extra phi (on most platforms, phis are considered free,
so not many tests are impacted).
PR: https://github.com/llvm/llvm-project/pull/223394
Commit: 081a3f0ca08e60747bf90620c0644af44321b9a4
https://github.com/llvm/llvm-project/commit/081a3f0ca08e60747bf90620c0644af44321b9a4
Author: Avi Kivity <avi at scylladb.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
A clang/test/PCH/flag-enum.c
Log Message:
-----------
Revert "[clang][NFC] Refactor flag enum caching (#210632)" (#223244)
This reverts commit f5437c4d4f2e9920614d856158d9683d650acffa.
That change moved population of Sema::FlagBitsCache out of
IsValueInFlagEnum and into ActOnEnumBody, and turned the lookup into
DenseMap::at(). ActOnEnumBody only runs for enum definitions that are
parsed in the current translation unit, so an EnumDecl deserialized from
a PCH never gets a cache entry and DenseMap::at() dereferences end(),
crashing clang in builds without assertions.
A switch over any enum with the flag_enum attribute that is defined in a
PCH is enough to reproduce. The crash cannot be avoided by turning the
switch diagnostics off: unlike DiagnoseAssignmentEnum, the switch path
in ActOnFinishSwitchStmt has no Diags.isIgnored() guard, because it runs
the analysis regardless in order to record the result in the AST.
In practice this breaks any translation unit that instantiates
std::basic_regex<char> while <regex> is in a PCH, since libstdc++ marks
std::regex_constants::syntax_option_type as a flag enum and
_Compiler<_TraitsT>::_S_validate switches over it. That became reachable
with 44b33260a38c, which made clang honor the gnu:: spelling of the
attribute, but the underlying defect is the one reverted here.
Add a regression test for the PCH path. It checks the computed flag bits
rather than just the absence of a crash, so that a silently empty cache
entry fails the test instead of passing it.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Fixes #223243
Commit: 44ebda796ec9b6a43d5bef01efe58c0c67b8c971
https://github.com/llvm/llvm-project/commit/44ebda796ec9b6a43d5bef01efe58c0c67b8c971
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
Log Message:
-----------
[SLP][NFC]Add a test with the overoptimistic vectorization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223523
Commit: eb13b3f197bd2537160cc29aa56495a1117ba64e
https://github.com/llvm/llvm-project/commit/eb13b3f197bd2537160cc29aa56495a1117ba64e
Author: Florian Mayer <fmayer at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
Log Message:
-----------
[SelectionDAG] [NFC] fix inaccurate docstring (#223515)
`getNode` calls FoldBUILD_VECTOR, which simplifies all-POSION or
all-UNDEF vectors.
Commit: 020e9fe44ac8887bb3891511b801111bdf1ab6ae
https://github.com/llvm/llvm-project/commit/020e9fe44ac8887bb3891511b801111bdf1ab6ae
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
Log Message:
-----------
[SLP]Loop-scale the extract cost in the splat subtree keep/drop check
The unscaled extract estimate kept extract-heavy subtrees in hot loops,
rejecting profitable trees.
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223524
Commit: e5d9e4d7d3208dd2450f185d30c383a1806383b8
https://github.com/llvm/llvm-project/commit/e5d9e4d7d3208dd2450f185d30c383a1806383b8
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/stack-protector-guard.c
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
A llvm/test/CodeGen/PowerPC/target-abi-module-flag.ll
Log Message:
-----------
PPC: Read the ELF ABI from the "target-abi" module flag (#221669)
Resolve the ELFv2 ABI from the effective ABI name module flag,
rather than strictly relying on the -target-abi flag.
Also start emitting "target-abi" for PPC from clang.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 737462135d1c9c854484e2fac4eade107cf3b7fa
https://github.com/llvm/llvm-project/commit/737462135d1c9c854484e2fac4eade107cf3b7fa
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp-gfx1170.mlir
A mlir/test/Conversion/AMDGPUToROCDL/lds-barrier-gfx90c.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
Log Message:
-----------
[mlir][AMDGPU][NFC] Pre-commit tests for incorrect version checks (#220104)
There'll be a refactoring from `amdgpu::Chipset` to
`ROCDL::TargetInfo`, thus also moving from chip version checks to
features checks. This commit adds tests for incorrect lowerings that
were allowed by the current code.
- gfx90c is >= gfx90a but stil needs atomic emulation (it doesn't
have buffer fmax and so on).
- gfx90c is also >= gfx90a but has no barrier back-off, so it needs
the inline asm workaround around `s_barrier` that it isn't getting
- gfx908 doesn't have a packed fp16 atomic add but we thought it did
- gfx950 is mistakenly allowing xf32 MFMAs
- gfx1200 is allowing permlane_swap instructions that it doesn't have
- gfx11.7 should be allowing OCP FP8 conversions but isn't on the list
This also cleans up some redundant tests with a --check-prefixes
AI disclosure: Claude found these and wrote the tests.
---------
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 3b479f9529d605b3c05337a62fae04bd4f7e0495
https://github.com/llvm/llvm-project/commit/3b479f9529d605b3c05337a62fae04bd4f7e0495
Author: Susan Tan (ス-ザン タン) <zujunt at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Options/FlangOptions.td
M flang/docs/OpenACC-extensions.md
M flang/include/flang/Lower/LoweringOptions.def
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Lower/OpenACC.cpp
A flang/test/Lower/OpenACC/acc-combined-loop-firstprivate-flag.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
Log Message:
-----------
[flang][openacc] Attach firstprivate scalar onto combined parallel loop (#222777)
Combined `parallel loop firstprivate` currently puts firstprivate only
on `acc.parallel`, the compute region. Independent iterations then share
that one copy when v is updated. Attach also an implicit loop
firstprivate whose varPtr is the remapped compute copy.
Attach only when: 1) the loop is combined parallel loop, 2) and
independent (the default; not seq/auto), and 3) the firstprivate is an
OpenACC scalar. Arrays, sections, derived/character/boxed types, serial
loop, and non-combined parallel+loop stay compute-only.
Commit: 2b680eecc9f7fad9fee351219aa3c45320f609ea
https://github.com/llvm/llvm-project/commit/2b680eecc9f7fad9fee351219aa3c45320f609ea
Author: Bruno De Fraine <bruno.defraine at globalfoundries.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/RegionInfo.h
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/RegionInfo.cpp
Log Message:
-----------
[Analysis] Fix GCC warnings on ABI annotations (#222286)
The GCC build is cluttered by type attribute warnings on some header
files:
```
llvm/include/llvm/Analysis/RegionInfo.h:898:41: warning: type attributes ignored after type is already defined [-Wattributes]
898 | extern template class LLVM_TEMPLATE_ABI RegionBase<RegionTraits<Function>>;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```
The type attributes originate from PR #199019. The warnings occur
because the
specific template instantiation is triggered implicitly earlier, without
the
type attribute. This can be fixed by placing the extern template
declaration
before the implicit use.
Also, the implementation files were using `LLVM_TEMPLATE_ABI` instead of
`LLVM_EXPORT_TEMPLATE`, contrary to the guidance in
`llvm/docs/InterfaceExportAnnotations.rst` ("Explicitly Instantiated
Template
Classes"). This would trigger the same type of GCC warning in the
implementation file.
Commit: 84ee9b56ba3947cacd3aff40c6dce622cc1bff6b
https://github.com/llvm/llvm-project/commit/84ee9b56ba3947cacd3aff40c6dce622cc1bff6b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
Log Message:
-----------
[VPlan] Bail out on chained reductions in handleMaxMinNumReductions. (#223521)
handleMaxMinNumReductions does not support reduction chains, as the NaN
check directly checks the operand of the single min/max reduction.
Bail out for now to fix a crash.
Fixes https://github.com/llvm/llvm-project/issues/223430.
Commit: 3f83cc8881839fa7b7a6f8ec37c5cba2e687855d
https://github.com/llvm/llvm-project/commit/3f83cc8881839fa7b7a6f8ec37c5cba2e687855d
Author: vporpo <vasileios.porpodas at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
Log Message:
-----------
Reapply "[SandboxVec][VecUtils][NFC] BndlRef helper class" (#223483) (#223487)
This reverts commit 1d073217b664263f62ff01db623ed7542fde6fda.
Commit: 3377fbdd341a30c57c7a5e3ff11aeb21f9d2e6d4
https://github.com/llvm/llvm-project/commit/3377fbdd341a30c57c7a5e3ff11aeb21f9d2e6d4
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineBasicBlock.cpp
A llvm/test/CodeGen/WebAssembly/splitcriticaledge-physreg-liveness.mir
Log Message:
-----------
CodeGen: Clear physreg ranges after SplitCriticalEdge (#223172)
After critical edge spliting replaces a terminator, clear referenced
physreg ranges. The block's terminators may be replaced, and may
reference physical registers (e.g. WebAssebly's ARGUMENTS. When
LiveIntervals is available, repairIntervalsInRange only repairs virtual
registers, so the tracked physreg units were stale.
It feels like a bug that repairIntervalsInRange doesn't touch physregs,
but I've left that for a future change.
Co-Authored-By: Claude claude-opus-4.8 <noreply at anthropic.com>
Commit: 4698a5193eccf41f2f81bdb4c1004b1e05811d95
https://github.com/llvm/llvm-project/commit/4698a5193eccf41f2f81bdb4c1004b1e05811d95
Author: Gheorghe-Teodor Bercea <doru.bercea at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/lib/BinaryFormat/Dwarf.cpp
A llvm/test/tools/llvm-dwarfdump/AMDGPU/DW_AT_LLVM_memory_space.yaml
Log Message:
-----------
[DWARF] Add DW_MSPACE_LLVM_* memory space encodings (#220766)
DW_AT_LLVM_memory_space is already defined in Dwarf.def, and the memory
space encodings it takes are already specified in
docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst, but the values
had no names in the source, so llvm-dwarfdump printed the attribute as a
bare integer.
Add the encodings via a HANDLE_DW_MSPACE macro alongside the existing
HANDLE_DW_ASPACE, define the MemorySpace enum, and add MemorySpaceString
and getMemorySpace. AttributeValueString then resolves the attribute, so
no changes are needed in the DWARF consumers themselves.
Unlike address spaces, memory space encodings are target-independent, so
MemorySpaceString takes no triple.
Commit: 2e5fa3ac6919234d90c99a5ae943cac85a2ea727
https://github.com/llvm/llvm-project/commit/2e5fa3ac6919234d90c99a5ae943cac85a2ea727
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx9.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN fmed3 builtins (#223101)
Adds codegen for the following AMDGCN fmed3 builtins:
- __builtin_amdgcn_fmed3f (float)
- __builtin_amdgcn_fmed3h (half)
These are lowered to the corresponding `llvm.amdgcn.fmed3` intrinsic.
Commit: 8f887e33d2b18328885716bcbdc568680335f43e
https://github.com/llvm/llvm-project/commit/8f887e33d2b18328885716bcbdc568680335f43e
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Builtins.td
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
A clang/test/SemaHLSL/BuiltIns/resource_gather-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/resource_load-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/resource_sample-errors.hlsl
Log Message:
-----------
[HLSL] Add CustomTypeChecking and improve sema for texture builtins (#221060)
This PR makes the texture builtins (for load, sample, gather) use
CustomTypeChecking, and adds additional semantic checks for them to make
them more strict and conform with the way sema checks are done for other
builtins.
The main benefit of CustomTypeChecking is preventing
DefaultArgumentPromotion from occurring due to the builtins being
declared `void(...)`; primarily, the promotion of float/half to double
is undesirable.
Floating-point scalar operands in codegen (`CGHLSLBuiltins.cpp`) for
these builtins always had a check and cast of the form `if
(Op->getType() != FloatTy) Op = CreateFPCast(Op, FloatTy);` to
compensate for that, which looked like a code smell to me.
The DefaultArgumentPromotion also affected diagnostics, which would
report the promoted type (double) instead of the type the user provided
(float) (e.g., https://hlsl.godbolt.org/z/Yec3dKh14). These diagnostics
were not exercised before, and this PR adds tests to exercise them.
Sema checks for the texture builtin args have also been made more strict
and rewritten to be like sema for other builtins, using
`CheckArgTypeMatches` rather than only checking vector element count.
Finally, in preparation for 1D texture types, the sema for texture
builtins now allow scalar args where it is relevant.
Assisted by: Claude Opus 5
---
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Commit: 3bb668718fc42be84ae4165d947d1de99a3c179b
https://github.com/llvm/llvm-project/commit/3bb668718fc42be84ae4165d947d1de99a3c179b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
A clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c
M clang/test/Driver/lto-aix.c
M flang/include/flang/Frontend/TargetOptions.h
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
A flang/test/Integration/PowerPC/aix-vec-extabi.f90
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll
M llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll
M llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll
M llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
M llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll
M llvm/test/CodeGen/PowerPC/aix-insert-extract.ll
M llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
M llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-stack.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
M llvm/test/CodeGen/PowerPC/bswap64.ll
M llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll
M llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll
M llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll
M llvm/test/CodeGen/PowerPC/cmpb.ll
M llvm/test/CodeGen/PowerPC/constants-i64.ll
M llvm/test/CodeGen/PowerPC/fdiv.ll
M llvm/test/CodeGen/PowerPC/fma-assoc.ll
M llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
M llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
M llvm/test/CodeGen/PowerPC/maddld.ll
M llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll
M llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
M llvm/test/CodeGen/PowerPC/mulli.ll
M llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll
M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
M llvm/test/CodeGen/PowerPC/pr33093.ll
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
M llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
M llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll
M llvm/test/CodeGen/PowerPC/vec-bswap.ll
M llvm/test/CodeGen/PowerPC/vec_clz.ll
M llvm/test/CodeGen/PowerPC/vec_constants.ll
M llvm/test/CodeGen/PowerPC/vec_revb.ll
M llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
M llvm/test/CodeGen/PowerPC/vmladduhm.ll
M llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
M llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll
Log Message:
-----------
PPC: Replace EnableAIXExtendedAltivecABI with "target-abi" module flag (#221670)
Continue purging ABI-influencing TargetOptions fields. Eliminate this
case by migrating to a module flag, reusing the generic target-abi module
flag with a new value.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: c5086962da8f36f69ad04ed81fce5aa2f19cec66
https://github.com/llvm/llvm-project/commit/c5086962da8f36f69ad04ed81fce5aa2f19cec66
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M clang/lib/Interpreter/Value.cpp
Log Message:
-----------
[clang-repl] Use ExecutorAddr::toPtr to get function ptr (#223395)
Fixes the pretty-print.cpp testcase on Darwin/arm64e.
This testcase was crashing on Darwin/arm64e when it tried to call a
value's destructor via an unauthenticated pointer.
Fix the issue by updating Value::Value to use ExecutorAddr::toPtr to get
an authenticated pointer to the destructor (rather than using
ExecutorAddr::getValue, which yields a raw address with no
authentication bits)
Commit: b80623b0255ae13c2d8337ea96d1bf2c673ea3c8
https://github.com/llvm/llvm-project/commit/b80623b0255ae13c2d8337ea96d1bf2c673ea3c8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions-vs-first-order-recurrences.ll
Log Message:
-----------
[LV] Add more tests with phis that could be FORs or predicated IVS (NFC) (#223539)
Extend test coverage with more cases where a phi can be both a FOR and a
predicated IV.
Test coverage for https://github.com/llvm/llvm-project/pull/201208.
Commit: d6ae821f93ca35b8d2d67d4ce9f7391c7e2fe9fc
https://github.com/llvm/llvm-project/commit/d6ae821f93ca35b8d2d67d4ce9f7391c7e2fe9fc
Author: Michael Jones <michaelrj at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/src/sys/sendfile/linux/sendfile.cpp
M libc/test/src/sys/sendfile/CMakeLists.txt
M libc/test/src/sys/sendfile/sendfile_test.cpp
Log Message:
-----------
[libc] Fix sendfile argument order (#223059)
The previous implementation had the arguments swapped. This PR fixes it
and also adds a test to ensure we don't regress.
Commit: 060aa57d39e12fd3b91113197d6ed78cf998158a
https://github.com/llvm/llvm-project/commit/060aa57d39e12fd3b91113197d6ed78cf998158a
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M clang/test/Interpreter/simple-exception.cpp
M clang/test/lit.cfg.py
Log Message:
-----------
[clang-repl] XFAIL simple-exception test on Darwin/arm64e (#223401)
ORC doesn't support unwinding on arm46e yet.
Commit: 66971239af0417693927880df128d01b89491171
https://github.com/llvm/llvm-project/commit/66971239af0417693927880df128d01b89491171
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M clang/unittests/Interpreter/InterpreterTest.cpp
Log Message:
-----------
[clang-repl] Fix FindMangledNameSymbol test on Darwin/arm64e (#223410)
Fix the FindMangledNameSymbol unit test by comparing values as
llvm::orc::ExecutorAddrs.
This test was using comparing a pointer cast to uintptr_t and the result
of an ExecutorAddr::getValue call, but those can be different on
Darwin/arm64e due to pointer authentication. Comparing as ExecutorAddr
values eliminates this difference (pointer authentication bits are
stripped from both sides).
Commit: 46e24dbc4475f42c0f8a6b4e0ccb7e57ea3d1cde
https://github.com/llvm/llvm-project/commit/46e24dbc4475f42c0f8a6b4e0ccb7e57ea3d1cde
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/InferAddressSpaces.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/X86/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/fake-use.ll
M llvm/test/Transforms/InferAddressSpaces/infer-address-spaces-overlapping-dead.ll
M llvm/test/Transforms/InferAddressSpaces/masked-gather-scatter.ll
M llvm/test/Transforms/InferAddressSpaces/optnone-func-unchanged.ll
A llvm/test/Transforms/InferAddressSpaces/pass-param-parse-errors.ll
M llvm/test/Transforms/InferAddressSpaces/vector-of-pointers.ll
Log Message:
-----------
InferAddressSpaces: Replace -assume-default-is-flat-addrspace cl::opt with pass parameter (#223480)
Migrate the pass-specific command-line option to a new pass manager
pass parameter, exposed as
infer-address-spaces<assume-default-is-flat-addrspace>.
Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>
Commit: a5815099928aa1aa95bfe93201bc8c0b864fa10c
https://github.com/llvm/llvm-project/commit/a5815099928aa1aa95bfe93201bc8c0b864fa10c
Author: David Green <david.green at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
Log Message:
-----------
[AArch64] Add test coverage for constant mask and extract of a vector store. NFC (#223552)
Commit: 6fb04b665761e3dc99264b040ecd4781a49afd32
https://github.com/llvm/llvm-project/commit/6fb04b665761e3dc99264b040ecd4781a49afd32
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
Log Message:
-----------
[RISCV] Add SRLI+PACK pattern for (or (and rs1, 0xffffffff), (and rs2, 0xffffffff00000000)). (#223507)
Fixes #223455.
Commit: da8d3b78f6865ef6ce893f1690b9151851a43aed
https://github.com/llvm/llvm-project/commit/da8d3b78f6865ef6ce893f1690b9151851a43aed
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/test/AST/HLSL/Textures-AST.hlsl
M clang/test/AST/HLSL/Textures-scalar-AST.hlsl
M clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
M clang/test/AST/HLSL/Textures-vector-AST.hlsl
M clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
M clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
M clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
M clang/test/CodeGenHLSL/resources/Textures-default.hlsl
M clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
M clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
M clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
M clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
M clang/test/SemaHLSL/Resources/Textures-declaration-order.hlsl
M clang/test/SemaHLSL/Resources/Textures-mips-errors.hlsl
M clang/test/SemaHLSL/Resources/Textures-unsupported-methods-errors.hlsl
Log Message:
-----------
[HLSL] Implement Texture1D and its variants (#221061)
Fixes https://github.com/llvm/llvm-project/issues/194738
Fixes https://github.com/llvm/llvm-project/issues/194741
Fixes https://github.com/llvm/llvm-project/issues/194943
Fixes https://github.com/llvm/llvm-project/issues/194945
This PR implements the Texture1D type and its variants: RWTexture1D,
Texture1DArray, and RWTexture1DArray.
It also implements the codegen for the texture builtins so that they can
handle scalars where they otherwise always assumed a vector before the
existence of 1D textures.
Assisted by: Claude Opus 5
---
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Commit: 4ae3c053973d611ba106b060ae4b1dd8cacba0ef
https://github.com/llvm/llvm-project/commit/4ae3c053973d611ba106b060ae4b1dd8cacba0ef
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx950.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN bitop3 builtins (#223104)
Adds codegen for the following AMDGCN bitop3 builtins:
- __builtin_amdgcn_bitop3_b32
- __builtin_amdgcn_bitop3_b16
These are lowered to the corresponding `llvm.amdgcn.bitop3` intrinsic.
Commit: 87afb37e3f032af3107dbda6bc0da53460f0407f
https://github.com/llvm/llvm-project/commit/87afb37e3f032af3107dbda6bc0da53460f0407f
Author: Abhay Kanhere <a_kanhere at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/trip-count-stride-positive-from-guard.ll
A llvm/test/Transforms/IndVarSimplify/exit-value-guarded-positive-stride.ll
Log Message:
-----------
[ScalarEvolution] howManyLessThans infer stride isPositive from guard (#214014)
Infer Stride is positive from loop guard.
This enables SCEV to compute symbolic-max backedge-taken count for
multi-exit loops.
Motivating example:
void example(int *p, int n, int stride, int bound) {
if (stride <= 0) __builtin_trap(); // dominating guard => stride > 0
for (int i = 0; i < n; i += stride) {
if (i > bound) __builtin_trap(); // per-iteration bounds check (2nd
exit)
p[i] = 0;
}
}
Commit: a636e928c1d63c7eabe140832446f22e360ae001
https://github.com/llvm/llvm-project/commit/a636e928c1d63c7eabe140832446f22e360ae001
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Teach RISCVOptWInstrs that zext.w is fixable to sext.w. (#223559)
Note, in some cases erasing the zext.w and fixing an earlier
instruction would be even better but that requires more extensive
changes.
Commit: 52b2e03278f103f5baaa14a43bd9be380301de94
https://github.com/llvm/llvm-project/commit/52b2e03278f103f5baaa14a43bd9be380301de94
Author: David Dada <davidtofunmidada at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/src/__support/File/file.cpp
M libc/src/__support/File/file.h
A libc/src/__support/File/file_mode.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/File/linux/file.h
A libc/src/__support/File/linux/file_flags.h
M libc/src/stdio/fmemopen.cpp
M libc/src/stdio/fopencookie.cpp
M libc/src/stdio/linux/stderr.cpp
M libc/src/stdio/linux/stdin.cpp
M libc/src/stdio/linux/stdout.cpp
M libc/test/src/__support/File/CMakeLists.txt
A libc/test/src/__support/File/file_mode_test.cpp
M libc/test/src/__support/File/file_test.cpp
Log Message:
-----------
[libc] feat(filemode): implement class and helper functions to handle file modes for an opened file (#220906)
I moved the logic from `mode_flags` function to the `FileMode`
constructor.
The `FileMode` class has several helper methods to work with modes which
can then be called in `File` class.
Issue: #213374
---------
Signed-off-by: tdadadavid <davidtofunmidada at gmail.com>
Co-authored-by: Michael Jones <michaelrj at google.com>
Commit: 37d9648ca786af803a4921aadbf842c7e12ec7f8
https://github.com/llvm/llvm-project/commit/37d9648ca786af803a4921aadbf842c7e12ec7f8
Author: Florian Mayer <fmayer at google.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
Log Message:
-----------
[NFC] [SelectionDAG] fix typo in comment (#223560)
Commit: 35d553bdd51c01effb0f7c4c161a77cc88b6b7a0
https://github.com/llvm/llvm-project/commit/35d553bdd51c01effb0f7c4c161a77cc88b6b7a0
Author: forking-google-bazel-bot[bot] <265904573+forking-google-bazel-bot[bot]@users.noreply.github.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[Bazel] Fixes 52b2e03 (#223567)
This fixes 52b2e03278f103f5baaa14a43bd9be380301de94 (#220906).
Buildkite error link:
https://buildkite.com/llvm-project/upstream-bazel/builds?commit=52b2e03278f103f5baaa14a43bd9be380301de94
Co-authored-by: Google Bazel Bot <google-bazel-bot at google.com>
Commit: 5cc8a513b417ab7dd791b78863e2f5f834f818d8
https://github.com/llvm/llvm-project/commit/5cc8a513b417ab7dd791b78863e2f5f834f818d8
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/test/CIR/CodeGen/forward-decls.cpp
Log Message:
-----------
[CIR] Fix 'isConstant' calc when looking at an incomplete type (#223444)
This popped up in a benchmark. Classic codegen ALWAYS sets this as
'excludeCtor'/'excludeDtor', but CIR tried 'harder' to get this right.
However, with an incomplete type, we can't actually look into it to see
if it has any mutable members, so determining 'constness' isn't
possible.
We could PROBABLY do better with enums since I would assume they can be
constant most of the time, but we fall-back to classic-codegen's
behavior here instead: which marks it as non-const.
Thanks to 'trying harder' than classic codegen as mentioned above, there
IS a slight LLVM-IR difference, but for the better.
Also note: Claude helped me with the tests.
Commit: 86dfc32f0defb728cf3cdabc346fa5e4939eae9e
https://github.com/llvm/llvm-project/commit/86dfc32f0defb728cf3cdabc346fa5e4939eae9e
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/test/CIR/CodeGen/atomic-libcall.c
Log Message:
-----------
[CIR] Atomic compare-and-exchange via libcall (#206073)
This patch adds support for atomic compare-and-exchange operations via libcall.
Assisted-by: Codex / gpt-5.5 xhigh
Commit: 45c113d869c69ccf17b368e087c744713cf26bfa
https://github.com/llvm/llvm-project/commit/45c113d869c69ccf17b368e087c744713cf26bfa
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
Log Message:
-----------
[BOLT][AArch64] Make Android instrumentation runtime fail safe (#223110)
Profiling failure in BOLT instrumentation runtime should not kill the
host app on Android. Under `ANDROID_AARCH64`, we now handle failures
in instrumentation setup, memory allocation, hash table operations,
data dumping, opening profile output file, zero-counter binary, etc..
Since the first failure, we will disable profiling and directly return
from various instrumentation entry points, instead of assert/exit.
Only for Android AArch64; the behavior is unchanged otherwise.
Commit: 0d91c104dde79e5f4467c90cf109d16aabe45c99
https://github.com/llvm/llvm-project/commit/0d91c104dde79e5f4467c90cf109d16aabe45c99
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
Log Message:
-----------
[lldb] Fix use-after-free in jThreadsInfo stop info cache (#223488)
WillPublicStop iterates over the array borrowed from m_jthreadsinfo_sp
while WillResume concurrently resets the pointer on another thread,
freeing the array during the walk.
Protect the cached stop info with a mutex and copy the shared pointer
out before processing. Also modernize m_shared_cache_info to Guarded.
rdar://186776438
Commit: d6b0c1b9a79d5fdd3d6f94ae36adb266930bd68e
https://github.com/llvm/llvm-project/commit/d6b0c1b9a79d5fdd3d6f94ae36adb266930bd68e
Author: Jinjie Huang <huangjinjie at bytedance.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/test/AArch64/validate-branch-target.s
M bolt/test/X86/validate-branch-target.s
Log Message:
-----------
[BOLT] Prevent missing ExternalBranch validation (#221927)
#165406 introduced validation to check whether a branch target is a
valid instruction to detect corrupted CFGs. However, as described in
[165406#discussion](https://github.com/llvm/llvm-project/pull/165406#discussion_r2601459105),
it can miss validations when a function contains multiple invalid
ExternalBranches.
Therefore, this patch introduces a branch-level set to prevent duplicate
validations while ensuring no branches are missed.
Commit: 40ab38adced10d38446b8fe0912e2039436f5adb
https://github.com/llvm/llvm-project/commit/40ab38adced10d38446b8fe0912e2039436f5adb
Author: Haowei <haowei at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Driver/modules-driver-depscan-log.cpp
Log Message:
-----------
Use -fsyntax-only for modules-driver-depscan-log.cpp test (#223014)
The modules-driver-depscan-log.cpp is failing after PR#222209 was landed
on mac when building LLVM with libcxx. This patch changed the `-o` flag
to `-fsyntax-only` to mitigate this issue.
Commit: 61a8c98594dbce9e09f39614b89cb74e563bcbbc
https://github.com/llvm/llvm-project/commit/61a8c98594dbce9e09f39614b89cb74e563bcbbc
Author: Chinmay Deshpande <chdeshpa at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AMDGPU] Fix maximum physical LDS reporting for gfx6 (#223185)
Reference:
https://docs.amd.com/api/khub/documents/VeItSxvoJNzy28rl~JwEAQ/content#page=77
> “The maximum LDS allocation size for a work-group is still 32 kB,
however each compute unit has a total of 64 kB of LDS.”
Reference:
https://docs.amd.com/api/khub/documents/J4foK5jvufN9rTHf_DlCPw/content#page=22
> “Each compute unit has a 64 kB of Local Data Share (LDS) memory
space…”
> “Each workgroup can allocate up to 32 kB of this space, and can read
and write any portion of the LDS space allocated to it.”
Commit: 7e8ce3bd5b7460685e060a3b86d054cfdc22f2bf
https://github.com/llvm/llvm-project/commit/7e8ce3bd5b7460685e060a3b86d054cfdc22f2bf
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/JSON/ObjectFileJSON.cpp
M lldb/test/API/functionalities/json/object-file/TestObjectFileJSON.py
Log Message:
-----------
[lldb] Bound JSON object file text by buffer size (#223575)
ObjectFileJSON created a StringRef from a bare pointer without a length.
Mapped buffers lack a NULL terminator, causing strlen to read past
page-aligned mappings.
Pass the buffer size and stop at the first NULL to handle unterminated
mappings and zero-padded probe reads.
rdar://186899370
Commit: 95ecc0a5736632f9cea75ad445a537979d3fc429
https://github.com/llvm/llvm-project/commit/95ecc0a5736632f9cea75ad445a537979d3fc429
Author: Stan Ulbrych <stan at python.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
A compiler-rt/test/fuzzer/MinimizeCrashCustomMutatorTest.cpp
A compiler-rt/test/fuzzer/minimize_crash_custom_mutator.test
Log Message:
-----------
[libFuzzer] Add test for stale size passed to Mutate in MinimizeCrashLoop (#223502)
Add tests for the fix in #223470.
Commit: 3493720eca95cf844a8d7e58fdd12e0e5644e7d0
https://github.com/llvm/llvm-project/commit/3493720eca95cf844a8d7e58fdd12e0e5644e7d0
Author: Ryunosuke (Rick) Yanashita <ryunosukeyanashita at gmail.com>
Date: 2026-09-15 (Tue, 15 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/trunc.ll
Log Message:
-----------
[InstCombine] Add fold combining adjacent extracted bit fields to restore optimization for separate truncations (#219598)
This restores the InstCombine optimization that was lost (regression)
starting from Clang 14, when assembling adjacent bit fields extracted
from a wider integer.
The fold combines:
```
(trunc (lshr X, S) & M0) | (lshr (trunc X), S & M1) --> (trunc (lshr X, S) & (C0 | C1))
```
The fold handles both orderings. I implemented tests for this fold in
trunc.ll
alive2 proof: https://alive2.llvm.org/ce/z/rPQN4D
Fixes #215254
Commit: fc07c0d0715abe84c59696369f69c4a443875937
https://github.com/llvm/llvm-project/commit/fc07c0d0715abe84c59696369f69c4a443875937
Author: Ryunosuke (Rick) Yanashita <ryunosukeyanashita at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Core/BinaryFunction.h
M bolt/lib/Core/BinaryContext.cpp
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/test/AArch64/validate-branch-target.s
A bolt/test/RISCV/relr.s
M bolt/test/X86/validate-branch-target.s
M bolt/unittests/Core/BinaryContext.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
M bolt/unittests/Profile/PerfScripts.cpp
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/clang-tidy/readability/FunctionCognitiveComplexityCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/readability/convert-member-functions-to-static.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/function-cognitive-complexity-alias.cpp
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/docs/ReleaseNotes.md
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/CodeGenOptions.h
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
M clang/include/clang/CIR/Dialect/IR/CIROps.td
M clang/include/clang/CIR/Dialect/IR/CIRTypes.td
M clang/include/clang/Driver/CommonArgs.h
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Options/FlangOptions.td
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/Basic/Targets/PPC.cpp
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
M clang/lib/CIR/Dialect/IR/CIRTypes.cpp
M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
M clang/lib/CIR/Dialect/Transforms/TargetLowering/CIRABIRewriteContext.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGHLSLBuiltins.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/Targets/DirectX.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/FreeBSD.cpp
M clang/lib/Driver/ToolChains/Fuchsia.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Haiku.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/NetBSD.cpp
M clang/lib/Driver/ToolChains/OpenBSD.cpp
M clang/lib/Driver/ToolChains/Solaris.cpp
M clang/lib/Driver/ToolChains/UEFI.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Frontend/CompilerInvocation.cpp
M clang/lib/Frontend/TextDiagnostic.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Interpreter/IncrementalExecutor.cpp
M clang/lib/Interpreter/Value.cpp
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
M clang/lib/Sema/HLSLExternalSemaSource.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaHLSL.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/AST/ByteCode/cxx11.cpp
M clang/test/AST/HLSL/Textures-AST.hlsl
M clang/test/AST/HLSL/Textures-scalar-AST.hlsl
M clang/test/AST/HLSL/Textures-shorthand-AST.hlsl
M clang/test/AST/HLSL/Textures-vector-AST.hlsl
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
A clang/test/Analysis/explicit-lambda-capture.cpp
M clang/test/C/C23/n2508.c
M clang/test/C/C2y/n3259.c
M clang/test/C/C2y/n3260.c
M clang/test/C/C2y/n3273.c
M clang/test/C/C2y/n3298.c
M clang/test/C/C2y/n3353.c
M clang/test/C/C2y/n3409.c
M clang/test/CIR/CodeGen/atomic-libcall.c
M clang/test/CIR/CodeGen/bitint-split-storage-nyi.c
M clang/test/CIR/CodeGen/bitint.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-bitint.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-sret-res-attrs.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.c
A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-union-bitfield.cpp
M clang/test/CIR/CodeGen/forward-decls.cpp
M clang/test/CIR/CodeGen/pointer-to-data-member.cpp
M clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
M clang/test/CIR/CodeGenBuiltins/builtin-bit.cpp
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx9.hip
A clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx950.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
A clang/test/CIR/CodeGenOpenCL/version.cl
A clang/test/CIR/IR/invalid-version.cir
A clang/test/CIR/IR/version.cir
A clang/test/CIR/Lowering/opencl-version-metadata.cir
A clang/test/CIR/Transforms/abi-lowering/dropped-return-res-attrs.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-aggregate-nyi.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-int-nyi.cir
M clang/test/CIR/Transforms/abi-lowering/x86_64-union.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/sve/dup.c
A clang/test/CodeGen/PowerPC/aix-vec-extabi-module-flag.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M clang/test/CodeGen/WebAssembly/wasm-exception-model-flag-parse-ir-input.ll
M clang/test/CodeGen/ms-setjmp.c
M clang/test/CodeGen/stack-protector-guard.c
A clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCUDASPIRV/kernel-cc.cu
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
M clang/test/CodeGenHIP/hipspv-kernel.cpp
M clang/test/CodeGenHLSL/resources/Textures-CalculateLevelOfDetail.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Gather.hlsl
M clang/test/CodeGenHLSL/resources/Textures-GetDimensions.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Load.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Mips.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Sample.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleBias.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmp.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleCmpLevelZero.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleGrad.hlsl
M clang/test/CodeGenHLSL/resources/Textures-SampleLevel.hlsl
M clang/test/CodeGenHLSL/resources/Textures-Subscript.hlsl
M clang/test/CodeGenHLSL/resources/Textures-default-explicit-binding.hlsl
M clang/test/CodeGenHLSL/resources/Textures-default.hlsl
M clang/test/CodeGenHLSL/resources/Textures-shorthand-contexts.hlsl
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/amdgpu-amd-amdhsa/libclang_rt.ubsan_standalone.a
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/x86_64-unknown-linux-gnu/libclang_rt.ubsan_offload.a
A clang/test/Driver/Inputs/resource_dir_with_amdgpu_per_target_subdir/lib/x86_64-unknown-linux-gnu/libclang_rt.ubsan_standalone.a
A clang/test/Driver/fsanitize-undefined-offload.c
M clang/test/Driver/ir-exception-model.c
M clang/test/Driver/lto-aix.c
M clang/test/Driver/mingw.cpp
M clang/test/Driver/modules-driver-depscan-log.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/sparc-as.c
M clang/test/Driver/wasm-toolchain.c
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Interpreter/simple-exception.cpp
M clang/test/Lexer/cxx2c-raw-strings.cpp
M clang/test/Lexer/hexfloat.cpp
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M clang/test/Misc/warning-flags.c
M clang/test/OffloadTools/clang-nvlink-wrapper/nvlink-wrapper.c
A clang/test/PCH/flag-enum.c
M clang/test/Parser/cxx-extra-semi.cpp
M clang/test/Parser/cxx2c-delete-with-message.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/c2x-attr.c
M clang/test/Sema/fixed-enum.c
M clang/test/Sema/for.c
M clang/test/Sema/pre-c2x-restrict-qualifier.c
M clang/test/SemaCXX/blocks.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/cxx98-compat-pedantic.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/enum.cpp
M clang/test/SemaCXX/ms-ctor-closure.cpp
M clang/test/SemaCXX/reinterpret-fn-obj-pedantic.cpp
A clang/test/SemaHIP/atomic-init.hip
A clang/test/SemaHLSL/BuiltIns/resource_gather-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/resource_load-errors.hlsl
A clang/test/SemaHLSL/BuiltIns/resource_sample-errors.hlsl
M clang/test/SemaHLSL/Resources/Textures-CalculateLevelOfDetail.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleBias.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmp.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleCmpLevelZero.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleGrad.hlsl
M clang/test/SemaHLSL/Resources/Textures-SampleLevel.hlsl
M clang/test/SemaHLSL/Resources/Textures-Sema.hlsl
M clang/test/SemaHLSL/Resources/Textures-Subscript.hlsl
M clang/test/SemaHLSL/Resources/Textures-declaration-order.hlsl
M clang/test/SemaHLSL/Resources/Textures-mips-errors.hlsl
M clang/test/SemaHLSL/Resources/Textures-unsupported-methods-errors.hlsl
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/test/lit.cfg.py
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M clang/unittests/Interpreter/InterpreterTest.cpp
M compiler-rt/cmake/caches/AMDGPU.cmake
M compiler-rt/cmake/config-ix.cmake
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer.h
M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_libcdep.cpp
M compiler-rt/lib/ubsan/CMakeLists.txt
A compiler-rt/lib/ubsan/offload/CMakeLists.txt
A compiler-rt/lib/ubsan/offload/hsa.h
A compiler-rt/lib/ubsan/offload/ubsan_offload.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_hsa_interceptors.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_report.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_rpc.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_rpc.h
A compiler-rt/lib/ubsan/offload/ubsan_offload_symbolize.cpp
A compiler-rt/lib/ubsan/offload/ubsan_offload_symbolize.h
M compiler-rt/lib/ubsan/ubsan_diag.cpp
M compiler-rt/lib/ubsan/ubsan_diag.h
M compiler-rt/lib/ubsan/ubsan_handlers.cpp
A compiler-rt/lib/ubsan/ubsan_handlers_internal.h
M compiler-rt/lib/ubsan/ubsan_interface.inc
A compiler-rt/lib/ubsan/ubsan_offload.cpp
A compiler-rt/lib/ubsan/ubsan_offload_checks.inc
A compiler-rt/lib/ubsan/ubsan_offload_packet.h
M compiler-rt/lib/ubsan/ubsan_value.h
M compiler-rt/test/CMakeLists.txt
A compiler-rt/test/fuzzer/MinimizeCrashCustomMutatorTest.cpp
A compiler-rt/test/fuzzer/minimize_crash_custom_mutator.test
A compiler-rt/test/ubsan/AMDGPU/abort.hip
A compiler-rt/test/ubsan/AMDGPU/dedup.hip
A compiler-rt/test/ubsan/AMDGPU/host-and-device.hip
A compiler-rt/test/ubsan/AMDGPU/lit.local.cfg.py
A compiler-rt/test/ubsan/AMDGPU/openmp-overflow.cpp
A compiler-rt/test/ubsan/AMDGPU/overflow-i128.hip
A compiler-rt/test/ubsan/AMDGPU/overflow.hip
A compiler-rt/test/ubsan/AMDGPU/shift.hip
M compiler-rt/test/ubsan/CMakeLists.txt
A compiler-rt/test/ubsan/Inputs/hip.h
M compiler-rt/test/ubsan/lit.common.cfg.py
M compiler-rt/test/ubsan/lit.site.cfg.py.in
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang/docs/OpenACC-extensions.md
M flang/docs/OpenMP-declare-target.md
M flang/include/flang/Frontend/TargetOptions.h
M flang/include/flang/Lower/LoweringOptions.def
M flang/include/flang/Lower/OpenMP/Clauses.h
A flang/include/flang/Optimizer/Builder/Runtime/CUDA/Support.h
M flang/include/flang/Optimizer/CodeGen/CGPasses.td
M flang/include/flang/Optimizer/CodeGen/CodeGen.h
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.h
M flang/include/flang/Optimizer/Dialect/FIRCG/CGOps.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/include/flang/Optimizer/Support/AllocationPolicy.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Frontend/CompilerInstance.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
A flang/lib/Optimizer/Builder/Runtime/CUDA/Support.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp
M flang/lib/Optimizer/Dialect/FIRCG/CMakeLists.txt
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/lib/Optimizer/Passes/Pipelines.cpp
M flang/lib/Optimizer/Support/AllocationPolicy.cpp
M flang/lib/Optimizer/Transforms/AddDebugInfo.cpp
M flang/lib/Optimizer/Transforms/AllocationPlacement.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/lib/Optimizer/Transforms/StackArrays.cpp
M flang/lib/Parser/openmp-parsers.cpp
M flang/lib/Semantics/check-omp-loop.cpp
M flang/lib/Semantics/check-omp-structure.cpp
M flang/lib/Semantics/check-omp-variant.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
M flang/test/Driver/frame-pointer-forwarding.f90
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
A flang/test/Fir/convert-to-llvm-unsafe-fp-conversion.fir
M flang/test/Fir/declare-codegen.fir
M flang/test/Fir/mem2reg.mlir
M flang/test/HLFIR/simplify-hlfir-intrinsics-eoshift.fir
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
A flang/test/Integration/PowerPC/aix-vec-extabi.f90
M flang/test/Lower/CUDA/cuda-allocatable.cuf
A flang/test/Lower/CUDA/cuda-allocation-policy.cuf
M flang/test/Lower/CUDA/cuda-atomicadd.cuf
M flang/test/Lower/CUDA/cuda-cdevloc.cuf
M flang/test/Lower/CUDA/cuda-cluster.cuf
M flang/test/Lower/CUDA/cuda-device-proc.cuf
M flang/test/Lower/CUDA/cuda-mod.cuf
M flang/test/Lower/CUDA/cuda-module-use.cuf
M flang/test/Lower/CUDA/cuda-proc-attribute.cuf
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/CUDA/cuda-shared.cuf
M flang/test/Lower/CUDA/cuda-synchronization.cuf
A flang/test/Lower/OpenACC/acc-combined-loop-firstprivate-flag.f90
M flang/test/Lower/OpenACC/acc-declare-globals.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-allocatable-component.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived-user-assign.f90
M flang/test/Lower/OpenACC/acc-firstprivate-derived.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
A flang/test/Lower/OpenMP/omp-lib-integer-wrappers.f90
A flang/test/Lower/OpenMP/target-data-use-device-addr-descriptor.f90
M flang/test/Lower/module-parameter-linkonce-odr.f90
M flang/test/Semantics/OpenMP/clause-validity01.f90
M flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
M flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
M flang/test/Transforms/allocation-policy-precedence.fir
A flang/test/Transforms/debug-cuf-device-variable.fir
A flang/test/Transforms/function-attr-frame-pointer.fir
M flang/test/Transforms/licm.fir
A flang/test/Transforms/stack-arrays-policy-opt-out.fir
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/arm/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/cookie_io_functions_t.h
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/__support/FPUtil/float80.h
M libc/src/__support/File/file.cpp
M libc/src/__support/File/file.h
A libc/src/__support/File/file_mode.h
M libc/src/__support/File/linux/CMakeLists.txt
M libc/src/__support/File/linux/file.cpp
M libc/src/__support/File/linux/file.h
A libc/src/__support/File/linux/file_flags.h
M libc/src/__support/big_int.h
M libc/src/__support/macros/properties/cpu_features.h
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/src/__support/math_extras.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/src/stdio/fmemopen.cpp
M libc/src/stdio/fopencookie.cpp
M libc/src/stdio/linux/stderr.cpp
M libc/src/stdio/linux/stdin.cpp
M libc/src/stdio/linux/stdout.cpp
M libc/src/string/memory_utils/op_generic.h
M libc/src/sys/sendfile/linux/sendfile.cpp
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/execv.cpp
M libc/src/unistd/linux/execve.cpp
M libc/src/unistd/linux/sysconf.cpp
M libc/test/src/__support/File/CMakeLists.txt
A libc/test/src/__support/File/file_mode_test.cpp
M libc/test/src/__support/File/file_test.cpp
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/sys/mman/linux/CMakeLists.txt
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/msync_test.cpp
M libc/test/src/sys/mman/linux/remap_file_pages_test.cpp
M libc/test/src/sys/sendfile/CMakeLists.txt
M libc/test/src/sys/sendfile/sendfile_test.cpp
A libc/utils/mathtools/wc_to_bin.py
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
R libcxx/test/libcxx/diagnostics/unused_variables.compile.pass.cpp
R libcxx/test/libcxx/diagnostics/unused_variables.verify.cpp
A libcxx/test/libcxx/unused_variables.compile.pass.cpp
A libcxx/test/libcxx/unused_variables.verify.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
A libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.verify.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
M lld/ELF/Driver.cpp
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
M lld/MachO/SyntheticSections.cpp
M lld/test/ELF/driver.test
R lld/test/ELF/dynamic-list-cpp.s
M lld/test/ELF/dynamic-list-glob.s
R lld/test/ELF/early-exit-for-bad-paths.s
M lld/test/ELF/map-file.s
R lld/test/ELF/version-script-reassign-glob.s
A lld/test/ELF/version-script-wildcard-precedence.s
M lldb/bindings/interface/SBValueDocstrings.i
M lldb/include/lldb/API/SBExpressionOptions.h
M lldb/include/lldb/API/SBValue.h
M lldb/include/lldb/Core/DumpRegisterValue.h
M lldb/include/lldb/Host/SafeMachO.h
M lldb/include/lldb/Target/Memory.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/packages/Python/lldbsuite/test/configuration.py
M lldb/packages/Python/lldbsuite/test/dotest.py
M lldb/source/API/SBExpressionOptions.cpp
M lldb/source/API/SBValue.cpp
M lldb/source/Commands/CommandObjectRegister.cpp
M lldb/source/Core/DumpRegisterValue.cpp
M lldb/source/Host/common/XML.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/JSON/ObjectFileJSON.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.h
M lldb/source/Target/Memory.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetProperties.td
M lldb/source/Utility/XcodeSDK.cpp
M lldb/source/ValueObject/DILEval.cpp
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/Makefile
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/TestCreateValueFromExpression.py
A lldb/test/API/commands/frame/var-dil/expr/CreateValueFromExpression/main.cpp
M lldb/test/API/functionalities/gdb_remote_client/TestBatchedBreakpointStepOver.py
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py
M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterVector.py
M lldb/test/API/functionalities/json/object-file/TestObjectFileJSON.py
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/Makefile
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/TestStepThroughTrampolineWithSymbol.py
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/add.c
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/add.h
A lldb/test/API/lang/c/step-through-trampoline-with-symbol/main.c
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
M lldb/unittests/SymbolFile/DWARF/XcodeSDKModuleTests.cpp
M lldb/unittests/Target/MemoryTest.cpp
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/LangRef.md
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/DominanceFrontier.h
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/Analysis/RegionInfo.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/Dwarf.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Support/Allocator.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Support/FormattedStream.h
M llvm/include/llvm/Support/MathExtras.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/include/llvm/Transforms/Scalar/InferAddressSpaces.h
A llvm/include/llvm/Transforms/Utils/SplitModuleCommon.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/InstrMaps.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.h
M llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/VecUtils.h
M llvm/lib/Analysis/DominanceFrontier.cpp
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/RegionInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/Dwarf.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineBasicBlock.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXSubtarget.h
M llvm/lib/Target/PowerPC/PPC.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.cpp
M llvm/lib/Target/PowerPC/PPCSubtarget.h
M llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
M llvm/lib/Target/PowerPC/PPCTargetMachine.h
M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.cpp
M llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
M llvm/lib/Target/WebAssembly/WebAssembly.h
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
M llvm/lib/Transforms/Scalar/InferAddressSpaces.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
M llvm/lib/Transforms/Utils/SplitModule.cpp
A llvm/lib/Transforms/Utils/SplitModuleCommon.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/BundleVec.cpp
M llvm/lib/Transforms/Vectorize/SandboxVectorizer/VecUtils.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Analysis/ScalarEvolution/pointer-iv-addrec.ll
A llvm/test/Analysis/ScalarEvolution/trip-count-stride-positive-from-guard.ll
A llvm/test/Assembler/llvm.loop.align.ll
A llvm/test/Assembler/module-flags-thread-model.ll
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/test/CodeGen/AArch64/cgp-usubo.ll
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AArch64/fptrunc.ll
A llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
A llvm/test/CodeGen/AArch64/misched-postra-only1.mir
M llvm/test/CodeGen/AArch64/neon-truncstore.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma-mix-true16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/default-flat-work-group-size-overrides-waves-per-eu.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
A llvm/test/CodeGen/AMDGPU/int_to_fp_narrow_i64.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
M llvm/test/CodeGen/AMDGPU/regalloc-spill-wmma-scale.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
A llvm/test/CodeGen/ARM/cbz-no-kill-flag.mir
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
A llvm/test/CodeGen/NVPTX/atomics-system-scope-sm50.err.ll
A llvm/test/CodeGen/NVPTX/clmad.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
A llvm/test/CodeGen/NVPTX/inline-asm-line-info-per-inst-compiler-generated.ll
M llvm/test/CodeGen/PowerPC/aix-alloca-r31.ll
M llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll
M llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll
M llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
M llvm/test/CodeGen/PowerPC/aix-dfltabi-rsrvd-reg.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-clobber-register.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo.ll
M llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable-vectorinfo_hasvarg.ll
M llvm/test/CodeGen/PowerPC/aix-insert-extract.ll
M llvm/test/CodeGen/PowerPC/aix-spills-for-eh.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-callee.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
M llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
M llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
M llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
M llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-stack.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-caller.ll
M llvm/test/CodeGen/PowerPC/aix-vector-vararg-fixed-caller.ll
M llvm/test/CodeGen/PowerPC/aix32-p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
M llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll
M llvm/test/CodeGen/PowerPC/aix64-virtual-call-no-spills.ll
M llvm/test/CodeGen/PowerPC/bswap64.ll
M llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll
M llvm/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll
M llvm/test/CodeGen/PowerPC/cmpb-ppc32.ll
M llvm/test/CodeGen/PowerPC/cmpb.ll
M llvm/test/CodeGen/PowerPC/constants-i64.ll
M llvm/test/CodeGen/PowerPC/fdiv.ll
M llvm/test/CodeGen/PowerPC/fma-assoc.ll
M llvm/test/CodeGen/PowerPC/ftrunc-vec.ll
M llvm/test/CodeGen/PowerPC/gpr-vsr-spill.ll
M llvm/test/CodeGen/PowerPC/maddld.ll
M llvm/test/CodeGen/PowerPC/mi-peephole-splat.ll
M llvm/test/CodeGen/PowerPC/mmaplus-intrinsics.ll
M llvm/test/CodeGen/PowerPC/mulli.ll
M llvm/test/CodeGen/PowerPC/p10-handle-split-promote-vec.ll
M llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
M llvm/test/CodeGen/PowerPC/popcnt-zext.ll
M llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
M llvm/test/CodeGen/PowerPC/pr33093.ll
M llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
M llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
A llvm/test/CodeGen/PowerPC/target-abi-module-flag.ll
M llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll
M llvm/test/CodeGen/PowerPC/vec-bswap.ll
M llvm/test/CodeGen/PowerPC/vec_clz.ll
M llvm/test/CodeGen/PowerPC/vec_constants.ll
M llvm/test/CodeGen/PowerPC/vec_revb.ll
M llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
M llvm/test/CodeGen/PowerPC/vmladduhm.ll
M llvm/test/CodeGen/PowerPC/xxpermdi_mnemonics.s
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/cheri-global-bounds.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/pr56457.ll
M llvm/test/CodeGen/RISCV/rv64zbkb.ll
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/SystemZ/zos-align-constpool.ll
A llvm/test/CodeGen/SystemZ/zos-section-readonlywithrel.ll
M llvm/test/CodeGen/WebAssembly/eh-option-errors.ll
A llvm/test/CodeGen/WebAssembly/splitcriticaledge-physreg-liveness.mir
A llvm/test/CodeGen/X86/avx512fp16-combine-fmsubadd-fadd.ll
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
M llvm/test/CodeGen/X86/ctpop-mask.ll
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
M llvm/test/CodeGen/X86/popcnt.ll
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
M llvm/test/CodeGen/X86/subcarry.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-bf16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-f16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-smla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
A llvm/test/Linker/module-flags-thread-model.ll
A llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err-fake16.s
A llvm/test/MC/AMDGPU/gfx1250_asm_bf16_inline_const_err.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx1250_asm_vopd_errs.s
A llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err-fake16.s
A llvm/test/MC/AMDGPU/gfx13_asm_bf16_inline_const_err.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/literals.s
M llvm/test/MC/AMDGPU/misaligned-vgpr-tuples-err.s
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
M llvm/test/Other/new-pm-print-pipeline.ll
M llvm/test/Other/print-on-crash.ll
A llvm/test/TableGen/GlobalISelEmitter/MatchTableOptimizerTypes.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
A llvm/test/Transforms/AggressiveInstCombine/RISCV/lit.local.cfg
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
A llvm/test/Transforms/IndVarSimplify/exit-value-guarded-positive-stride.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/X86/noop-ptrint-pair.ll
M llvm/test/Transforms/InferAddressSpaces/fake-use.ll
A llvm/test/Transforms/InferAddressSpaces/infer-address-spaces-overlapping-dead.ll
M llvm/test/Transforms/InferAddressSpaces/masked-gather-scatter.ll
M llvm/test/Transforms/InferAddressSpaces/optnone-func-unchanged.ll
A llvm/test/Transforms/InferAddressSpaces/pass-param-parse-errors.ll
M llvm/test/Transforms/InferAddressSpaces/vector-of-pointers.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
M llvm/test/Transforms/InstCombine/trunc.ll
A llvm/test/Transforms/InstCombine/uitofp.ll
M llvm/test/Transforms/LoopVectorize/AArch64/force-target-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/predication_costs.ll
A llvm/test/Transforms/LoopVectorize/AArch64/sve-non-native-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-icmpcost.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/massv-calls.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
M llvm/test/Transforms/LoopVectorize/WebAssembly/memory-interleave.ll
A llvm/test/Transforms/LoopVectorize/X86/CostModel/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/X86/CostModel/vpinstruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/early_exit_legality.ll
M llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/fmin-without-fast-math-flags.ll
M llvm/test/Transforms/LoopVectorize/induction-cost.ll
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
M llvm/test/Transforms/LoopVectorize/phi-cost.ll
M llvm/test/Transforms/LoopVectorize/predicated-inductions-vs-first-order-recurrences.ll
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/PGOProfile/ppc-prevent-mma-types.ll
A llvm/test/Transforms/RelLookupTableConverter/AArch64/dynamic_relocs.ll
M llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
A llvm/test/Transforms/SLPVectorizer/AArch64/splat-gather-subtree-loop-extracts.ll
M llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps-2.ll
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps.ll
A llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
M llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-booleanized-leaves.ll
A llvm/test/Transforms/SROA/large-alloca.ll
A llvm/test/Transforms/SafeStack/X86/pointer-address-domtree.ll
A llvm/test/Verifier/llvm.loop.align.ll
A llvm/test/Verifier/module-flags-thread-model.ll
M llvm/test/tools/llubi/fp_cast.ll
A llvm/test/tools/llvm-dwarfdump/AMDGPU/DW_AT_LLVM_memory_space.yaml
M llvm/test/tools/llvm-split/unnamed.ll
M llvm/tools/llc/CMakeLists.txt
R llvm/tools/llc/NewPMDriver.cpp
R llvm/tools/llc/NewPMDriver.h
A llvm/tools/llc/lib/CMakeLists.txt
A llvm/tools/llc/lib/NewPMDriver.cpp
A llvm/tools/llc/lib/NewPMDriver.h
A llvm/tools/llc/lib/llcdriver.cpp
R llvm/tools/llc/llcdriver.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/tools/llvm-jitlink/llvm-jitlink.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
M llvm/unittests/Analysis/ScalarEvolutionTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/SimpleRemoteEPCUtilsTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Support/AllocatorTest.cpp
M llvm/unittests/Support/KnownFPClassTest.cpp
M llvm/unittests/Support/formatted_raw_ostream_test.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/SandboxVectorizer/VecUtilsTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/Common/GlobalISel/MatchTable/Matchers.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/gn/secondary/compiler-rt/lib/ubsan/BUILD.gn
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llc/lib/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/Orc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
M mlir/examples/toy/Ch2/mlir/Dialect.cpp
M mlir/examples/toy/Ch3/mlir/Dialect.cpp
M mlir/examples/toy/Ch4/mlir/Dialect.cpp
M mlir/examples/toy/Ch5/mlir/Dialect.cpp
M mlir/examples/toy/Ch6/mlir/Dialect.cpp
M mlir/examples/toy/Ch7/mlir/Dialect.cpp
M mlir/include/mlir/Analysis/DataFlowFramework.h
M mlir/include/mlir/CAPI/Wrap.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLDialect.td
M mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Support/DebugStringHelper.h
M mlir/lib/Analysis/DataFlowFramework.cpp
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemRefs.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/lib/Dialect/MemRef/Utils/CMakeLists.txt
M mlir/lib/Dialect/MemRef/Utils/MemRefUtils.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Dialect/PDLInterp/IR/PDLInterp.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/Dialect/ROCDL/ROCDLToLLVMIRTranslation.cpp
M mlir/lib/Tools/mlir-pdll-lsp-server/Protocol.cpp
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
M mlir/test/Analysis/test-foo-analysis.mlir
A mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp-gfx1170.mlir
A mlir/test/Conversion/AMDGPUToROCDL/lds-barrier-gfx90c.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
M mlir/test/Conversion/VectorToGPU/vector-to-mma-ops.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
M mlir/test/Dialect/GPU/decompose-memrefs.mlir
M mlir/test/Dialect/LLVMIR/rocdl.mlir
A mlir/test/Dialect/Linalg/hoist-redundant-vector-transfers.mlir
M mlir/test/Dialect/Linalg/hoisting.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/IR/invalid-builtin-types.mlir
M mlir/test/IR/parser.mlir
A mlir/test/Integration/GPU/CUDA/TensorCore/wmma-transposed-store-f16.mlir
A mlir/test/Target/LLVMIR/nvvm/ex2_invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
M mlir/test/Target/LLVMIR/rocdl-module-flags.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
M offload/ci/hip-tpl.py
M offload/plugins-nextgen/amdgpu/dynamic_hsa/hsa.cpp
M openmp/device/include/Interface.h
M openmp/device/src/State.cpp
M openmp/docs/Building.md
M openmp/libompd/gdb-plugin/CMakeLists.txt
M openmp/libompd/gdb-plugin/README.txt
R openmp/libompd/gdb-plugin/ompdDLService.c
A openmp/libompd/gdb-plugin/ompdDLService.cpp
M openmp/libompd/test/lit.cfg
M openmp/libompd/test/lit.site.cfg.in
M openmp/libompd/test/ompd_dl_service.c
M openmp/module/omp_lib.F90.var
M openmp/runtime/src/dllexports
M openmp/runtime/src/include/omp.h.var
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_csupport.cpp
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_ftn_os.h
M openmp/runtime/src/kmp_stub.cpp
A openmp/runtime/test/api/kmp_integer_8_apis.f90
M orc-rt/CMakeLists.txt
M orc-rt/docs/CodingConventions.md
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/support/CoreTypes.h
M orc-rt/include/orc-rt-c/support/Error.h
A orc-rt/include/orc-rt-c/support/RTTI.h
A orc-rt/include/orc-rt/bedrock/SocketHandle.h
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/RTTI.h
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
A orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
M orc-rt/lib/support/Error.cpp
M orc-rt/lib/support/RTTI.cpp
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/Inputs/RTTICrossDylibTestError.h
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
A orc-rt/test/unit/bedrock/SocketHandleTest.cpp
A orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
M orc-rt/test/unit/support/CAPICompileTest.c
M orc-rt/test/unit/support/ErrorCAPITest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
A orc-rt/test/unit/support/RTTICrossDylibTest.cpp
M orc-rt/test/unit/support/RTTITest.cpp
M orc-rt/tools/ogre/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/mman/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.8-beta.1
[skip ci]
Compare: https://github.com/llvm/llvm-project/compare/4fb11173d367...fc07c0d0715a
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