[all-commits] [llvm/llvm-project] 64b7df: [PassManager] Store analysis results in contiguous...
Adam Smith via All-commits
all-commits at lists.llvm.org
Mon Sep 14 06:41:30 PDT 2026
Branch: refs/heads/users/adams381/cir-callconv-dropped-return-res-attrs
Home: https://github.com/llvm/llvm-project
Commit: 64b7dfef40e59b8596a272a431aa3a4abcef33c1
https://github.com/llvm/llvm-project/commit/64b7dfef40e59b8596a272a431aa3a4abcef33c1
Author: Clemens Wasser <clemens.wasser at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerImpl.h
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M polly/include/polly/ScopInfo.h
Log Message:
-----------
[PassManager] Store analysis results in contiguous storage (#222003)
Store per-IR analysis results in a `SmallVector` instead of `std::list`
to avoid a heap allocation per cached analysis. The lookup map stores
the raw result pointer, which stays stable behind the unique_ptr.
geomean -0.12% for optimizing builds, clang build -0.34%
https://llvm-compile-time-tracker.com/compare.php?from=e6734a41bb41d91cb880fe7abce46d8146182518&to=4fc43802817cf8daddbebadb0b7fbfaa6286e7fe&stat=instructions:u
Commit: 2eb8c73f47c7bf6560fc6458713099fd5e1921a3
https://github.com/llvm/llvm-project/commit/2eb8c73f47c7bf6560fc6458713099fd5e1921a3
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
[AMDGPU] Expose buffer resource num_records width in TargetParser (#220103)
This also fixes the conflict in gfx12.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---------
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 9a9ed337c81c4ca2b95e5f8f7fcb449220c722ae
https://github.com/llvm/llvm-project/commit/9a9ed337c81c4ca2b95e5f8f7fcb449220c722ae
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A llvm/test/tools/dsymutil/Inputs/member-hash/2.o
A llvm/test/tools/dsymutil/Inputs/member-hash/debug-map.map
A llvm/test/tools/dsymutil/X86/member-hash.cpp
Log Message:
-----------
[dsymutil] Test qualified name hashing for members (#223017)
hashFullyQualifiedName walks DW_AT_specification to reach a member's
enclosing struct, so the accelerator table entry for a type nested in an
out-of-line member function definition depends on that walk. Pin the
resulting hash.
The test has lived downstream since the fix that made the function take
its DWARFDie by value instead of by pointer, where the pointee went out
of scope during the walk. Give it a debug map of its own describing
member-hash/2.o rather than extending the shared dummy-debug-map.map,
which describes a different set of objects.
rdar://184990209
Commit: e41147d567ee1f3eddc77ff3cbf505a4d5158e84
https://github.com/llvm/llvm-project/commit/e41147d567ee1f3eddc77ff3cbf505a4d5158e84
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/XVentanaCondOps-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Remove Ventana Conditional Ops (#221042)
This extension is used by any silicon as far as I am aware.
If any person/company was reliant on this extension, the extension
can be added back in under the same/different name.
AI Usage: Assisted by Codex
Commit: ecb66ef84fc881eb8bea392cbd9b61f83605b196
https://github.com/llvm/llvm-project/commit/ecb66ef84fc881eb8bea392cbd9b61f83605b196
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
Log Message:
-----------
[CIR][NFCI] Refactor uses of 'mlir::Location' vs 'SourceRange' on calls/etc (#222981)
As a prerequisite to an upcoming patch, emitCall needs access to the
Clang source locations, not just the mlir::Location. We're going to need
this in quite a few more places in the future, since there are various
diagnostics that use clang locations in the code generation.
This patch also has to change the RAII source location stuff, which I
switched to SourceRange. This should improve the amount of data we give
for our source information.
I DID have to remove the assertion on it though, because we do have a
few places that intentionally wanted an invalid location if other stuff
wasn't available (see the CUDA use in particular), but otherwise this
should allow us to improve our source location info, AND use it for
diagnostics in the future.
Commit: 9a762fce97374fb1ce5d2f21f99b5a7ed584ba71
https://github.com/llvm/llvm-project/commit/9a762fce97374fb1ce5d2f21f99b5a7ed584ba71
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Implement 'simple' atomic inc/dec. (#222730)
This only works for types where a compare-exchange instruction (or just
a lock-free implementation matters) is possible, and a loop isn't
necessary. This is basically just a conversion of classic-codegen,
except it clarifies some of the logic (particularly around bools).
Commit: 28efe19f92567ec666e205b860cfd77f6f1764fc
https://github.com/llvm/llvm-project/commit/28efe19f92567ec666e205b860cfd77f6f1764fc
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/docs/UsersManual.md
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/CodeGen/keep-inline-functions.c
A clang/test/CodeGen/keep-inline-functions.cpp
A clang/test/CodeGen/keep-inline-functions.cppm
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fkeep-inline-functions.c
Log Message:
-----------
[Clang] Implement -fkeep-inline-functions (#218533)
Implement the -fkeep-inline-functions flag, which forces selected inline
function definitions to be emitted into the object file even if they
have been inlined into all their callers. The function retention
behavior follows GCC's semantics.
The front-end has been modified to:
- emit the selected functions even if they are unused; and
- add the selected functions to llvm.compiler.used/llvm.used to ensure
they are retained.
The functions selected for emission are inline function definitions that
are available in the current translation unit. available_externally
definitions are excluded because their authoritative definitions are
expected to be emitted by another translation unit.
This is also done for C99 inline function external definitions with
external linkage, which would normally be emitted into the object file
anyway, to ensure the functions are retained for LTO purposes.
See the proposed Clang documentation update for details on the function
selection criteria.
Commit: 204b703adb18599fc7f5d7b1bc0b0b410ca1ce15
https://github.com/llvm/llvm-project/commit/204b703adb18599fc7f5d7b1bc0b0b410ca1ce15
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
Fix bazel build for libc/test/UnitTest:string_utils (#223051)
Fixes https://github.com/llvm/llvm-project/pull/222988 (commit
18db3eee9d04) by adding missing dependencies.
Commit: 105ff16f816ffdce14b1d4895d8584971ef5192c
https://github.com/llvm/llvm-project/commit/105ff16f816ffdce14b1d4895d8584971ef5192c
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M lld/test/ELF/lto/riscv-target-abi.ll
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
M llvm/test/CodeGen/RISCV/target-abi-invalid.ll
M llvm/test/MC/RISCV/target-abi-invalid.s
M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
Log Message:
-----------
[RISCV] Change RISCVABI::computeTargetABI() to return Expected<ABI>
Return Expected<ABI> instead of printing to errs()/reportFatalUsageError
internally, so callers decide whether to fall back to the default ABI
or treat the failure as fatal, and so it's unit-testable. Also fold the
duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and
RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest
coverage for the error paths.
This change was created with the help of AI tools
Reviewed By: lenary
Pull Request: https://github.com/llvm/llvm-project/pull/213410
Commit: 51450333e1fd156fcdb20b61d7c70ed96461812b
https://github.com/llvm/llvm-project/commit/51450333e1fd156fcdb20b61d7c70ed96461812b
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
Log Message:
-----------
[BOLT][AArch64][Android] Only the dumping thread can longjmp (#222719)
`__bolt_instr_recovery_active` is a process global flag and the reader
in `boltHandleFatalAndRecover()` runs on any thread. When a dump is in
flight, another thread that fails `assert()` or exhausts `GlobalAlloc`
in `instrumentIndirectCall()` could see the flag set, longjmp with the
dumping thread's buffer and restore the dump thread's sp/fp/lr. This
is wrong since the thread would then run on the dumping thread's stack
and later release a mutex that it does not own or hold.
`GlobalWriteProfileMutex` already serializes the writers, so one buffer
would be sufficient; only the reader side needs to know who owns the
buffer. Replace the flag with `__bolt_instr_recovery_tid` holding the
owner's thread ID, and longjmp only when it matches `__gettid()`. Other
threads will fall through to just record the failure and return.
Added a `__gettid()` syscall wrapper, for aarch64 only.
Assited-by: opus
Commit: 5c27600b852b9a86b7811142482a09defd963ad3
https://github.com/llvm/llvm-project/commit/5c27600b852b9a86b7811142482a09defd963ad3
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/atomic64-typed-resource.ll
Log Message:
-----------
[DirectX] Add texture support to atomicrmw lowering (#221369)
Fixes https://github.com/llvm/llvm-project/issues/218034
Fixes https://github.com/llvm/llvm-project/issues/186154
atomicrmw lowering didn't support textures. This PR adds that missing
support.
Assisted by: Claude Opus 5
Commit: 364bed30971df7fb50d7aadfc21f3996a97bf3a4
https://github.com/llvm/llvm-project/commit/364bed30971df7fb50d7aadfc21f3996a97bf3a4
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
Log Message:
-----------
(NFC)[Clang][Driver] Add ToolChain::GetFilePathIfExists and use it (#221063)
Replaces patterns like `if (TC.GetFilePath("file") != "file")` to avoid
repeating `"file"`.
Commit: 393710bbf74c4e7b92226603a18ead0bba70a8a0
https://github.com/llvm/llvm-project/commit/393710bbf74c4e7b92226603a18ead0bba70a8a0
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
A llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
Log Message:
-----------
Reland "[llvm][AArch64] Ensure stack alignment in non-sibcall tail calls with FPDiff" (#220406)
When a caller has a non-multiple of the minimum stack alignment more
argument stack space than the callee it is tail calling, we need to ensure that
the resulting FPDiff's magnitude has been rounded up to a multiple of the
platform's minimum stack alignment.
In this re-land there is a fixup to 234ce03692ede13ffd2fcb35570d801c1e332814,
which, because of the wrong order, wasn't actually moving NumBytes after
FPDiff had been re-aligned.
rdar://184474075
Commit: f77ec648706b957698a61e54a715bd69042ce491
https://github.com/llvm/llvm-project/commit/f77ec648706b957698a61e54a715bd69042ce491
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Fix -Wunused-lambda-capture in #223016 (#223053)
Clang will warn on this despite this being required for MSVC, so add a
workaround for now.
Commit: d42c701dc3d00dacff3806ea428a274aae39fed0
https://github.com/llvm/llvm-project/commit/d42c701dc3d00dacff3806ea428a274aae39fed0
Author: Kunal Pathak <kunalspathak at hotmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
A llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-indirect-call-anchor.prof
A llvm/test/Transforms/SampleProfile/Inputs/profile-mismatch-indirect-call.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-multiple-sampled-callees.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-zero-callee.prof
A llvm/test/Transforms/SampleProfile/non-probe-stale-profile-indirect-call-anchor.ll
A llvm/test/Transforms/SampleProfile/profile-mismatch-indirect-call.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch.ll
Log Message:
-----------
[SampleProfile] Ignore unsampled callees in profile anchors (#219335)
Sample profiles can retain zero-count callee entries in both flattened
body call targets and
unflattened callsite samples:
```text
probe 12:
foo: 10
cleanup: 0
```
Counting every entry as a distinct callee converts the uniquely sampled
foo callsite into
UnknownIndirectCallee. It then fails to match the direct IR call to foo,
causing valid
samples to be reported as stale.
Ignore zero-count entries when the same location has a sampled callee.
Preserve the existing
behavior for genuine multi-callee sites and locations where every callee
has zero samples.
```text
foo: 10, cleanup: 0 -> foo
foo: 10, bar: 1 -> UnknownIndirectCallee
foo: 0, cleanup: 0 -> unchanged
```
The change covers both:
- flattened call targets from body samples;
- inline callees from unflattened callsite samples.
## Related fixes
This is downstream profile-matching robustness related to #219079.
Those changes prevent invalid pseudo-probe context earlier in the
pipeline. This change
ensures that any zero-sample entries reaching the profile matcher are
not treated as
evidence of another executed callee.
## Tests
Added regression coverage for zero-sample callees, genuine multiple
sampled callees,
flattened body targets, and unflattened callsite samples.
Assisted by: Claude
Commit: 55221f7a2baca65325ad073eabdaf8cc18472e12
https://github.com/llvm/llvm-project/commit/55221f7a2baca65325ad073eabdaf8cc18472e12
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/test/Driver/flang-f-opts.f90
Log Message:
-----------
[Flang/CI] Hotfix of flang/test/Driver/flang-f-opts.f90. (#223076)
The test started failing in Flang CI after #218533. This is just a
hotfix.
Commit: 17de86741560e43304c8c013092d80ae91d401ff
https://github.com/llvm/llvm-project/commit/17de86741560e43304c8c013092d80ae91d401ff
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/IR/Dominators.cpp
Log Message:
-----------
[IR] Make verify<domtree> work in non-asserts builds (#223066)
It doesn't make sense to lose this test coverage in non-assert builds,
and I would expect a release build of opt to have a working
verify<domtree> pass. This also better matches the behavior of the other
verify<*> passes.
Commit: 242ccbf6b6d9d090762a87138c854f2d93b6ab60
https://github.com/llvm/llvm-project/commit/242ccbf6b6d9d090762a87138c854f2d93b6ab60
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
Log Message:
-----------
[BOLT] Fix -Wunused-template (#222439)
This was enabled by default in LLVM 23.1.0. It was disabled in LLVM
23.1.1, but it makes sense to fix the outstanding issues given they are
real.
Commit: 44d1d020a920341903e726506f3efefe27ea3145
https://github.com/llvm/llvm-project/commit/44d1d020a920341903e726506f3efefe27ea3145
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
Add standard libc package features to libc subpackages (#223079)
Commit: 04a04612e6696d36cd26edadddf20d1329794d2e
https://github.com/llvm/llvm-project/commit/04a04612e6696d36cd26edadddf20d1329794d2e
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][Cpp] Stop using Operation::getAttrs (NFC) (#223080)
Only discardable attributes on multi-result func.return operations are
C++ tuple arguments; the operation has no inherent attributes relevant
to the translation.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: b5874129d921518823d257770c742da2a860b2cf
https://github.com/llvm/llvm-project/commit/b5874129d921518823d257770c742da2a860b2cf
Author: Kareem Ergawy <kergawy at nvidia.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/test/Transforms/licm.fir
Log Message:
-----------
[flang] Do not hoist fir.field_index out of loops (#222891)
Lowering a consumer of a !fir.field value inspects its defining
operation: for a record whose layout is known at compile time the field
becomes an LLVM GEP struct index, which must be a constant, and
otherwise the `field` attribute is read off the defining op. A field
value therefore may not be a block argument.
LICM broke that. fir.field_index is Pure and takes no operands, so it is
trivially loop-invariant and was hoisted out of the loop. Lowering emits
one inside each arm of a construct -- for example the CASEs of a SELECT
CASE that each pass a different component of the same derived type as an
actual argument -- so hoisting them left those arms as
otherwise-identical blocks differing only in that operand. Block merging
then merged them and threaded the field through a new block argument,
and codegen aborted with "must be a constant".
Leave producers of a !fir.field where they are. The arms then differ by
an operation rather than by an operand, so they are no longer merge
candidates. Consumers are unaffected and still hoist: fir.coordinate_of
uses the attribute form of the field, so it does not depend on the
fir.field_index value.
The check keys on the result type rather than on FieldIndexOp so that
any operation producing a !fir.field is covered, and sits in the
predicate shared by the direct-loop and nested-region hoisting paths.
Commit: f795e9526254f4d1cee4855b40041d5797d2f676
https://github.com/llvm/llvm-project/commit/f795e9526254f4d1cee4855b40041d5797d2f676
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Shape/IR/Shape.cpp
Log Message:
-----------
[mlir][Shape] Stop using Operation::getAttrs in printers (NFC) (#223083)
Print only discardable attributes after inherent fields are handled by
the custom assembly formats.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: bb14dc958cbb7f9742f37cbae6d290a0997e7299
https://github.com/llvm/llvm-project/commit/bb14dc958cbb7f9742f37cbae6d290a0997e7299
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/examples/toy/Ch2/mlir/Dialect.cpp
M mlir/examples/toy/Ch3/mlir/Dialect.cpp
M mlir/examples/toy/Ch4/mlir/Dialect.cpp
M mlir/examples/toy/Ch5/mlir/Dialect.cpp
M mlir/examples/toy/Ch6/mlir/Dialect.cpp
M mlir/examples/toy/Ch7/mlir/Dialect.cpp
Log Message:
-----------
[mlir][Toy] Stop using Operation::getAttrs (NFC) (#223082)
Print only discardable attributes in Toy custom operation printers.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: c7a7f8364a1335b8938af2113fd8ec43cd3a2c47
https://github.com/llvm/llvm-project/commit/c7a7f8364a1335b8938af2113fd8ec43cd3a2c47
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
Log Message:
-----------
[mlir] Stop using Operation::getAttrs in dialect utilities (NFC) (#223081)
Copy operation properties and discardable attributes separately.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 4cec7e6e3082e8abbee08f90db3c353c4c379bdb
https://github.com/llvm/llvm-project/commit/4cec7e6e3082e8abbee08f90db3c353c4c379bdb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
Log Message:
-----------
[mlir][SMT] Stop using Operation::getAttrs (NFC) (#223086)
Print only discardable attributes after inherent fields are handled by
the custom operation printers.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 0cc524fdf4becec3763cd50930de5156d76ba1d4
https://github.com/llvm/llvm-project/commit/0cc524fdf4becec3763cd50930de5156d76ba1d4
Author: nvptm <pmathew at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-declare-globals.f90
M flang/test/Lower/module-parameter-linkonce-odr.f90
Log Message:
-----------
[flang][OpenACC] Do not emit declare ctor/dtor for module PARAMETER variables (#222993)
A module PARAMETER in !$acc declare is already emitted as an initialized
device global. A host ctor/dtor would still register that same symbol
with the runtime. Skip the registration pair and keep acc.declare so the
constant is
still emitted as an initialized global in the GPU module.
Commit: 5f09d40446ffbcd92d9e1a2a14bae974eb445cdb
https://github.com/llvm/llvm-project/commit/5f09d40446ffbcd92d9e1a2a14bae974eb445cdb
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/PDLInterp/IR/PDLInterp.cpp
Log Message:
-----------
[mlir][PDLInterp] Stop using Operation::getAttrs (NFC) (#223088)
Print the discardable dictionary after the inherent fields handled by
the custom assembly format.
This is part of a general migration to use the "new" properties-based
APIs and stop mixing discardable/inherent attributes, see #155475
Assisted-by: Codex
Commit: 641dc586869b21dc42785aa72949ed57c408204e
https://github.com/llvm/llvm-project/commit/641dc586869b21dc42785aa72949ed57c408204e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/docs/CodingConventions.md
M orc-rt/include/orc-rt-c/support/CoreTypes.h
M orc-rt/include/orc-rt-c/support/Error.h
A orc-rt/include/orc-rt-c/support/RTTI.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/RTTI.h
M orc-rt/lib/support/Error.cpp
M orc-rt/lib/support/RTTI.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/Inputs/RTTICrossDylibTestError.h
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
M orc-rt/test/unit/support/CAPICompileTest.c
M orc-rt/test/unit/support/ErrorCAPITest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
A orc-rt/test/unit/support/RTTICrossDylibTest.cpp
M orc-rt/test/unit/support/RTTITest.cpp
Log Message:
-----------
[orc-rt] Refactor RTTI for cross-library support, add C API (#222946)
Identify types by name rather than by the address of a per-type ID
object, so that a type's identity survives crossing a library boundary:
an object may be constructed by one library and have its type queried by
another, each with its own copy of orc-rt, where per-type addresses
would not agree. Participating classes now declare an RTTIName, which
must be unique across the process.
RTTIRoot records which library produced each value, so same-library
queries still resolve by pointer comparison, and only cross-library ones
fall back to strcmp.
Adds orc-rt-c/support/RTTI.h to expose this to C.
ORC_RT_RTTI_PARTICIPANT and ORC_RT_C_RTTI_IMPL declare and define a
per-type cast entry point, reached via ORC_RT_DYNCAST, alongside
orc_rt_RTTIRoot_getTypeName for logging. This replaces the
orc_rt_Error_TypeId API (orc_rt_Error_getTypeId,
orc_rt_StringError_getTypeId), which exposed ID addresses and so could
not work across libraries. orc_rt_ErrorRef moves from CoreTypes.h to
Error.h.
RTTICrossDylibTest checks identity across a real boundary: its helper
library links its own copy of orc-rt-bedrock, giving it a distinct
library ID.
Commit: 80bc02604c4ecec507c906552db3e03e5efdaee3
https://github.com/llvm/llvm-project/commit/80bc02604c4ecec507c906552db3e03e5efdaee3
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
Log Message:
-----------
[flang][OpenACC] Allocate bufferized recipe descriptors in device memory (#223028)
ACCRecipeBufferization places the descriptor of a bufferized recipe
clause next to the variable it holds. When the clause sits inside a
compute construct and the variable is already produced by a data entry
operation, that memory is host memory no data clause maps, so device
code reading the descriptor through it gets a host address.
Place the descriptor in the construct region in that case. The region is
device memory and needs no data clause of its own, and the mapped
variable is a legal live-in since a data entry operation produces it.
The region entry block is used rather than the clause operation so that
a clause on a nested loop does not allocate on every iteration.
Assisted-by: Cursor
Commit: a8e989fe377385906abdda1f965622fe83941fd4
https://github.com/llvm/llvm-project/commit/a8e989fe377385906abdda1f965622fe83941fd4
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
M flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
Log Message:
-----------
[mlir][OpenACC] Preserve reduction mappings during materialization. (#222189)
Create or reuse structured reduction mappings before compute-construct
reduction recipes are consumed. Materialize initialization and
combination against the mapped value while leaving nested loop
reductions unchanged.
Assisted-by: Cursor
Commit: 4d10444e7d4c8fcb6533522f39cd0ffb88497253
https://github.com/llvm/llvm-project/commit/4d10444e7d4c8fcb6533522f39cd0ffb88497253
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
Log Message:
-----------
[mlir][OpenACC] Restrict implicit data to compute constructs (#222759)
acc.kernel_environment contains host-side preparation around an outlined
compute region; it is not itself an OpenACC compute construct. Treating
all of its live-ins as implicit device mappings can map
compiler-generated host operations and assign them kernels-style copy
semantics.
Limit ACCImplicitData to parallel, kernels, and serial. In particular,
do not process kernel_environment or the lowered compute_region form.
Assisted-by: Cursor
Commit: 329f45430835fe803b753ac78fc823b5dfc5df69
https://github.com/llvm/llvm-project/commit/329f45430835fe803b753ac78fc823b5dfc5df69
Author: Douglas <Douglas.Gliner at sony.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SafeStack.cpp
A llvm/test/Transforms/SafeStack/X86/pointer-address-domtree.ll
Log Message:
-----------
[CodeGen][SafeStack] Successful InlineFunction should force a recalculation of potentially stale DominatorTree (#222820)
In commit 51a25846c198, Safe Stack began preserving the `DominatorTree`
by the end of the pass' run. Updates to the `DominatorTree` were then
made lazily via inclusion of `DomTreeUpdater` and its use with
`SplitBlockAndInsertIfThen`. Preservation was maintained when updated to
the new pass manager in 3bd517205799. However, there was an overlooked
case where the `DominatorTree` would remain stale by the end of the Safe
Stack pass if the actions under `TryInlinePointerAddress` completed
successfully and modified the caller's CFG.
The conditions for a stale `DominatorTree` to exist are roughly:
1. Safe Stack obtains the Unsafe Stack pointer location as a `CallInst`
(i.e. one way is `-safestack-use-pointer-address`)
2. `__safestack_pointer_address` is defined and inlined successfully.
3. The inlining changes the CFG such that a recalculated `DominatorTree`
would differ.
4. `DominatorTree` remains unchanged since it is preserved and currently
not recalculated.
Here's a simple example that demonstrates the issue:
```
@unsafe_stack_pointer_a = thread_local global ptr null
@unsafe_stack_pointer_b = thread_local global ptr null
declare i32 @get_runtime_mode() nounwind willreturn memory(none)
declare void @escape(ptr)
define ptr @__safestack_pointer_address() alwaysinline {
entry:
%first = call i32 @get_runtime_mode()
%use_a = icmp eq i32 %first, 0
br i1 %use_a, label %a, label %b
a:
ret ptr @unsafe_stack_pointer_a
b:
ret ptr @unsafe_stack_pointer_b
}
define i32 @caller() safestack {
entry:
%unsafe = alloca i32, align 4
call void @escape(ptr %unsafe)
%second = call i32 @get_runtime_mode()
ret i32 %second
}
```
```
> opt -mtriple=x86_64-pc-linux-gnu -safestack-use-pointer-address -passes=require<libcall-lowering-info>,function(safe-stack,verify<domtree>) -disable-output example.ll
DominatorTree is different than a freshly computed one!
Current:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
[1] %entry {4294967295,4294967295} [0]
Roots: %entry
Freshly computed tree:
=============================--------------------------------
Inorder Dominator Tree: DFSNumbers invalid: 0 slow queries.
[1] %entry {4294967295,4294967295} [0]
[2] %a.i {4294967295,4294967295} [1]
[2] %__safestack_pointer_address.exit {4294967295,4294967295} [1]
[2] %b.i {4294967295,4294967295} [1]
Roots: %entry
```
To avoid a stale `DominatorTree` by the end of the Safe Stack pass, I
propose calling `recalculate` on the `DominatorTree` for the function
which will have the call to `__safestack_pointer_address` inlined
assuming the inlining was successful and `DomTreeUpdater` is non-NULL.
Commit: 923902483c7a6937a65b9679795a247ae2a2ad56
https://github.com/llvm/llvm-project/commit/923902483c7a6937a65b9679795a247ae2a2ad56
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M lldb/include/lldb/Host/SafeMachO.h
Log Message:
-----------
[lldb] Attempt to unbreak building lldb with the 27 SDK (#223090)
See this report:
https://github.com/llvm/llvm-project/pull/222721#issuecomment-5636252813
Commit: 4e3b379b6cfcd13a11e26834756519430a9f9377
https://github.com/llvm/llvm-project/commit/4e3b379b6cfcd13a11e26834756519430a9f9377
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M mlir/include/mlir/CAPI/Wrap.h
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Support/DebugStringHelper.h
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Tools/mlir-pdll-lsp-server/Protocol.cpp
Log Message:
-----------
[MLIR] Fix -Wunused-template (#221480) (#223094)
This warning was enabled by default for clang 23 (although reverted in
23.1.1). Given someone might enable it in the future and the cleanup
seemed nice, we should just do it.
This was done primarily by removing static from templates in headers and
then deleting any unused templates in translation units.
Previously attempted to land this in #221480, but accidentally merged
into a user branch rather than main.
Commit: 675cfb91660e20bfc17456f347c01c310322fc9d
https://github.com/llvm/llvm-project/commit/675cfb91660e20bfc17456f347c01c310322fc9d
Author: Yonah Goldberg <ygoldberg at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
A llvm/test/CodeGen/NVPTX/atomics-system-scope-sm50.err.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
Log Message:
-----------
[NVPTX] Error on atomics with system scope pre-sm60 (#222458)
Pre-SM60, atomics could only have device scope.
`NVPTXDAGToDAGISel::getAtomicScope` can conservatively emit device scope
for all scopes that are not system scope. For system scope, we need to
error out.
This resolves a TODO in llvm/test/CodeGen/NVPTX/cmpxchg.ll. Update that
and llvm/test/CodeGen/NVPTX/cmpxchg.ll to use SM60 now, demonstrating
correct lowering for system scope.
Commit: 5618cfdae27157a48ea670e6d817310404afb746
https://github.com/llvm/llvm-project/commit/5618cfdae27157a48ea670e6d817310404afb746
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
Log Message:
-----------
[RISCV] Remove hasCZEROLike() in favor of directly checking for Zicond Extension (#221053)
Only Zicond implements a CZero-Like instruction now that Ventana
Conditional Operations have been removed.
Commit: 7727fb8eaed54b90d08a35fca4896a21a04349b2
https://github.com/llvm/llvm-project/commit/7727fb8eaed54b90d08a35fca4896a21a04349b2
Author: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
Log Message:
-----------
[NFC][AMDGPU] Add tests for converting an i64 that fits in 32 bits (#223030)
It is converted with the full i64 expansion. The shifts by 31 leave a
value that does not fit.
The idea is to optimize conversion of an i64 that fits in 32 bits from
its low half.
Commit: 355cbe15b1c7694cab8590ecd773087b78a31121
https://github.com/llvm/llvm-project/commit/355cbe15b1c7694cab8590ecd773087b78a31121
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Implement MonotonicDescriptor (#214490)
RFC link:
https://discourse.llvm.org/t/rfc-loop-vectorization-of-compress-store-expand-load-patterns/86442
"Monotonic" variable is similar to induction variable, but its value is
updated under some condition, e.g.:
```
int idx = 0;
for(int i = 0; i < n; ++i) {
// some uses of idx
if (cond)
++idx;
}
```
In this example, `i` is induction variable and `idx` is monotonic
variable: it's updated only when cond == true. In LLVM IR, this looks
like:
```
loop_header:
%monotonic_phi = phi [ %start, %preheader ], [ %update, %latch ]
br i1 %do_step, label %step_bb, label %latch
step_bb:
%step = add/gep %monotonic_phi, %step_val
br label %latch
latch:
%update = phi [ %monotonic_phi, %loop_header ], [ %step, %step_bb ]
br label %loop_header
```
This initial patch only matches the case where `%update` directly
selects between the `%monotonic_phi` or the step. We also limit the
descriptor to only matching cases where all users of the
`%monotonic_phi` are loads/stores that can be mapped to expandloads or
compresstores.
This is a continuation Sergey Kachkov's patch (#140720).
---------
Co-authored-by: Sergey Kachkov <sergey.kachkov at syntacore.com>
Commit: 4e865028f0563584bde4e54858855ba4f45946ad
https://github.com/llvm/llvm-project/commit/4e865028f0563584bde4e54858855ba4f45946ad
Author: David Tellenbach <dtellenbach at apple.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
Log Message:
-----------
[AArch64] Form CCMP for CBB and CBH (#221113)
AArch64ConditionalCompares forms CMP/CCMP chains to transform patterns
such as
Head Head
/ | CmpBB
/ | / |
| CmpBB => / |
| / | Tail |
| / | | |
Tail | | |
| | | |
... ... ... ...
where Head is terminated by a conditional branch and CmpBB contains
a cmp + conditional branch.
We usually try to split any fused conditional branches to be able to
form CCMP. However, in the case of CBB and CBH, splitting the fused
conditional branch in CmpBB could require the insertion of explicit
zero- or sign-extensions for both operands. In the Head block we can
cheaply fuse at least one of the extensions into cmp.
We therefore convert CBB and CBH unconditionally when we find them in
the Head block. In the CmpBB block, we only do the transformation if
neither operands needs an extension.
Commit: 2c30f74239871203b0a998cd4797e01c3338a9fa
https://github.com/llvm/llvm-project/commit/2c30f74239871203b0a998cd4797e01c3338a9fa
Author: PiJoules <leonardchan at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
A llvm/test/Transforms/RelLookupTableConverter/AArch64/dynamic_relocs.ll
M llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
R llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
A llvm/test/Transforms/RelLookupTableConverter/relative_lookup_table.ll
Log Message:
-----------
[llvm] Avoid PREL32 overflow to .data.rel.ro on AArch64 and re-enable (#222809)
Under the [AArch64 Small Code
Model](https://github.com/ARM-software/abi-aa/blob/main/sysvabi64/sysvabi64.rst#code-models),
the text segment (containing .text and .rodata) is limited to 2GB, but
the combined span of text and data segments can be up to 4GB.
When a relative lookup table is emitted in .rodata but references target
operands that require dynamic relocations (placed in .data.rel.ro in the
data segment), the distance between .rodata and .data.rel.ro can legally
exceed the 2GB range of signed 32-bit R_AARCH64_PREL32 relocations.
In this PR:
1. Ensure that on AArch64, lookup table operands do not need dynamic
relocations. If the lookup table were in `.rodata` (text segment), then
any of the target components would need to be in the data segment, so
the dynamic reloc check would suffice.
2. Re-enable RelLookupTableConverter for AArch64 (while keeping Darwin
disabled as before).
3. Limit the existing `AArch64/no_relative_lookup_table.ll` test to just
darwin aarch64.
4. Move the `X86/relative_lookup_table.ll` into the parent dir since
those checks are (mostly) generic, and allow those same checks to be run
for aarch64. That also includes a minor refactor for not checking the
`unnamed_addr` bit since `unnamed_addr` is
[dropped](https://github.com/llvm/llvm-project/blob/6959b7d081df5fb2349e67e0d8e8e87841fa10d9/llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp#L82)
for aarch64.
AI: Gemini was used to help make this patch and debug the issue. I
reviewed this PR to the best of my ability before submitting.
Commit: f471750e042c5da3daf947169c0125e58300df0d
https://github.com/llvm/llvm-project/commit/f471750e042c5da3daf947169c0125e58300df0d
Author: Andy Kaylor <akaylor at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/docs/CIR/CleanupAndEHDesign.md
Log Message:
-----------
[CIR] Document dynamic exception specification design (#222451)
This change adds documentation for the CIR handling of dynamic exception
specification handling in pre-C++17 code. This is not yet implemented.
The implementation will follow in a series of changes based on this
design.
This documentation was generated by Claude Opus 5, based on an
interactive planning session in which I worked out the details of how I
want to implement this feature. I have carefully read the entire
document to verify that it correctly matches my intended implementation.
Commit: 5b1d7415a6cf8f4799b4f586417346abf0c56e84
https://github.com/llvm/llvm-project/commit/5b1d7415a6cf8f4799b4f586417346abf0c56e84
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A flang/include/flang/Optimizer/Builder/Runtime/CUDA/Support.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
A flang/lib/Optimizer/Builder/Runtime/CUDA/Support.cpp
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
Log Message:
-----------
[flang][cuda] Synchronize context before finalization (#223058)
Commit: e471938cf2c9647a33458eed6ad5647b6323d153
https://github.com/llvm/llvm-project/commit/e471938cf2c9647a33458eed6ad5647b6323d153
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A llvm/test/Transforms/AggressiveInstCombine/RISCV/lit.local.cfg
Log Message:
-----------
[AggressiveInstCombine] Add lit.local.cfg to RISCV test directory. NFC (#223067)
To fix buildbot failures after #220310.
Commit: fe36473cb62cca28c14b7174c0797cb74bcdfc7e
https://github.com/llvm/llvm-project/commit/fe36473cb62cca28c14b7174c0797cb74bcdfc7e
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
Log Message:
-----------
[CIR][AMDGPU] Let amdgcn_lerp and ds_swizzle use the generic codegen path (#222204)
__builtin_amdgcn_lerp and __builtin_amdgcn_ds_swizzle both map 1:1 onto
concrete (non-overloaded) intrinsics and carry the ClangBuiltin<> marker
in IntrinsicsAMDGPU.td, so EmitBuiltinExpr already lowers them
automatically by forwarding the arguments to the intrinsic.
Commit: bb962e790106c624e0668118d0b7d92c706c2da4
https://github.com/llvm/llvm-project/commit/bb962e790106c624e0668118d0b7d92c706c2da4
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/include/CMakeLists.txt
A orc-rt/include/orc-rt/bedrock/SocketHandle.h
M orc-rt/lib/bedrock/CMakeLists.txt
A orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/bedrock/SocketHandleTest.cpp
A orc-rt/test/unit/bedrock/SocketTestUtils.h
A orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
Log Message:
-----------
[orc-rt] Add SocketHandle, NativeSocketHandle APIs (#223114)
SocketHandle is an owning wrapper for a NativeSocketHandle value, and
closes the native socket on destruction.
NativeSocketHandle is a typedef for the platform's native socket handle
type.
Only POSIX is implemented in this patch (in sys/posix/SocketHandle.cpp).
Windows support will be added later.
This will be used for an upcoming SimpleRemote-based ControllerAccess
implementation that uses sockets for transport (SocketSimpleRemoteCA).
Commit: 25fe99bf939c50c7064e714a7edcbeb445bb9dc1
https://github.com/llvm/llvm-project/commit/25fe99bf939c50c7064e714a7edcbeb445bb9dc1
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.cpp
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
Log Message:
-----------
[ORC] Retire rt::SimpleExecutorMemoryManager* for sps_ci (#223113)
Move all clients to the sps_ci SimpleNativeMemoryMap / MemMgr
counterparts and retire the old rt::SimpleExecutorMemoryManager*
interface names.
Commit: 64a6af1666c9bbb63eb86c0697a3709a4cca8e50
https://github.com/llvm/llvm-project/commit/64a6af1666c9bbb63eb86c0697a3709a4cca8e50
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
A clang/test/CIR/IR/invalid-version.cir
A clang/test/CIR/IR/version.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
Log Message:
-----------
[CIR][OpenCL] Add OpenCL language version module attributes (#219687)
Add structured CIR module attributes for OpenCL and C++ for OpenCL
language versions. Verify their module-level placement and version
components so lowering can consume explicit source-language version
state.
Assisted-by: Codex / GPT-5.6 Sol
Commit: ba3010d7e4520b6aee926f878c5c1771f1c2a6f3
https://github.com/llvm/llvm-project/commit/ba3010d7e4520b6aee926f878c5c1771f1c2a6f3
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
A clang/test/CIR/CodeGenOpenCL/version.cl
M clang/test/CodeGenCUDASPIRV/kernel-cc.cu
M clang/test/CodeGenHIP/hipspv-kernel.cpp
A clang/test/SemaHIP/atomic-init.hip
Log Message:
-----------
[CIR][OpenCL] Emit OpenCL language version metadata in CIR (#219688)
Emit OpenCL and C++ for OpenCL language version attributes from CIRGen.
Preserve the compatible OpenCL version and the C++ for OpenCL version
separately so later lowering does not infer one from the other.
Assisted-by: Codex / GPT-5.6 Sol
Commit: 070455b3f2f77dbd1d5121a9d1bc3d9a3e3f65bc
https://github.com/llvm/llvm-project/commit/070455b3f2f77dbd1d5121a9d1bc3d9a3e3f65bc
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/readability/convert-member-functions-to-static.cpp
Log Message:
-----------
[clang-tidy] Fix convert-member-functions-to-static crash on attributed methods (#223007)
Fixes #222951
Commit: 78f557806dca9c81453e94c038409fb9ad49d063
https://github.com/llvm/llvm-project/commit/78f557806dca9c81453e94c038409fb9ad49d063
Author: shivaramaarao <58245296+shivaramaarao at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
A flang/test/Lower/OpenMP/omp-lib-integer-wrappers.f90
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M openmp/device/include/Interface.h
M openmp/device/src/State.cpp
M openmp/module/omp_lib.F90.var
M openmp/runtime/src/dllexports
M openmp/runtime/src/include/omp.h.var
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_csupport.cpp
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_ftn_os.h
M openmp/runtime/src/kmp_stub.cpp
A openmp/runtime/test/api/kmp_integer_8_apis.f90
Log Message:
-----------
[OpenMP] [Flang] Add Fortran integer(kind=8) overloads for omp_lib APIs (#221451)
Fortran code that uses integer(8) arguments, including
-fdefault-integer-8, did not match omp_lib interfaces declared with
omp_integer_kind (typically kind 4). Added *_8 specific procedures to
named generic interfaces in omp_lib, exported matching Fortran and C
runtime entry points, and implemented the *_8 functions as thin wrappers
that saturate-convert arguments to 32-bit and call the existing APIs.
Commit: a67c8f208e8710ad8b6b6e2ca4de57e4e0db7178
https://github.com/llvm/llvm-project/commit/a67c8f208e8710ad8b6b6e2ca4de57e4e0db7178
Author: Kaviya Rajendiran <67495422+kaviya2510 at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/frame-pointer-forwarding.f90
A flang/test/Transforms/function-attr-frame-pointer.fir
Log Message:
-----------
[Flang][Driver]Implemented support for option -momit-leaf-frame-pointer/-mno-omit-leaf-frame-pointer in flang (#216700)
Added support for `-momit-leaf-frame-pointer` /
`-mno-omit-leaf-frame-pointer` in the Flang compiler.
- The driver resolves the flags via `getFramePointerKind()` and forwards
`-mframe-pointer=<kind>` to flang -fc1, resulting in the LLVM IR
function attribute "frame-pointer"
- These options, used with `-fno-omit-frame-pointer`, control whether
leaf functions (functions that don't call other functions) retain or
omit the frame pointer.
- `fno-omit-frame-pointer -momit-leaf-frame-pointe`r : Keep the frame
pointer in non-leaf functions, but omit it in leaf functions (produces
"frame-pointer"="non-leaf").
- `fno-omit-frame-pointer -mno-omit-leaf-frame-pointe`r : Keep the frame
pointer in all functions, including leaf functions (produces
"frame-pointer"="all").
Commit: 4388400c3d0a95b75a36f81c7edd2eb95c6d63ea
https://github.com/llvm/llvm-project/commit/4388400c3d0a95b75a36f81c7edd2eb95c6d63ea
Author: Benjamin Chetioui <3920784+bchetioui at users.noreply.github.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/test/IR/invalid-builtin-types.mlir
M mlir/test/IR/parser.mlir
Log Message:
-----------
[mlir] Remove the memory space attribute restriction on memref types (#222995)
Follow-up to #187682. `isSupportedMemorySpace` only rejected builtin
attributes other than IntegerAttr/StringAttr/DictionaryAttr. This is a
leftover from when memory spaces were restricted to integers, and is now
inconsistent.
Commit: eff88db8f004bf74c54c65bd39a3fc2fb27969f0
https://github.com/llvm/llvm-project/commit/eff88db8f004bf74c54c65bd39a3fc2fb27969f0
Author: Akimasa Watanuki <mencotton0410 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.h
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
M clang/test/CIR/CodeGenOpenCL/version.cl
A clang/test/CIR/Lowering/opencl-version-metadata.cir
Log Message:
-----------
[CIR][OpenCL] Lower OpenCL language version metadata to LLVM dialect (#219689)
Propagate CIR OpenCL language version module attributes as LLVM dialect
named metadata before LLVM IR translation.
Assisted-by: Codex / GPT-5.6 Sol
Commit: cebfe6c25f45c81f7be238c835828b97f48730ab
https://github.com/llvm/llvm-project/commit/cebfe6c25f45c81f7be238c835828b97f48730ab
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/IR/Verifier.cpp
A llvm/test/Assembler/llvm.loop.align.ll
A llvm/test/Verifier/llvm.loop.align.ll
Log Message:
-----------
IR: Add verifier checks and LangRef for llvm.loop.align (#221933)
Verify the nested !{!"llvm.loop.align", i32 N} tag.
Require exactly two operands, an integer constant of type i32 or
smaller, and a positive power-of-two value
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: 1f13035dd3bec940226402c59bbb086ab703caeb
https://github.com/llvm/llvm-project/commit/1f13035dd3bec940226402c59bbb086ab703caeb
Author: A. Jiang <de34 at live.cn>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libcxx/docs/Status/Cxx26Issues.csv
A libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.verify.cpp
Log Message:
-----------
[libc++] Test LWG4113: Disallow `has_unique_object_representations<Incomplete[]>` (#169446)
We have been rejecting `has_unique_object_representations<Incomplete[]>`
since LLVM 6.
Some related change landed in Clang 19 due to
6451806ef73bb033be3f6e1599f3bcb224943206, and then a follow-up change
ae9990ed965118e7274a52399b43e3b9fb419a54 simplified error messages.
Test coverage for incomplete enumeration types is skipped for Clang-cl
mode, because an incomplete enumeration type is incorrectly considered
to be complete. See https://llvm.org/PR169472.
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 25728f8e380096df53f3aa966068ec3a24271b30
https://github.com/llvm/llvm-project/commit/25728f8e380096df53f3aa966068ec3a24271b30
Author: Tomer Shafir <tomer.shafir8 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
A llvm/test/CodeGen/AArch64/misched-postra-only1.mir
Log Message:
-----------
[MISched] Fix post-RA pickOnlyChoice debug logs (#222927)
On the way, adding a stable test for `pickOnlyChoice()` scheduling paths
directly, which has been missing, while filechecking the fixed tracing.
Commit: cad1b33322a4000bad6974b4c40ee5bff987eb89
https://github.com/llvm/llvm-project/commit/cad1b33322a4000bad6974b4c40ee5bff987eb89
Author: lntue <lntue at google.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
Log Message:
-----------
[libc] Pass correct system include flag for macOS. (#223116)
Commit: e17b8cb5341d42f805c538236771edafa737a87e
https://github.com/llvm/llvm-project/commit/e17b8cb5341d42f805c538236771edafa737a87e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/LangRef.md
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/TargetParser/Triple.cpp
A llvm/test/Assembler/module-flags-thread-model.ll
A llvm/test/Linker/module-flags-thread-model.ll
A llvm/test/Verifier/module-flags-thread-model.ll
Log Message:
-----------
IR: Introduce "thread-model" module flag (#222768)
Introduce the replacement for TargetOptions::ThreadModel, but
does not yet wire up the uses. This maintains the current values,
but I question if it makes sense to retain "posix" as the default.
POSIX sounds very target opinionated, but isn't used in a non-binary
way anywhere. Alternatively we could have a simple singlethread binary
flag, or name this something more general.
Follows the precedent of float-abi. It happens the triple default
is just POSIX, but theoretically targets like AVR should be defaulting
to singlethread.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Commit: 2706780356665d560cc5a38dee91e7377a6d6002
https://github.com/llvm/llvm-project/commit/2706780356665d560cc5a38dee91e7377a6d6002
Author: Andreas Jonson <andjo403 at hotmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
Log Message:
-----------
[InstCombine] support trunc condition in foldSelectICmpAndAnd (#223132)
Reland https://github.com/llvm/llvm-project/pull/220690 with the fix for
asan failure see fixup commit
Commit: d41121260c37b1be088995b375d074f198942114
https://github.com/llvm/llvm-project/commit/d41121260c37b1be088995b375d074f198942114
Author: Jesse Huang <jesse.huang at sifive.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/MC/RISCV/tail-call.s
Log Message:
-----------
[RISCV] Add PseudoTAILX7, PseudoTAILReg for cf-protection-branch (#220657)
Previously, PseudoTAIL selected between X6 and X7 at encode time by
checking the Zicfilp feature bit via getTailExpandUseRegNo. This is
incorrect for the codegen path because -fcf-protection=branch can emit
lpad without requiring Zicfilp to be enabled.
Add PseudoTAILX7 for codegen: when cf-protection-branch is active,
ISelLowering and the machine outliner now emit PseudoTAILX7 which
always expands using X7. The existing PseudoTAIL behavior is unchanged
— it still selects X6 or X7 based on Zicfilp at encode time, as
documented in the assembler manual.
Also add PseudoTAILReg ("tail address, register") assembly form that
lets users explicitly specify the scratch register for AUIPC+JALR
expansion, per the proposed syntax in
https://github.com/riscv-non-isa/riscv-asm-manual/pull/227.
Commit: 3569a1f1d2cee5616a15a992ca49646447efaa47
https://github.com/llvm/llvm-project/commit/3569a1f1d2cee5616a15a992ca49646447efaa47
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
Log Message:
-----------
[AMDGPU] Fix placement of FeatureSupportsXNACK (#223111)
This can't be put into 12_50_Common because of conflict in downstream
code.
Commit: 5eff11f8e9b56b1653950409355d829f48547127
https://github.com/llvm/llvm-project/commit/5eff11f8e9b56b1653950409355d829f48547127
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
M orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
Log Message:
-----------
[orc-rt] Reduce SimpleRemoteCA to transport-independent utils (#223141)
Reduce SimpleRemoteCA to the transport-independent parts: opcodes, setup
and hang-up payload encoding, message validation and dispatch, and the
table of calls awaiting a result. Subclasses are now responsible for the
connection state and synchronization, since they'll usually want to
implement these things for their transports anyway (or the transport
will already manage connection-state/synchronization).
takePendingCall becomes pure virtual, since subclasses must synchronize
access to the pending-call table.
The header moves from orc-rt-internal/ to orc-rt/: with the transport a
subclass concern, there's no reason to preclude library clients from
writing one.
Commit: 1ae00a52bbe432ff8174664ce28fb33cc600f6f0
https://github.com/llvm/llvm-project/commit/1ae00a52bbe432ff8174664ce28fb33cc600f6f0
Author: Zorojuro <sawantsukumar at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M libc/src/__support/FPUtil/float80.h
Log Message:
-----------
[libc] Enable Float80-type for x86_32 (#221408)
Enables for x86_32 by using Uint<96>
```CPP
struct Float80 {
#if __SIZEOF_LONG_DOUBLE__ == 12
UInt<96> bits;
#else
UInt128 bits;
#endif
```
for testing it on x86_32
it needs -m32 and --msse2 extra flags other than your usual cmake for x86_32
Commit: 0adddbb3a5f7f57614e8c59c87d37cec5421e514
https://github.com/llvm/llvm-project/commit/0adddbb3a5f7f57614e8c59c87d37cec5421e514
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
Log Message:
-----------
[clang][bytecode][NFC] Move Remove unused CheckExtern prototype (#223146)
And add an overload taking only a Block.
Commit: 66573c1ecdc0ce1dc5f1cbd7d22974a7eb4ccf5d
https://github.com/llvm/llvm-project/commit/66573c1ecdc0ce1dc5f1cbd7d22974a7eb4ccf5d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ScalarEvolution.cpp
A llvm/test/Analysis/ScalarEvolution/pointer-iv-addrec.ll
Log Message:
-----------
[SCEV] Directly form add recurrences for simple pointer IVs. (#222915)
Add support for PN = PHI(Start, gep Self, LoopInvariant) to
createSimpleAffineAddRec.
This allows to handle simple pointer IVs without going through the more
expensive createAddRecFromPHI machinery in many cases.
This is not completely NFC: previously we created SCEVUnknown for a
trivial AddRec with step 0, now we return the start value.
This gives a modest geomean compile-time decrease
* stage1-O3: -0.05%
* stage1-ReleaseThinLTO: -0.06%
* stage1-ReleaseLTO-g: -0.06%
* stage1-aarch64-O3: -0.07%
* stage2-O3: -0.05%
* clang build: -0.08%
With larger decreases for more SCEV-heavy workloads.
https://llvm-compile-time-tracker.com/compare.php?from=c1b661fde124399f0484c4b39501b37613cc4757&to=5cd19e23596c86eae9607286efe86b7a3e885a86&stat=instructions:u
PR: https://github.com/llvm/llvm-project/pull/222915
Commit: e1b6027992df8846729ebfaacc9d3ac8573dd106
https://github.com/llvm/llvm-project/commit/e1b6027992df8846729ebfaacc9d3ac8573dd106
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/Transforms/LoopVectorize/induction-cost.ll
Log Message:
-----------
[LV] Add test for cost of widened pointer induction (NFC). (#223153)
Add a cost test where the pointer induction is used as a value and
remains a VPWidenPointerInductionRecipe.
PR: https://github.com/llvm/llvm-project/pull/223153
Commit: 345d699de809ee2962307df4ae0bd95f791275b3
https://github.com/llvm/llvm-project/commit/345d699de809ee2962307df4ae0bd95f791275b3
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[SelectionDAG] Remove dead functions and declarations (NFC) (#223126)
SelectionDAG::getStore (with Offset): Added on July 31, 2026 in commit
c57b2b6103cb4bb6c4c2bee901c1eee2b966e5f0 without a definition or any
callers.
SelectionDAG::getIndexedLoadVP, SelectionDAG::getIndexedStoreVP: Added
on August 31, 2021 in commit 524ded7d01a700aa6473d09a877be13fe45b85a3
without any callers.
SelectionDAG::getTruncStridedStoreVP: Added on March 10, 2022 in commit
28cfa764c2e3d36b856b3e70d49f17088b90c1f5 without any callers.
Assisted-by: Antigravity
Commit: d7d7992e58674a2e9ad1ae42e4a627b7fff24cef
https://github.com/llvm/llvm-project/commit/d7d7992e58674a2e9ad1ae42e4a627b7fff24cef
Author: Zhige Chen <zhige_chen at outlook.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/test/tools/llubi/fp_cast.ll
M llvm/tools/llubi/lib/Interpreter.cpp
Log Message:
-----------
[llubi] Implement fast-math flags for `uitofp`/`sitofp` (#222858)
Closes #203773
Commit: eb9844b5ceee01c9d9fad92cbcd027c5798c5ed4
https://github.com/llvm/llvm-project/commit/eb9844b5ceee01c9d9fad92cbcd027c5798c5ed4
Author: Hamed <hamedghorbani17 at live.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/test/CodeGen/ms-setjmp.c
Log Message:
-----------
[clang][ARM] Use sponentry for setjmp on Windows ARM32 (#222366)
On Windows, _setjmp and _setjmpex take a second argument, the frame,
which the CRT stores in the jmp_buf and which longjmp later hands to
RtlUnwindEx as the frame to unwind. On aarch64, this is the stack pointer
on entry to the function, while x86_64 takes the function frame address.
ARM expects the same as aarch64 here, the stack pointer on entry.
Assisted-by: Claude Opus 5 (Anthropic)
Commit: 148ee2b266b73a49f1f31d0bd17d4818b91bee9f
https://github.com/llvm/llvm-project/commit/148ee2b266b73a49f1f31d0bd17d4818b91bee9f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps.ll
Log Message:
-----------
[SLP] Fix dep accounting when cancelling a bundle with copyable elements
Restore the parent-edge copyable data as a user of the instruction only
if the cancelled element displaced it at creation (chained copyable
self-use); otherwise the extra user dependency is never released and
scheduling asserts.
Fixes #223139
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223174
Commit: ca8f82b625494996d4f9f61f30d25b62a5660dca
https://github.com/llvm/llvm-project/commit/ca8f82b625494996d4f9f61f30d25b62a5660dca
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Support/KnownFPClass.cpp
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/unittests/Support/KnownFPClassTest.cpp
Log Message:
-----------
[KnownFPClass] Restrict KnownFPClass::bitcast/toKnownBits deductions to verified FP semantics (#221133)
`KnownFPClass::bitcast` and `KnownFPClass::toKnownBits` previously made
deductions for floating-point semantics whose bit representations had
not been verified.
I have made it so `KnownFPClass::bitcast` and
`KnownFPClass::toKnownBits` return `fcAllFlags`/unknown for any
`APFloat` semantics we have not verified. Currently, this prevents
potentially invalid deductions for `PPCDoubleDouble` (mostly in regards
to the signbit and endianess). It also allows these functions to be
"safely" used with the 4/6/8 bit floating point types since we
conservatively return unknown.
Currently the list of supported/verified semantics for both `bitcast`
and `toKnownBits` are:
```
IEEEhalf
BFloat
IEEEsingle
IEEEdouble
IEEEquad
x87DoubleExtended
```
Commit: d65afea7b5c25b7be41dd86eaedaac263f04cd40
https://github.com/llvm/llvm-project/commit/d65afea7b5c25b7be41dd86eaedaac263f04cd40
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
Log Message:
-----------
[gn build] Port 0f47e798205b (#223189)
Commit: b6ca452aea0d805fd1f2f98a609e30692184a5bf
https://github.com/llvm/llvm-project/commit/b6ca452aea0d805fd1f2f98a609e30692184a5bf
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
Log Message:
-----------
[gn build] Port 4214b4601f49 (#223190)
Commit: 5d188c401f7d64daf08b7aac887d93aa5073e1dd
https://github.com/llvm/llvm-project/commit/5d188c401f7d64daf08b7aac887d93aa5073e1dd
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
Log Message:
-----------
[ELF] Version scripts: simplify version suffix handling. NFC (#223194)
Use StringRef::split instead of index arithmetic.
Commit: 387c965bb013d14dbcee52098e714c27d6f98249
https://github.com/llvm/llvm-project/commit/387c965bb013d14dbcee52098e714c27d6f98249
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
R lld/test/ELF/dynamic-list-cpp.s
M lld/test/ELF/dynamic-list-glob.s
R lld/test/ELF/version-script-reassign-glob.s
A lld/test/ELF/version-script-wildcard-precedence.s
Log Message:
-----------
[ELF,test] Cover wildcard precedence in version scripts and dynamic lists (#223195)
version-script-wildcard-precedence.s, renamed from
version-script-reassign-glob.s, covers more cases.
dynamic-list-glob.s absorbs dynamic-list-cpp.s and adds an extern "C++"
wildcard, which had no --dynamic-list coverage.
Commit: 474b7358a90e4f22b04e6a0933381d239fb7044e
https://github.com/llvm/llvm-project/commit/474b7358a90e4f22b04e6a0933381d239fb7044e
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/tools/llc/CMakeLists.txt
R llvm/tools/llc/NewPMDriver.cpp
R llvm/tools/llc/NewPMDriver.h
A llvm/tools/llc/lib/CMakeLists.txt
A llvm/tools/llc/lib/NewPMDriver.cpp
A llvm/tools/llc/lib/NewPMDriver.h
A llvm/tools/llc/lib/llcdriver.cpp
R llvm/tools/llc/llcdriver.cpp
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[llc] Move LLVMLlcDriver implementation into lib (#222840)
Addressing comment
[here](https://github.com/llvm/llvm-project/pull/221896#discussion_r3982250858)
Commit: 745ff71c706f6a55c7fa1cda660860925e0b2739
https://github.com/llvm/llvm-project/commit/745ff71c706f6a55c7fa1cda660860925e0b2739
Author: Craig Topper <craig.topper at sifive.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Log Message:
-----------
[RISCV] Consistently use RISCVSubtarget::is64Bit() instead of isRV32/isRV64. (#223038)
99% of code uses RISCVSubtarget::is64Bit().
Maybe we should consider removing is64Bit(), and using isRV64() instead
but right now I think we should be consistent.
Commit: 7a7cea921c3e450903b57e5f4b2992f1dce4c410
https://github.com/llvm/llvm-project/commit/7a7cea921c3e450903b57e5f4b2992f1dce4c410
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
Log Message:
-----------
[ELF] Version script: simplify wildcard matching. NFC (#223202)
Replace a loop over non-"*" wildcard patterns and another loop over "*"
with a single loop that calls the inlined
`SymbolTable::assignWildcardVersion`.
Commit: 051c49202368a8478661548b5b8de03549d9d183
https://github.com/llvm/llvm-project/commit/051c49202368a8478661548b5b8de03549d9d183
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/test/SemaCXX/ms-ctor-closure.cpp
Log Message:
-----------
[clang][test] Remove an uninitialized read in a test case (#223120)
This test case was added in
https://github.com/llvm/llvm-project/pull/222212. Its purpose is to
check that explicit constructor calls work at compile time.
However, the test case left var.a uninitialized and the copy constructor
reads an unitialized value. MSVC diagnoses this, but clang currently
fails to do so.
Change the test case to remove the unrelated problem of an uninitialized
read.
Commit: 0d55d0bf81ce2e0d6d3c46b7835efb788bde634a
https://github.com/llvm/llvm-project/commit/0d55d0bf81ce2e0d6d3c46b7835efb788bde634a
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lld/ELF/ICF.cpp
Log Message:
-----------
[ELF] Parallelize ICF's section sort. NFC (#223216)
All candidate sections are sorted by a serial stable_sort, which is a
scalability bottleneck. Switch to parallel sort using Schwartzian
transform. Linking Chromium with --icf=all (--threads=8) drops from
4.47s to 3.18s.
Commit: 8ea78db3c1bf6522ccaf6d75e73a03d80f08a00b
https://github.com/llvm/llvm-project/commit/8ea78db3c1bf6522ccaf6d75e73a03d80f08a00b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Options/Options.td
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/Driver/wasm-toolchain.c
Log Message:
-----------
clang/WebAssembly: Add -femscripten-exceptions driver flag (#221431)
Commit: c4628f0385efd0d0d3c9d9ee0b88f89fdd4bd1f3
https://github.com/llvm/llvm-project/commit/c4628f0385efd0d0d3c9d9ee0b88f89fdd4bd1f3
Author: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/cmake/modules/HandleLLVMOptions.cmake
Log Message:
-----------
[CMake] Disable linker version scripts for Emscripten (#221647)
Emscripten reports itself as a Unix-like CMake platform, causing LLVM to
set `LLVM_HAVE_LINK_VERSION_SCRIPT` and pass GNU/ELF `--version-script`
options when linking shared libraries.
Emscripten uses `wasm-ld`, which does not support GNU version scripts
and currently reports:
```
em++: warning: ignoring unsupported linker flag: `--version-script`
```
Treat Emscripten like the other platforms without version-script
support. This prevents LLVM and Clang shared-library targets from
passing an unsupported linker option.
This was encountered while building LLVM 23.1.0 for both wasm32 and
wasm64 with Emscripten 6.x in emscripten-forge.
```
[ 45%] Building CXX object tools/clang/lib/Sema/CMakeFiles/obj.clangSema.dir/SemaExceptionSpec.cpp.o
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
.....
[100%] Linking CXX shared library ../../lib/libLTO.so
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
.....
[100%] Linking CXX shared library ../../../../lib/libclang.so
em++: warning: ignoring unsupported linker flag: `--version-script` [-Wlinkflags]
```
Commit: 4dd595b99e4e0a9c7994726065ab99d6c2b071c2
https://github.com/llvm/llvm-project/commit/4dd595b99e4e0a9c7994726065ab99d6c2b071c2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
Log Message:
-----------
Wasm: Remove incorrect assumption that intrinsics cannot throw (#221180)
A few intrinsics are marked as Throws
Commit: 709ef4b96668471c7be0bd67abece4ebfce62a22
https://github.com/llvm/llvm-project/commit/709ef4b96668471c7be0bd67abece4ebfce62a22
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
A llvm/test/CodeGen/ARM/cbz-no-kill-flag.mir
Log Message:
-----------
ARM: Avoid relying on kill flags for determining CPSR liveness (#222873)
When forming CBZ/CBNZ in ARMConstantIslands, check if CPSR is live-out
of the block instead of relying on the kill flag. Kill flags have been
soft deprecated for over a decade.
Co-authored-by: Claude claude-opus-4.8 <noreply at anthropic.com>
Commit: 31a1c03fe67cccd917f11e5ab50cc425770c1400
https://github.com/llvm/llvm-project/commit/31a1c03fe67cccd917f11e5ab50cc425770c1400
Author: Brad Smith <brad at comstyle.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/Unix/Path.inc
Log Message:
-----------
[Support] Implement getMainExecutable for OpenBSD with getexecpath() (#220141)
OpenBSD now has a proper function to retrieve the executable and path.
Commit: eae1ec7b1d6752d7d94214e4beaf724ce560aed2
https://github.com/llvm/llvm-project/commit/eae1ec7b1d6752d7d94214e4beaf724ce560aed2
Author: Pkuyo <miku_mi at foxmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
Log Message:
-----------
[SelectionDAG] Handle scalable INSERT_SUBVECTOR in ComputeNumSignBits (#221631)
Handle scalable INSERT_SUBVECTOR in SelectionDAG as a pre-fix for
#220976.
Add coverage for scalable subvectors and fixed subvectors inserted into
scalable vectors.
Commit: 3deeb018ed1d1c61ad9e1798161128e0202e7920
https://github.com/llvm/llvm-project/commit/3deeb018ed1d1c61ad9e1798161128e0202e7920
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps-2.ll
Log Message:
-----------
[SLP]Fix dep accounting when cancelling a bundle with repeated copyable users
Skip duplicate users instead of stopping at the first one when walking
the operand lanes; an early stop misses a trailing self-use lane, the
displaced parent-edge copyable data is never restored, and scheduling
asserts.
Fixes #223225
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223236
Commit: f8a96032096158c992ea4cd369e43068b2b072a7
https://github.com/llvm/llvm-project/commit/f8a96032096158c992ea4cd369e43068b2b072a7
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
Log Message:
-----------
[lldb] Bound Mach-O symtab allocation to the file size (#222955)
Opening a Mach-O file whose LC_SYMTAB claims far more symbols than the
file could possibly hold makes lldb ask for hundreds of gigabytes. A
128-byte file with LC_SYMTAB.nsyms = 0x80000000 (the new unit test's
input, built with yaml2obj) reproduces it through `lldb-target-fuzzer`,
the harness that found this bug:
```
==45515== ERROR: libFuzzer: out-of-memory (malloc(171798691840))
#8 std::__1::__split_buffer<lldb_private::Symbol,...>::__split_buffer(...)
#9 std::__1::vector<lldb_private::Symbol,...>::resize(unsigned long)
#10 lldb_private::Symtab::Resize(unsigned long)
#11 ObjectFileMachO::ParseSymtab(lldb_private::Symtab&)
```
`ParseSymtab()` sizes the destination `Symtab`'s `vector<Symbol>`
directly
from `nsyms` and `nindirectsyms`, two counts read from the file's
`LC_SYMTAB` and `LC_DYSYMTAB` commands. `nlist_data`, the view already
built earlier in the function from the bytes the file actually has at
`symoff`, is far smaller than what those counts claim; the guard gating
this code only checks that it is non-empty, not how many nlist records
it can back.
Bound both counts by what `nlist_data` and `indirect_symbol_index_data`
(already clipped to the available bytes) can hold, instead of trusting
the file's counts outright.
Add a unit test whose LC_SYMTAB claims about two billion symbols in a
128-byte file; completing quickly instead of reserving that much space
is the regression check.
Assited-by: claude
Commit: 3c77eb3a3f2793a75e0ce86d96076637d5989bea
https://github.com/llvm/llvm-project/commit/3c77eb3a3f2793a75e0ce86d96076637d5989bea
Author: Stanislav Bardyuk <6258615+kodlan at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
Log Message:
-----------
[DAGCombiner] Only fold shift+mask compare to rotate if the shift amount divides the bit width (#220743)
DAGCombiner::visitSETCC can turn `(X << S) == (X & -(1 << S))` (or the
srl variant) into `rotl(X, S) == X`, and the other way around, when the
target prefers one form over the other. The two forms are only equivalent when
S divides the bit width. The check used `isPowerOf2(S)`, which is the same
thing for i8/i16/i32/i64 but not for odd widths like i3, where S = 2 is a
power of two that does not divide 3. On x86, which prefers the rotate,
the reporter's i3 function returned the wrong value for two of its eight
inputs.
This changes the `MayTransformRotate` flag passed to
`preferedOpcodeForCmpEqPiecesOfOperand` to check `NumBits % S == 0`
(with S != 0) and fixes the two comments that described the old rule. For legal
scalar types nothing changes. On illegal non power of two widths this
also lets a non power of two amount that divides the width use the rotate
(like i6 with S = 3); that is correct for the same reason and legalizes
through the usual rotate promotion, same as i6 with S = 2 did before. The x86
hook already honors the flag in both directions, so the fix lives in the
target independent code.
Tests: the i3 shl and lshr cases from the issue (must stay shift+mask), an
i6 / S = 3 case (3 divides 6, so the rotate is still allowed), and the
reporter's function.
Fixes #220542
Commit: baec9c34d1ecdbabca0cc100ed6de73986174938
https://github.com/llvm/llvm-project/commit/baec9c34d1ecdbabca0cc100ed6de73986174938
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
Log Message:
-----------
[AMDGPU] Fix fneg fold with multi use fadd/fma (#217573)
Commit: db65ace07649b2beb8cdbdfd6af4901809df9966
https://github.com/llvm/llvm-project/commit/db65ace07649b2beb8cdbdfd6af4901809df9966
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/docs/ReleaseNotes.md
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaTemplate/concepts-lambda.cpp
Log Message:
-----------
Revert "[Clang] Refactor instantiation of declarations within concepts" (#223235)
This reverts llvm/llvm-project#221707
This broke std::map as reported in
https://github.com/llvm/llvm-project/issues/223220
Commit: d283a555109576cd92b35a88b4d110166043fb77
https://github.com/llvm/llvm-project/commit/d283a555109576cd92b35a88b4d110166043fb77
Author: Joseph Huber <huberjn at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/test/OffloadTools/clang-nvlink-wrapper/nvlink-wrapper.c
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
Log Message:
-----------
[clang-nvlink-wrapper] Fix response file handling for the nvlink wrapper (#220249)
Summary:
Response files were not handled correctly because the copied support
used the `nvlink` argument which is not supported by the argument
parser. Pass to the nvlink wrapper using the canonical format and then
reconstruct it when we execute the sub jobs
Fixes: https://github.com/llvm/llvm-project/issues/219914
Commit: 3409d079b5b76d0cdd51526b29aebd4143ecca64
https://github.com/llvm/llvm-project/commit/3409d079b5b76d0cdd51526b29aebd4143ecca64
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
Log Message:
-----------
[SLP][NFC]Add a test with missed widened boolean optimization, NFC
Reviewers:
Pull Request: https://github.com/llvm/llvm-project/pull/223245
Commit: ca2424325cd9247ac0c11cd2d1c8ea3fb07ab16e
https://github.com/llvm/llvm-project/commit/ca2424325cd9247ac0c11cd2d1c8ea3fb07ab16e
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
Log Message:
-----------
[AMDGPU][GlobalISel] Reject guaranteed tail calls in call lowering (#216260)
The FPDiff immediate was being written to the wrong operand, corrupting
the callee GlobalAddress
Reject required tail calls like SelectionDAG does, and fix the stale
index for the one path that still needs it (cs.chain lowering)
Commit: 0c324f10322b490d66de738d73458f6f65460cdb
https://github.com/llvm/llvm-project/commit/0c324f10322b490d66de738d73458f6f65460cdb
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/MathExtras.h
Log Message:
-----------
[Support] Fix the return type of AddOverflow, SubOverflow, and MulOverflow (#223217)
This patch fixes the return type of the 3-argument overloads of
AddOverflow, SubOverflow, and MulOverflow to bool.
Without this patch, these functions are declared with a return type
of T:
template <typename T>
std::enable_if_t<std::is_signed_v<T>, T> AddOverflow(T X, T Y, T
&Result);
even though they return a boolean indicating whether an overflow
occurred, as stated in the comment:
/// Add two signed integers, computing the two's complement truncated
result,
/// returning true if overflow occurred.
Assisted-by: Antigravity
Commit: 23f2e449afa0b0de43939a03ea241bc17dfe1141
https://github.com/llvm/llvm-project/commit/23f2e449afa0b0de43939a03ea241bc17dfe1141
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
Log Message:
-----------
[SelectionDAG] Remove unused float promotion in DAGTypeLegalizer (NFC) (#223219)
This patch removes PromotedFloats along with GetPromotedFloat and
SetPromotedFloat. The Mapped bitmask in PerformExpensiveChecks is
adjusted accordingly, shifting the bit for SoftPromotedHalfs.
The last uses of DAGTypeLegalizer::GetPromotedFloat and
DAGTypeLegalizer::SetPromotedFloat were removed on January 26, 2026 in
commit a7d48bd305ef3aa4bd543da6f4cd8682a3d35c32 when TypePromoteFloat
and its associated DAG machinery were removed.
With these accessors gone, DAGTypeLegalizer::PromotedFloats is no longer
populated.
Assisted-by: Antigravity
Commit: c67808cf4426290e259f2cd4bd1a48516f9b8d7b
https://github.com/llvm/llvm-project/commit/c67808cf4426290e259f2cd4bd1a48516f9b8d7b
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
Log Message:
-----------
[OpenMP] Change association of some directives from "none" to "explicit" (#222703)
Certain declarative directives are associated with base language
declarations by having the declared entities explicitly listed as
arguments.
Previously these had "none" in OMP.td. Change them to "explicit" to be
consistent with the spec. The existing code does not require any
changes, since the only potentially affected code would be that which
checked the assocation for "none", and the only such cases were applied
to executable directives.
Commit: 483af6c1be7ca13eda7cc5314bb93185d21b272a
https://github.com/llvm/llvm-project/commit/483af6c1be7ca13eda7cc5314bb93185d21b272a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M flang/include/flang/Lower/OpenMP/Clauses.h
M flang/lib/Lower/OpenMP/Clauses.cpp
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
Log Message:
-----------
[OpenMP] Add definitions for REDUCTION_KIND and SHIFT clauses (#222745)
This is a barebones change to introduce the enum identifiers for these
clauses.
Commit: 240670d0d5dcd649bd3728871087c938b5e097f2
https://github.com/llvm/llvm-project/commit/240670d0d5dcd649bd3728871087c938b5e097f2
Author: MaoJiaping <maojiaping1 at huawei.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/include/llvm/Transforms/Utils/SplitModuleCommon.h
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/SplitModule.cpp
A llvm/lib/Transforms/Utils/SplitModuleCommon.cpp
M llvm/test/tools/llvm-split/unnamed.ll
Log Message:
-----------
[NFC][ModuleUtils] Move externalize() from module splitting utilities (#221181)
`SplitModule.cpp` and `AMDGPUSplitModule.cpp` each carry an identical
static `externalize()` helper that promotes local-linkage globals to
external + hidden visibility and assigns a stable name to unnamed
entities, so they are named consistently across module partitions.
This patch removes the duplication by moving the helper into
`ModuleUtils` as `llvm::externalize`, and updates both users to call the
shared implementation. No functional changes are intended.
This also prepares for upcoming module splitting utilities to reuse a
single, canonical implementation.
Development of this patch was assisted by AI and reviewed by me.
Commit: 860fb775d3d626af6e4a45ea5d62039718957d26
https://github.com/llvm/llvm-project/commit/860fb775d3d626af6e4a45ea5d62039718957d26
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-booleanized-leaves.ll
Log Message:
-----------
[SLP]Reduce logical and/or reductions in the wide leaf type
Logical and/or reductions on i1 with booleanized wide leaves (truncs
of same-op chains, zero-tests of values from [0, 1]) are performed in
the wide type, exposing the underlying consecutive values to the tree;
bit 0 of the result is the final value. Fixes the fragmented reduction
and the gather-of-scalars regression for compile-time-expanded Boolean
reductions.
Fixes #221167
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/221321
Commit: 588304bdb9ee0a9c8229db8c702415e80d05ad33
https://github.com/llvm/llvm-project/commit/588304bdb9ee0a9c8229db8c702415e80d05ad33
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
Log Message:
-----------
[SLP]Model copyable lanes of idempotent binops as op(V, V) when the operand column has a constant lane
The op(V, identity) form lets the reorder move the lane out of the
joined column, breaking the opcode-peer node; the symmetric form is
reorder-proof.
Reviewers: RKSimon, bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/220252
Commit: f4ecba36726d6bede2ab58890dfcc861c2bb28a9
https://github.com/llvm/llvm-project/commit/f4ecba36726d6bede2ab58890dfcc861c2bb28a9
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
Log Message:
-----------
[KnownFPClass] Unify and refine interested classes for `KnownFPClass::log` (#219751)
Previously, `ValueTracking` and `GISelValueTracking` only called
`KnownFPClass::log` when the requested classes included NaN or infinity.
As a result, narrowly interested queries could miss unconditional
deductions, for example, `log(x)` is never subnormal or negative zero
(With the exception of `PPCDoubleDouble`
https://github.com/llvm/llvm-project/issues/217658).
This change makes the interested-class handling consistent between
`ValueTracking` and `GISelValueTracking`. The source is queried only
when its classes are needed, but `KnownFPClass::log` is always called so
its unconditional deductions are preserved.
Future work:
- Fixing `KnownFPClass::log` for `PPCDoubleDouble`.
AI disclosure:
I used OpenAI Codex (sol 5.6) to help write the unit tests, which I
reviewed and ran locally.
Commit: c1f1a288ccd67f9b9dadefda9c510aa7568022e7
https://github.com/llvm/llvm-project/commit/c1f1a288ccd67f9b9dadefda9c510aa7568022e7
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Complete upstream vector saturating shift left NEON builtins (#221507)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for the vector saturating shift left intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left).
This completes the family.
Port tests from `clang/test/CodeGen/AArch64/neon-intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`.
Commit: 0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
https://github.com/llvm/llvm-project/commit/0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
Log Message:
-----------
RegisterCoalescer: Remove empty subranges after merging subranges (#222050)
Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.
Exposed with subregister liveness once LiveIntervals runs before
TwoAddress.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: cff226a5716e4bc3589d4869066ea6687ed142ce
https://github.com/llvm/llvm-project/commit/cff226a5716e4bc3589d4869066ea6687ed142ce
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
Log Message:
-----------
[ConstraintElim] Fold sadd.with.overflow with a constant op. (#223239)
Generalize the overflow-math simplification to also allow simplifying
sadd.with.overflow if the second operand is constant, using
makeGuaranteedNoWrapRegion.
Note that this partially overlaps with the flag strengthening logic.
I'll share a patch soon to try to unify the code more.
No improvements in llvm-opt-benchmarks-nightly. It improves end-to-end
optimizations for Swift (which emits a lot of checked arithmetic) and
also Clang + UBsan.
An end-to-end improvement with overflow intrinsics is
https://llvm.godbolt.org/z/6nrj7aodd.
PR: https://github.com/llvm/llvm-project/pull/223239
Commit: 979b374a7ca7adc936d9339c1db79b0d6cda06db
https://github.com/llvm/llvm-project/commit/979b374a7ca7adc936d9339c1db79b0d6cda06db
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
Log Message:
-----------
[AggressiveInstCombine] Fix terminology in a few comments (NFC) (#222327)
Fix the comments (and a debug print) that say "dominated by trunc"
rather than "post-dominated".
Also fixes a Doxygen syntax (use \p instead of /p) and fix
capitalization in the middle of a sentence.
Commit: d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
https://github.com/llvm/llvm-project/commit/d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
Author: Taimuraz Kaitmazov <5769345+atassis at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
Log Message:
-----------
[MIRParser] Reject a one-element fixed-length vector type (#213290)
MIParser accepts `<1 x sN>` and then asserts while building the LLT, so
llc aborts during parsing instead of reporting a parse error:
```
Assertion `!EC.isScalar() && "invalid number of vector elements"' failed.
```
LLT has no one-element fixed-length vector. `getLLTForType`,
`getLLTForMVT` and
`LLT::changeElementCount` all map a one-element `ElementCount` to the
element
type through `LLT::scalarOrVector`, nothing calls `LLT::fixed_vector(1,
...)`,
and no in-tree .mir test uses the syntax. `verifyVectorElementCount`
already rejects 0 and anything above 2^16, so 1 was the remaining hole; it now
gets the same diagnostic instead of aborting the parser.
Scalable vectors are unaffected: `<vscale x 1 x sN>` is a valid type and
stays legal through the `HasVScale` check.
AI assistance: drafted with AI help; reviewed and validated by me.
Commit: ce73dba9552c93d1cc3abc481dff63a4ab6d0579
https://github.com/llvm/llvm-project/commit/ce73dba9552c93d1cc3abc481dff63a4ab6d0579
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
Log Message:
-----------
[clang][SPIR-V][AMDGPU] Fix variadic aggregate ABI classification for AMDGCN (#216326)
Mirror AMDGPUABIInfo fixed/variadic split
AMDGCNSPIRVABIInfo::classifyArgumentType did not distinguish fixed from
variadic arguments, so aggregates passed through `...` were
misclassified as indirect byref instead of direct
Commit: d91624c19074e219d5a5c5af45f48afd4cd9052a
https://github.com/llvm/llvm-project/commit/d91624c19074e219d5a5c5af45f48afd4cd9052a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
Log Message:
-----------
[AMDGPU] Fix MAI hazard scan missing 19-instruction-old hazards (#222040)
The scan only looked back 19 instructions, but gfx950 can need a gap of
20 after some MFMAs
A hazard exactly 19 instructions back was missed, so no wait was
inserted
Commit: 8864a4bb996d6bb541b0974d34991da40a643c90
https://github.com/llvm/llvm-project/commit/8864a4bb996d6bb541b0974d34991da40a643c90
Author: neoto <48843913+neoto at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
Log Message:
-----------
[Mips] Handle division by zero trap on MIPS1 (#201133)
LLVM currently emits the `teq` instruction for every arch version, but
`teq` is unsupported on MIPS1.
This special cases MIPS1 so that `bne(z)` and `break` are emitted
instead.
Compared to https://github.com/llvm/llvm-project/pull/81311, this should
also handle liveness as far as I can tell.
I didn't want to add another bool to the argument list so I combined
`IsMicroMips` and what was supposed to be `IsMips1` into an enum, which
feels much nicer in this case.
Besides that and the main change, I also changed the `hasSideEffects`
bit for `PseudoSDIV` and `PseudoUDIV`,
which allows the delay slot to be usefully filled - well, at least with
`-O1`+. This seems to be in line with what GCC does:
https://godbolt.org/z/zqcG5ha35
Tested using clang directly and through Zig's LLVM backend.
Closes https://github.com/llvm/llvm-project/issues/80554
Supersedes https://github.com/llvm/llvm-project/pull/81311
Commit: 85f694b3eeafc07e5c586fa15715facefba71094
https://github.com/llvm/llvm-project/commit/85f694b3eeafc07e5c586fa15715facefba71094
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
Log Message:
-----------
[ASan] Convert pointer-pair operands based on type (#218494)
`CreatePointerCast` was being called on everything without checking what
it actually is, so if the operand came from ptrtoint ... to i32 it just
crashes (its not a pointer).
now it check the type first - pointers get pointer-cast, ints get
zext/trunc'd to intptr width.
Fixes #217544
also edited regression tests for this
Commit: 4098f568c46e06b6df470111868b4c165dd80f4d
https://github.com/llvm/llvm-project/commit/4098f568c46e06b6df470111868b4c165dd80f4d
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Don't fold in_bounds for negative constant indices (#219681)
`isInBounds` checked only that the transfer *ends* inside the source:
return cstOp.value() + vectorSize <= sourceSize;
The `in_bounds` attribute promises more than that. Its definition in
VectorOps.td says accesses "(including the starting point)" may run
out-of-bounds when it is "false", so setting it to "true" is a claim
about the start of the transfer as well as its end.
With a negative constant index the two disagree. For
vector.transfer_read %m[-1] : memref<8xf32>, vector<4xf32>
`-1 + 4 <= 8` holds, so the fold set `in_bounds = [true]`, even though
element -1 is read from outside `%m`.
The same expression also overflows for a large enough index: at `index =
2^63 - 1` the addition wraps and the fold again reports `in_bounds =
[true]`. Computing the bound as `sourceSize - vectorSize` instead avoids
the addition entirely; both operands are static, non-negative dimension
sizes, so the subtraction cannot overflow.
This is a spec-conformance fix, not a live miscompile report. A negative
index into a memref is already undefined behaviour, and the masked
lowering would not have caught it either: the guard
`generateInBoundsCheck` emits in VectorToSCF is `memrefDim > index +
iv`, an upper-bound check only.
Adds three regression tests, each of which fails without the change.
Assisted-by: Claude
Commit: b7877e01cb1087d81fd72eb320c3c7d3f8e03500
https://github.com/llvm/llvm-project/commit/b7877e01cb1087d81fd72eb320c3c7d3f8e03500
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
Log Message:
-----------
[ConstraintElim] Derive an unsigned IV bound from a signed relational latch. (#222762)
For a known non-negative backedge (either via isKnownNonNegative or
because the increment is increasing), 0 <=s PN <= B holds and implies
that B is non-negative as well.
Use that to translate a signed condition to the equivalent unsigned one.
Note that the general signed->unsigned rewrite cannot catch this,
because the precondition also needs rewriting to unsigned.
No llvm-opt-benchmark-nightly impact, but it can help remove runtime
checks generated by sanitizers or Swift code. An end-to-end C example is
https://clang.godbolt.org/z/vbd91MjaM.
Alive2 Proof: https://alive2.llvm.org/ce/z/G3Mv7t
PR: https://github.com/llvm/llvm-project/pull/222762
Commit: 914e15cd29f78e01e15378cfccff97d42e6e9e82
https://github.com/llvm/llvm-project/commit/914e15cd29f78e01e15378cfccff97d42e6e9e82
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Move the LLVMContext out of ReplaceableMetadataImpl. NFC (#222085)
No ReplaceableMetadataImpl method reads its LLVMContext reference, and
ValueAsMetadata reaches the context through the wrapped Value. Keep the
reference in a derived ReplaceableUsesWithContext, used by the two
owners with no other route to it: MDNode's on-demand RAUW support and
DIArgList.
Rename the base to ReplaceableUses: it is the use map behind RAUW for
the metadata kinds that support it, not a pimpl, and the name matches
ContextAndReplaceableUses and getReplaceableUses().
Make the base destructor protected, since getOrCreate() hands out
ReplaceableUses pointers that must never be deleted. Delete copy
assignment explicitly; the LLVMContext reference suppresses it
implicitly.
sizeof(ValueAsMetadata) 152 -> 144.
Aided by Opus 5
Commit: d44791d35a4b15f3da7855790203ca14f7953410
https://github.com/llvm/llvm-project/commit/d44791d35a4b15f3da7855790203ca14f7953410
Author: averne <45773016+averne at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
Log Message:
-----------
[AMDGPU] IGLP: Sanitize user schedule hints (#221256)
Fixes the following ICE:
```cpp
extern __shared__ int lds[];
__global__
void kern_ice() {
auto _ = lds[threadIdx.x];
__builtin_amdgcn_sched_barrier(~0x380); // Allow all except DS instructions
}
```
See: https://godbolt.org/z/oGfT1TTa4
Commit: cba24d6a935382154b0487d09c1d91a0e2bda04b
https://github.com/llvm/llvm-project/commit/cba24d6a935382154b0487d09c1d91a0e2bda04b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Generalize folding IV increment into phi start value (NFC). (#223260)
simplifyRecipe folds
X = phi(0, IVInc)
IVInc = X + Step
Def = IVInc + Y
into a phi starting at Y, but only if Y is a live-in. Also allow values
defined in the block the phi's start value is coming from, which is
where the value conservatively has to be available.
NFC today, but preparation for modeling the full epilogue skeleton in
VPlan.
Commit: 8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
https://github.com/llvm/llvm-project/commit/8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
Log Message:
-----------
[NFC][AMDGPU] Fix clang-tidy warnings in VOPD related files (#223261)
Commit: 86858de86cb28299ebc9c0ce8a06e5a61ed6b261
https://github.com/llvm/llvm-project/commit/86858de86cb28299ebc9c0ce8a06e5a61ed6b261
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/test/Headers/__clang_hip_math.hip
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[ValueTracking] Propagate non-negativity through fptosi (#217868)
Fixes #217442
`fptosi` is poison when the rounded value does not fit in the result
type, so `computeKnownBits` can assume the conversion rounds towards
zero without wrapping. Negative subnormals and negative zero always
round to 0, so only sources known to never be a negative normal or
negative infinity (i.e. values <= -1.0) can produce a negative result.
This lets InstCombine fold `(int)fabs(x) < 0` to `false`, matching GCC,
and also benefits other magnitude-clamping intrinsics such as sqrt.
Commit: 667efaee701ae5345f4cde42f8b3e5b7f98549ee
https://github.com/llvm/llvm-project/commit/667efaee701ae5345f4cde42f8b3e5b7f98549ee
Author: Benji Smith <6193112+Benjins at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
Log Message:
-----------
[InstCombine] Fix fold of comparison of rotates (#223263)
rotate(X, AmtX) == rotate(Y, AmtY) -> rotate(X, AmtX - AmtY) == Y
This fold is usually valid, but implicitly assumed that the bit width
was a power of two. This is now checked and the transform doesn't fire
if the bit width isn't a power of two.
Fixes https://github.com/llvm/llvm-project/issues/223262
Commit: 0485ad7e469a56443094872c0f57f2870eccb654
https://github.com/llvm/llvm-project/commit/0485ad7e469a56443094872c0f57f2870eccb654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGen/thread-model.c
Log Message:
-----------
clang: Emit the "thread-model" module flag (#223156)
Commit: eb5c148b1cbc89c75a57a505d2533ae52e5bde44
https://github.com/llvm/llvm-project/commit/eb5c148b1cbc89c75a57a505d2533ae52e5bde44
Author: zhouguangyuan0718 <zhouguangyuan.xian at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
Log Message:
-----------
[MachineScheduler] Order fixed-FI memory operations by object offset (#219669)
## Summary
- sort fixed frame-index memory operands by their explicit stack offsets
- preserve the existing frame-index ordering for ordinary stack objects
and as a tie-breaker
- add an AArch64 MIR regression with fixed objects created out of offset
order
## Background
`BaseMemOpClusterMutation` currently orders frame-index bases by
frame-index number, adjusted for the stack growth direction. Fixed frame
objects are different from ordinary stack objects: they carry explicit
offsets, and their creation order is not required to match address
order.
As a result, a target clustering hook can receive two fixed objects in
reverse address order. AArch64's `shouldClusterFI` expects the incoming
fixed-object offsets to be ordered and aborts with `Object offsets are
not ordered` in an assertions-enabled build.
When both operands refer to fixed frame objects, compare their
`MachineFrameInfo` object offsets first. The existing frame-index
comparison remains the fallback, so the ordering of ordinary stack
objects is unchanged.
Make the ordering between fixed and non-fixed frame-index bases
explicit: non-fixed bases precede fixed bases for downward-growing
stacks, while fixed bases precede non-fixed bases for upward-growing
stacks. This preserves the existing cross-category ordering without
relying on non-fixed object offsets before frame layout.
The regression deliberately creates two fixed objects in an order that
disagrees with their explicit offsets. It covers both the legacy and new
machine-scheduler pass forms.
## AI assistance
OpenAI Codex was used to assist with the investigation, patch
preparation, testing, and drafting this PR description.
Commit: a129f830b8727c51c087db8278035d2c6f08da25
https://github.com/llvm/llvm-project/commit/a129f830b8727c51c087db8278035d2c6f08da25
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Use BitVector for RegisterSet in AsmMatcherEmitter (NFC) (#222525)
This patch replaces std::set with BitVector for RegisterSet in
AsmMatcherEmitter.
Without this patch, RegisterSet is represented as
std::set<const Record *, LessRecordByID>. On targets with large
register files like AMDGPU (~3,000 registers), repeatedly computing set
intersections and subset checks using std::set nodes incurs
significant overhead.
This patch assigns each register record a dense bit index ordered by
LessRecordByID. This allows us to represent RegisterSet as a
BitVector, enabling fast bitwise operations for set intersections and
subset checks.
This reduces the wall-clock time of generating AMDGPUGenAsmMatcher.inc
from 39.53s to 31.32s (a 20.8% speedup) across 3 runs while producing
bit-for-bit identical output across all targets.
Assisted-by: Antigravity
Commit: ac8aca03372551f8a8c999e86e5cb6cbfae3e307
https://github.com/llvm/llvm-project/commit/ac8aca03372551f8a8c999e86e5cb6cbfae3e307
Author: Yousef <yousef.idris01 at bcmail.cuny.edu>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
Log Message:
-----------
[GlobalISel] Add KnownBits support for G_INSERT_SUBVECTOR (#215048)
## Summary
Add KnownBits support for `G_INSERT_SUBVECTOR` in GlobalISel value
tracking.
The implementation splits the demanded elements between the original
vector and inserted subvector, ignores overwritten source elements, and
intersects the KnownBits information from the contributing operands.
Part of #150515.
## Testing
- `llvm-lit
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir`
- `llvm-lit llvm/test/CodeGen/AArch64/GlobalISel/knownbits-*.mir`
- 40/40 passed
Commit: 8497b7a259bbc8239d7358dc7bf83eb04b363c76
https://github.com/llvm/llvm-project/commit/8497b7a259bbc8239d7358dc7bf83eb04b363c76
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
Log Message:
-----------
[AMDGPU] Support TFE D16 format buffer loads on gfx8/10/11/12 (#211465)
gfx90a has no hardware encoding for TFE D16 format buffer loads, so
reject the combination there with a diagnostic. Other targets
(gfx8/10/11/12) do have real encodings, so add codegen support for them
instead of rejecting unconditionally.
Commit: 89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
https://github.com/llvm/llvm-project/commit/89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
Log Message:
-----------
[VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
No-op casts get folded to the input operand, which caused applyFlags to
crash if that was not a cast. Fix by avoiding creating such trivial
casts in the first place.
Commit: 82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
https://github.com/llvm/llvm-project/commit/82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
M clang/test/Driver/mingw.cpp
Log Message:
-----------
[Clang][MinGW] Link default-manifest.o if exists (#223084)
Some MinGW distributions provide a pre-compiled manifest xml to disable
the UAC escalation dialog.
Link automatically the manifest only if it exists when linking an
executable.
Do the same as Cygwin (#220875) and align with GCC.
Commit: 9bf40ce33523745e19328924593134e4510bfa5f
https://github.com/llvm/llvm-project/commit/9bf40ce33523745e19328924593134e4510bfa5f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
Log Message:
-----------
[AMDGPU] Fix s_buffer_load crash for illegal result types (#215483)
i1, i4, v2i1, v3i16, v6i8, and i128 had no SBUFFER_LOAD selection
pattern and crashed
Load a legal i32/vNi32 carrier instead and narrow/bitcast down to the
requested type
Commit: cf530065be1fccbd9ac1d5ccc7d55d80681de41d
https://github.com/llvm/llvm-project/commit/cf530065be1fccbd9ac1d5ccc7d55d80681de41d
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
Log Message:
-----------
[lldb][Process/FreeBSD-Kernel-Core] Dereference stoppcbs based on target kernel version (#222977)
As of `__FreeBSD_version 1400089` stoppcbs is a pointer to the pcbs
array. Dereference stoppcbs on sufficiently new kernels.
Obtained-from:
https://cgit.freebsd.org/src/commit/?id=0f2bb40bc7ddee7ba329d9b344623e2a186b4046
Commit: 4b08871f7ffe6ad818147145f8b6103e6c9b2c95
https://github.com/llvm/llvm-project/commit/4b08871f7ffe6ad818147145f8b6103e6c9b2c95
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
Log Message:
-----------
[SSAF][SourceEdit] Wire in 'clang-ssaf-src-edit-merge' and add multi-TU tests (#220372)
With 'clang-ssaf-src-edit-merge', we can test source edits over multiple
translation units: their Replacements are merged before apply. This
covers both clean merges and conflicts.
Commit: e476e76df9b17ace8d12f85616482718901d4854
https://github.com/llvm/llvm-project/commit/e476e76df9b17ace8d12f85616482718901d4854
Author: David Green <david.green at arm.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Make ImmInsnModel operands optional. NFC (#223280)
This helps make sure we do not use them incorrectly, and should allow
them to
be checked for values in the future.
Commit: e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
https://github.com/llvm/llvm-project/commit/e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
Log Message:
-----------
[VPlan] Add tests for narrowing users of a widened induction (NFC). (#223277)
Add additional narrowing tests for wide IV including pointer inductions
and FP inductions.
Commit: cc6d78e8eea21e0ddc5376b1700af00e33a77e17
https://github.com/llvm/llvm-project/commit/cc6d78e8eea21e0ddc5376b1700af00e33a77e17
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[VPlan] Fold shifts by zero. (#223276)
Add trivial folds of shifts by zero. This allows us to match IR SCEV
behavior (which looks through trivial shifts), w/o explicitly handling
those in getSCEVExprForVPValue.
Commit: 0c4e1a6b8941babd458e803041abc4d5186361e8
https://github.com/llvm/llvm-project/commit/0c4e1a6b8941babd458e803041abc4d5186361e8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Set the containing plan when creating blocks (NFC). (#223269)
Now that we funnel all VP block creation through VPlan helpers, make
sure the Plan field is set for each block. This means we can remove the
CFG walk to find a Plan's entry.
Also drop an assertion in VPSlotTracker::getOrCreateName: a block now
knows its plan as soon as it is created.
This has a very small positive compile-time impact.
Commit: 462535b1455c639bfb1875b71720d94586a5f650
https://github.com/llvm/llvm-project/commit/462535b1455c639bfb1875b71720d94586a5f650
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[InstCombine][NFC] Move bitcast from float tests into their own file (#223196)
Commit: c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
https://github.com/llvm/llvm-project/commit/c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
Log Message:
-----------
[lldb] Test undefined return addresses in signal frames (#223046)
Signal-frame CFI can explicitly mark its return-address register
undefined to represent a terminal synthetic context. This is useful for
contexts such as newly created FreeBSD kernel threads that do not have
an interrupted caller.
Verify that LLDB keeps the signal frame in the backtrace and terminates
the unwind without creating a caller.
Assisted-by: GPT
Commit: bce20f538caf18619a825c689883f652471091d3
https://github.com/llvm/llvm-project/commit/bce20f538caf18619a825c689883f652471091d3
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Add experimental Smidctrl, Ssidctrl, Smnip, and Ssnip support (#218108)
Add experimental MC support for Smidctrl, Ssidctrl, Smnip, and Ssnip
extensions.
This completes MC support for the ACLIC v0.20 extensions.
Commit: 63d2e62707e8ec6c070a3b258ea81f320920525c
https://github.com/llvm/llvm-project/commit/63d2e62707e8ec6c070a3b258ea81f320920525c
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Lex/PPMacroExpansion.cpp
Log Message:
-----------
[clang][Lex] Unique ModuleMacros with a UniquingSet (NFC) (#223270)
This patch migrates ModuleMacros in Preprocessor from llvm::FoldingSet
to llvm::UniquingSet.
ModuleMacro keys on a pair of Module * and const IdentifierInfo *.
Switching to UniquingSet allows us to look up macros with a typed key,
eliminating FoldingSetNodeID serialization at lookup sites and removing
ModuleMacro::Profile.
Assisted-by: Antigravity
Commit: 6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
https://github.com/llvm/llvm-project/commit/6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
A llvm/test/Transforms/InstCombine/uitofp.ll
Log Message:
-----------
[InstCombine] Fold uitofp of masked truncations (#222592)
Fold an unsigned integer-to-floating-point conversion of a masked
truncation by widening the mask and eliminating the truncation:
`uitofp((trunc X) & C)` → `uitofp(X & zext(C))`
Apply the fold when the intermediate instructions have one use and
widening the integer operation is desirable.
This reduces the instruction count on both AMDGPU and NVPTX.
AMDGPU example: https://godbolt.org/z/rTYhM61ce
NVPTX example: https://godbolt.org/z/fWhsrne19
Commit: 9e70d8f070ba046b8e09388fa84b3a65eb2073e3
https://github.com/llvm/llvm-project/commit/9e70d8f070ba046b8e09388fa84b3a65eb2073e3
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/blocks.cpp
Log Message:
-----------
[Clang][NFC] add additional test coverage for default argument parsing errors (#222556)
Fixes #115280
Commit: 291b60a5bc416c8dd81731954680ebd41f599ab5
https://github.com/llvm/llvm-project/commit/291b60a5bc416c8dd81731954680ebd41f599ab5
Author: wanglei <wanglei at loongson.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
Log Message:
-----------
[LoongArch][test] Test 1- and 2-byte subtraction relocations. NFC (#222825)
Add MC tests for 1- and 2-byte subtraction relocations enabled by
#211754.
Commit: dbac421efa19a5901f2511958040e18e8188b112
https://github.com/llvm/llvm-project/commit/dbac421efa19a5901f2511958040e18e8188b112
Author: lntue <lntue at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/utils/mathtools/wc_to_bin.py
Log Message:
-----------
[libc][math] Fix fast path with small inputs for double precision sin/cos. (#221012)
https://github.com/llvm/llvm-project/pull/201748 added a fast branch for
small inputs to double precision sin/cos,
but the Ziv error bounds were too tight.
Fixes in this PR:
- Updating the Ziv error bounds to accommodate rounding errors.
- Copy binary64 sin/cos hard-to-round cases from the CORE-MATH project.
- Add python tool to convert textual hard to round cases to binary
files, and add those binary files.
- Add hard-to-round tests for double precision sin/cos in the exhaustive
test folder.
Fixes https://github.com/llvm/llvm-project/issues/220934.
Assisted-by: Gemini is used to generate the worst-case text-to-binary
tool.
Commit: a92db5feb9eb78ae7bf37d969391d9f94f181afb
https://github.com/llvm/llvm-project/commit/a92db5feb9eb78ae7bf37d969391d9f94f181afb
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen] Declare <TargetName>RegClassByHwModeTables in MC header (#223292)
When a target uses RegClassByHwMode in CompressPat, the generated
functions reference <TargetName>RegClassByHwModeTables.
Declare it under GET_INSTRINFO_MC_HELPER_DECLS (<Target>MCTargetDesc.h)
so it is visible to MC-layer users such as RISCVBaseInfo.cpp.
Fixes: 700d1f029d00 ("[TableGen] Support RegClassByHwMode in
CompressPat")
Commit: 10b2437880e6d3365f973174f6bce8e07f54f549
https://github.com/llvm/llvm-project/commit/10b2437880e6d3365f973174f6bce8e07f54f549
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Build RTTICrossDylibTestLib with ORC_RT_COMPILE_FLAGS (#223144)
Without ORC_RT_COMPILE_FLAGS, the test library builds with C++ RTTI on
by default. This leads to link errors when the ORC runtime is built with
C++ RTTI turned off.
Commit: 72d03332c0cd0579ad09d00f9086c7cb6035fce0
https://github.com/llvm/llvm-project/commit/72d03332c0cd0579ad09d00f9086c7cb6035fce0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/tools/ogre/CMakeLists.txt
Log Message:
-----------
[orc-rt] Add ORC_RT_BEDROCK_LIBRARY_TYPE (STATIC/SHARED) (#223288)
Add CMake options to build bedrock as either a static or shared library.
Default is static.
This is CMake infrastructure only. Shared library builds aren't actually
useable yet: bedrock doesn't export its C++ API, and its C API is
insufficient to do anything interesting. Tools and test code are updated
to link against the -object libraries directly, since they use the
(unexported) C++ API.
Commit: 5fa83314adddbd13e4347ec8fc22e235d5710978
https://github.com/llvm/llvm-project/commit/5fa83314adddbd13e4347ec8fc22e235d5710978
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/test/Driver/sparc-as.c
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M llvm/lib/Target/Sparc/Sparc.td
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
Log Message:
-----------
[SPARC] Add LEON5 processor (#222912)
Same target exists in GCC.
Commit: f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
https://github.com/llvm/llvm-project/commit/f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve EHFrame registration symbols via lookupAndApply (#223304)
EHFrameRegistrationPlugin::Create resolved its register/deregister
alloc-action addresses with EPC.getBootstrapSymbols. For consistency,
switch to lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
https://github.com/llvm/llvm-project/commit/bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
Log Message:
-----------
[libc] Implement pthread_attr_[gs]etschedparam (#222991)
This patch implements pthread_attr_setschedparam and
pthread_attr_getschedparam.
Like the schedpolicy patch, this commit only operates on the
pthread_attr_t object and does not attempt to install scheduling
parameters when creating a new thread.
I also don't attempt to validate the priority value here. The valid
priority range depends on the scheduling policy (which may not even be
set yet or could change later), and we can let the kernel validate the
parameters when creating the thread or setting scheduler settings.
While in there:
- update the file headers to the modern llvm format
- use proxy headers instead of direct pthread.h inclusion
Assisted-by: Gemini
Commit: aeefb10b01fb7cf11a1917230f10b663d5ec109b
https://github.com/llvm/llvm-project/commit/aeefb10b01fb7cf11a1917230f10b663d5ec109b
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/IR/Metadata.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Simplify ValueAsMetadata::handleRAUW. NFC (#223301)
Metadata refers to a Value through its unique ValueAsMetadata wrapper.
When a Value is RAUW'd, handleRAUW reuses the old value's wrapper for
the new value if the new value has none yet; otherwise it moves the uses
to the new value's wrapper, with special cases for a local becoming a
constant, a constant becoming a local, and a value moving to another
function.
Always move the uses (or drop them in the last two cases) and delete the
old wrapper, so that a ValueAsMetadata wraps the same value for its
whole life.
Instruction counts for SLPVectorizer.cpp and X86ISelLowering.cpp at -O2
-g are unchanged (-0.04%, -0.01%).
Aided by Opus 5
Commit: 9a7c7f2b3a40c32e53dcaf2637087851d694cc60
https://github.com/llvm/llvm-project/commit/9a7c7f2b3a40c32e53dcaf2637087851d694cc60
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
Log Message:
-----------
[Clang][RISCV] Add packed widening add accumulate intrinsics (#221622)
Add Clang header intrinsics for the RISC-V P-extension packed widening
add accumulate operations:
- __riscv_pwadda_i16x4
- __riscv_pwadda_i32x2
- __riscv_pwaddau_u16x4
- __riscv_pwaddau_u32x2
The header wrappers use generic LLVM IR. RV32 selects the direct
`pwadda.*` / `pwaddau.*` instructions. RV64 lowers the generic IR to the
decomposition specified by the P-extension intrinsic spec, including
`zip16p + pli.h + pm2adda.h/pm2addau.h` for the halfword forms.
Commit: f8c52ad174682e05e222c1456a9f3ad177cf464b
https://github.com/llvm/llvm-project/commit/f8c52ad174682e05e222c1456a9f3ad177cf464b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
Log Message:
-----------
[TargetInstrInfo] Enable instruction size verification by default (#221687)
Enable verification for instruction sizes by default. When emitting
machine code, this checks that the reported instruction size is not
smaller than the actual instruction size. Not under-reporting
instruction sizes is critical for any target that does branch relaxation
(or similar) on MIR.
The default allows over-estimating the size. Targets can opt-in to
precise instruction sizes if they want.
Exclude two instructions on ARM, which report incorrect sizes, but
fixing those sizes breaks the constant islands pass for some reason.
Commit: a9253c774aae777f5c0135d063a3a044612ae48f
https://github.com/llvm/llvm-project/commit/a9253c774aae777f5c0135d063a3a044612ae48f
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/Allocator.h
M llvm/unittests/Support/AllocatorTest.cpp
Log Message:
-----------
[Allocator] Don't overestimate alignment for operator new (#223300)
On many platforms with alignof(max_align_t)=16, when sizeof(T) == 24,
The placement new overestimates the alignment to 16:
`std::min(llvm::bit_ceil(Size), alignof(std::max_align_t)) = min(32, 16) = 16`.
We can use a better estimate: `min(countr_zero(Size),
alignof(max_align_t))`, which is hand-optimized to the form in the code.
Commit: 93d89033cddd47fc512dbe14917fd62d302f4f1d
https://github.com/llvm/llvm-project/commit/93d89033cddd47fc512dbe14917fd62d302f4f1d
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
Log Message:
-----------
[GlobalOpt] Fix assertion failure with CallInst user (#221955)
By removing the unnecessary assertion, which can get
out of sync with GlobalStatus.
Fixes: #221589
Commit: b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
https://github.com/llvm/llvm-project/commit/b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
Log Message:
-----------
[RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 (#222829)
i64 is not a legal type on RV32, so f16 to i64 conversions used to be expanded to a __fixhfdi/__fixunshfdi libcall, which compiler-rt does not provide. f16 is the only FP type whose finite values always fit in an i32 after truncation towards zero, so custom expand them to an i32 conversion plus an extension instead; out of range values and NaN are poison, so the fcvt clamping is acceptable. With only Zfhmin/Zhinxmin the i32 conversion promotes f16 to f32, and both imply F/Zfinx so f32 is always legal. Other FP source types keep using the libcall.
Commit: bc985edd777ff8efab9f161444d4a9ff00c25574
https://github.com/llvm/llvm-project/commit/bc985edd777ff8efab9f161444d4a9ff00c25574
Author: Chris Copeland <chris at chrisnc.net>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
Log Message:
-----------
[CodeGen][test] use -float-abi=soft in 2009-03-29-SoftFloatVectorExtract.ll (#223122)
In #221434, using +soft-float with a hard-float ABI is now an error on
ARM.
This test does not specify a target triple, so it will fail when the
default triple is hard-float ARM. Explicitly specify -float-abi=soft
so the test will continue to use the host triple but force the
soft-float ABI
where applicable.
Commit: badec9b619f3f7d6090d5ae84a60adf416139a15
https://github.com/llvm/llvm-project/commit/badec9b619f3f7d6090d5ae84a60adf416139a15
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve unwind-info alloc-actions via lookupAndApply (#223312)
UnwindInfoRegistrationPlugin::Create resolved its register- /
deregister-section alloc-actions with EPC.getBootstrapSymbols. For
consistency, switch to lookupAndApply/recordAddr on the bootstrap
JITDylib instead.
Commit: 109f29a7c0a3910a768fa7dd490ac8f51708b858
https://github.com/llvm/llvm-project/commit/109f29a7c0a3910a768fa7dd490ac8f51708b858
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
Log Message:
-----------
[SPIR-V] Print group operation of uniform group instructions as enum (#222540)
Opcodes typed `$groupOp` as i32imm, so the printer emitted 0 instead of
"Reduce" and spirv-as rejected the output
Commit: 20b53106931742d2e5e64132f06994980fe94d7d
https://github.com/llvm/llvm-project/commit/20b53106931742d2e5e64132f06994980fe94d7d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Avoid use of ConstantExpr::getSizeOf() (#223323)
This will not be supported in ptradd representation. Directly
create a constant with the type size instead.
Commit: a872c86cf07ad71cc4e05a98c5169a27d600d16c
https://github.com/llvm/llvm-project/commit/a872c86cf07ad71cc4e05a98c5169a27d600d16c
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Parser/cxx-extra-semi.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for extra semicolons in parameter lists (#222572)
Fixes #112377
Commit: 61519bf9fa07fed0546c2985a6884b60ca71ca2b
https://github.com/llvm/llvm-project/commit/61519bf9fa07fed0546c2985a6884b60ca71ca2b
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/enum.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for parameter declaration errors (#222562)
Fixes #113465
Commit: ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
https://github.com/llvm/llvm-project/commit/ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
Log Message:
-----------
[CGP] Clear poison generating flags when freezing icmp of constants (#223326)
Followup to https://github.com/llvm/llvm-project/pull/222314. That
PR only dropped the flags for the case where a new freeze instruction
was created, but of course we also need to do this if both operands
are constant and the freeze is dropped entirely.
Commit: fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
https://github.com/llvm/llvm-project/commit/fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[lldb-dap] Fix logpoint to breakpoint conversion (#222906)
When user sets logpoint and after that removes `logMessage`, which
implicitly converts it to usual breakpoint, breakpoint still has
`BreakpointHitCallback`, which leads to missed stops.
Commit: 0f89e7a6027b9fc93032aa4d154028045ed9018f
https://github.com/llvm/llvm-project/commit/0f89e7a6027b9fc93032aa4d154028045ed9018f
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
Log Message:
-----------
[Flang][OpenMP] Show warning for -fdoconcurrent-to-openmp in SIMD only mode (#220943)
The OpenMP feature is considered enabled if either `-fopenmp` or
`-fopenmp-simd` have been passed. However, full OpenMP support is
required in order for the `-fdoconcurrent-to-openmp` option to take
effect.
A warning message that wasn't shown when SIMD-only OpenMP support was
enabled is fixed.
Commit: 860d945db8787845349096521157eabf09be81cb
https://github.com/llvm/llvm-project/commit/860d945db8787845349096521157eabf09be81cb
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223328)
Commit: 6e071ab17caa0058a83cdd1580026259fdaecb4f
https://github.com/llvm/llvm-project/commit/6e071ab17caa0058a83cdd1580026259fdaecb4f
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
Log Message:
-----------
[RISCV] Rewrite ADD to SUB to reuse a materialized negated constant (#221027)
When an ADD needs a large constant whose negation is already
present in the DAG, rewrite (add X, C) into (sub X, -C) so both
share one materialization of -C instead of building it twice.
selectNegImm already does a related rewrite, but only when -C is
strictly cheaper than C and during instruction selection, where the
sibling constant may already have been selected into instructions.
Do it in PreprocessISelDAG instead, before selection, while both are
still ConstantSDNodes that getConstant can unique together. The
rewrite only fires when -C is no more expensive than C and a node
holding -C already exists, so it never adds a materialization.
Fixes https://github.com/llvm/llvm-project/issues/220555
Assisted-by: TRAE CLI (Opus 4.8)
Commit: 6d4ad3383e9b235c0f07a82be141bb57278650af
https://github.com/llvm/llvm-project/commit/6d4ad3383e9b235c0f07a82be141bb57278650af
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
Log Message:
-----------
[AMDGPU] Model waterfall loop EXEC update as a terminator (#219519)
Defining a register normally disqualifies an instruction from being a
terminator, so mark it unspillable instead
Skip this at -O0, since RegAllocFast ignores that and spills right after
the def
Commit: 6b5912a441c2236859a7cfe1e5ce3e02a547b588
https://github.com/llvm/llvm-project/commit/6b5912a441c2236859a7cfe1e5ce3e02a547b588
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
Revert "[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC)" (#223341)
Reverts llvm/llvm-project#223328 (looking into buildbot error, e.g.
https://github.com/llvm/llvm-project/pull/223328#issuecomment-5661919431)
Commit: 1042f3cd8299003876babb567d78540d30c019aa
https://github.com/llvm/llvm-project/commit/1042f3cd8299003876babb567d78540d30c019aa
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[mlir][ComplexToStandard] Use negf/subf instead of multiplying by -1 (#222877)
Commit: e8d2def7e7ed18f22a493b72435468225c1047ba
https://github.com/llvm/llvm-project/commit/e8d2def7e7ed18f22a493b72435468225c1047ba
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
Log Message:
-----------
[libc++] Provide aligned allocation function iff the compiler claims support (#219199)
There isn't much of a point to providing declarations for aligned
allocation functions but not allowing the compiler to use them. So
either aligned allocations should be allowed to be used via
`-faligned-allocation` or not provided at all.
Commit: 1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
https://github.com/llvm/llvm-project/commit/1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/docs/OpenMP-declare-target.md
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
Log Message:
-----------
[MLIR][OpenMP] DeclareTargetInterface and DeclareTargetAttr cleanup (#217295)
The changes introduced by this patch are intended to avoid triggering
multiple by name lookups to the "omp.declare_target" attribute every
time any data from the `DeclareTargetInterface` is queried, remove the
need for keeping multiple default values for the same data, clean up the
assembly format and generally improve the usage of the interface.
List of changes:
- `DeclareTargetInterface` only provides `setDeclareTarget` and
`getDeclareTarget` methods to handle the "omp.declare_target" attribute,
maintaining a single canonical way of accessing it.
- `DeclareTargetAttr` provides direct access to the capture clause and
device type enums, rather than wrapping them into an `Attribute`. These
are now mandatory as well. Both changes together make accessing them
more straightforward and simplify the attribute representation.
Commit: 37fe7024f2944f71d58b8608d209bda3254fa43a
https://github.com/llvm/llvm-project/commit/37fe7024f2944f71d58b8608d209bda3254fa43a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/read_image.ll
Log Message:
-----------
[SPIR-V] Add missing read_imageh builtin mapping (#222549)
Commit: c4c4bbaf14303d3e5399487c16ec6a0ff4754386
https://github.com/llvm/llvm-project/commit/c4c4bbaf14303d3e5399487c16ec6a0ff4754386
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__charconv/to_chars_integral.h
Log Message:
-----------
[libc++][NFC] Remove some unused functions from to_chars_integral.h (#223130)
Commit: d873afedebd0726700ba7f42a5d6e54dba288557
https://github.com/llvm/llvm-project/commit/d873afedebd0726700ba7f42a5d6e54dba288557
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
Log Message:
-----------
[libc++] Optimize string copy construction (#222021)
We know that the string size provided to `__init_copy_ctor_external` is
less than or equal to `max_size()`, so we don't need to do that check
again. Removing that check allows the compiler to ShrinkWrap the small
size path and also removes some unnecessary work in the allocating path.
Commit: 1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
https://github.com/llvm/llvm-project/commit/1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
Log Message:
-----------
[libc++] Move _LIBCPP_HAS_COND_CLOCKWAIT into condition_variable.h (#222904)
`_LIBCPP_HAS_COND_CLOCKWAIT` is only used inside
`<__condition_variable/condition_variable.h>`, so we might as well move
it there.
Commit: 59f4a867528eeb8cd8823afb0ee4e5c4d2843741
https://github.com/llvm/llvm-project/commit/59f4a867528eeb8cd8823afb0ee4e5c4d2843741
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
Log Message:
-----------
[X86] Fix `"Cannot select"` for `bf16` vector selects on a scalar condition under `AVX10.2` (#222854)
Fixes #222673
A `select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b` failed instruction
selection with `+avx10.2-512` on a `v8bf16 X86ISD::CMOV`. Selects on a
scalar condition are lowered to the `CMOV_VR*` pseudos and expanded to a
branch, but those pseudos only have patterns for integer and f16
vectors. Before #101603 bf16 vectors were treated as "soft" everywhere,
so `LowerSELECT` bitcast them to `v8i16` first and never produced a bf16
CMOV. That PR made bf16 non-soft under AVX10.2 to enable native
arithmetic, which silently removed the only bf16-aware path in
`LowerSELECT` without adding a replacement. `v16bf16` and `v32bf16` hit
the same thing.
`LowerSELECT` now takes the integer-bitcast path for every bf16 vector,
using the existing `isBF16orSoftF16` helper, so the select is lowered
exactly as it is on every other bf16 target and as `v8f16` is on FP16
targets. Scalar `bf16` is soft-promoted to `f32` before lowering, so it
is unaffected. Added `pseudo_cmov_lower-bf16.ll` alongside the f16
sibling, covering the reproducer plus `v8/v16/v32bf16` on both
`+avx512bf16,+avx512vl` and `+avx10.2-512`.
Commit: 1b97c0daeb67ef7895034a1702ccc04562283ecc
https://github.com/llvm/llvm-project/commit/1b97c0daeb67ef7895034a1702ccc04562283ecc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
Log Message:
-----------
[ORC] Resolve JITLoaderGDB alloc actions via lookupAndApply (#223325)
ELFDebugObjectPlugin resolved its RegisterJITLoaderGDB alloc-action
address with EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: eb6d5dd90eb596f8b82632d03d2ad8517df2d764
https://github.com/llvm/llvm-project/commit/eb6d5dd90eb596f8b82632d03d2ad8517df2d764
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223346)
Commit: f477555c212d2eddd65f5a791b19efe075e2c708
https://github.com/llvm/llvm-project/commit/f477555c212d2eddd65f5a791b19efe075e2c708
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Memory.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Target/Memory.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Memory cache: no overlap and read across cache entries (#222688)
The memory cache keeps two collections of cached bytes, L1 and L2, which
are named confusingly. L2 holds cache lines at aligned addresses, but
each line size is less than or equal to the fixed line size. L1 holds
pieces from arbitrary addresses with arbitrary lengths. This caused two
problems:
1. A lookup had to find every byte it wanted inside a *single*
entry. A range that spanned two adjacent entries missed even when the
two collections together already held every byte of it. The lookup
rejected such a read rather than take part of it from each entry.
2. The pieces could also overlap each other, which made the lookup
incomplete as well as ambiguous. It examined only the piece starting at
or below the address, so a short piece hid a longer one that covered the
whole read. The read missed with the bytes resident.
This change fixes these problems by introducing these properties to the
cache:
- At most one collection holds any given address.
- The line collection holds only whole, aligned lines (`LineCache`).
- The piece collection holds only fragments smaller than a line, and
they never overlap each other (`ChunkCache`).
- A read takes what it needs from consecutive entries in turn until a
miss (`ReadFromCaches`).
- `AddCacheData` (renamed from `AddL1CacheData`) splits incoming bytes
at line boundaries and drops bytes already held, so callers no longer
pick the cache tier.
Disjoint entries make the cache simple to reason about:
- A read no longer depends on which copy of an address is found first,
because there is only one.
- Probing one candidate is now complete. Since entries cannot
overlap, the entry starting at or below an address is the only one
that can hold it. No byte is stored twice.
- Invalidating an address touches one entry, with no second copy
elsewhere to find and drop.
- Callers of the cache need no knowledge of cache internals.
`ReadRanges` also uses `ReadFromCaches`. Previously, each requested
range had to fit entirely within a single cache entry. Ranges can now
be served across multiple entries and line boundaries. For example,
`Process::ReadCStringsFromMemory` reads strings in 256-byte windows.
Because strings start at arbitrary offsets, these windows frequently
span
two adjacent cache lines. Under the old lookup, such a window missed in
`ReadRanges` even when both lines were resident. It now hits from cache
across the line boundary.
`Flush` now drops all cached entries that intersect the range instead of
erasing only the entry matching the start address. It uses saturating
addition to prevent address wraparound. Its runtime is bounded by the
number of cached entries rather than the range size.
`GrowReadRange` isolates the read-ahead policy from `Read`. It aligns
the read address down to the line base so fetches land in `LineCache` as
whole lines. It caps read-ahead to two lines, skips the last line if
already resident, and clips the read at invalid ranges.
Assited-by: claude
Commit: 9271a73e189508743b4b2ad4393f12d5a8132fa9
https://github.com/llvm/llvm-project/commit/9271a73e189508743b4b2ad4393f12d5a8132fa9
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
Log Message:
-----------
[AMDGPU] Mark `SI_WATERFALL_LOOP` as divergent in `hasDivergentBranch` (#218969)
When a vector instruction takes an SGPR source operand, sinking it out
of a loop with divergent exit would cause the vector instruction to only
get the value from the last iteration in the SGPR. However, in a
divergent loop the value of the SGPR operand may vary across iterations,
so the instruction cannot be sink out of the loop as only using the last
value is incorrect. Before this change `SI_LOOP` was marked as divergent
but `SI_WATERFALL_LOOP` was not, allowing such incorrect sinking for
waterfall loops.
Assisted-by: Claude Code
Commit: 611db63efe0456cca4745930977fcdfe64cc25a9
https://github.com/llvm/llvm-project/commit/611db63efe0456cca4745930977fcdfe64cc25a9
Author: MarkVeerasingam <122292447+MarkVeerasingam at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
Log Message:
-----------
[dfsan] Fix big-endian origin mask (#223247)
Fix the mask used when loading wide shadows on big-endian targets.
The previous expression used a 32-bit integer for the shift, producing
an incorrect zero mask for 64-bit wide shadows. Changed the expression
to use 1ULL so that a 64-bit mask is constructed correctly. The
resulting mask keeps the upper 32 bits and clears the lower 32 bits.
Previously, the big-endian path generated:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, 0
```
With this change, it generates:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, -4294967296
```
Added a SystemZ big-endian regression test.
cc: @uweigand @anoopkg6
Commit: c46d8f243727b467d8803c4b2430534b348daed1
https://github.com/llvm/llvm-project/commit/c46d8f243727b467d8803c4b2430534b348daed1
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
Log Message:
-----------
[SLP]Booleanize logical and/or nodes in the wide leaf type
i1 and/or tree nodes with booleanized wide leaves (one-use truncs of
wide values, zero-tests of values from [0, 1]) are registered in MinBWs
and emitted in the wide type; bit 0 of the result is the final value.
Reviewers: bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/223250
Commit: 27c38b80934067471d7aa7477f894bcb8461a4f3
https://github.com/llvm/llvm-project/commit/27c38b80934067471d7aa7477f894bcb8461a4f3
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16 (#221960)
Use the high 16 bits of a VGPR directly instead of shifting.
Before:
```
v_lshrrev_b32_e32 v1, 16, v0
v_add_f16_e32 v0.l, v0.l, v1.l
```
After:
```
v_add_f16_e32 v0.l, v0.l, v0.h
```
Example: https://godbolt.org/z/c7bE46hzb
Commit: e9d50d35104db2a3ac87e1280e043a0e7f4f7e4d
https://github.com/llvm/llvm-project/commit/e9d50d35104db2a3ac87e1280e043a0e7f4f7e4d
Author: Benedek Kaibas <82393336+benedekaibas at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
A clang/test/Analysis/explicit-lambda-capture.cpp
Log Message:
-----------
[analyzer] Resolve lambda captures for explicit object parameters (#219726)
Currently explicit object parameters are not modeled in the
`VisitCommonDeclRefExpr` function in `ExprEngine`. Because of this when
a lambda has an explicit object parameter and a possible division by
zero the `core.DivideZero` checker does not emit warning. This PR solves
that issue by deciding if the lambda has an explicit object parameter
and then records the binding (if the parameter has the reference type)
between the parameter and the argument's expression otherwise it returns
the captured field's lvalue.
This PR fixes #218708
Commit: eaab447acac971ed7fbcb51c11343db899ad5ffe
https://github.com/llvm/llvm-project/commit/eaab447acac971ed7fbcb51c11343db899ad5ffe
Author: Charles Zablit <c_zablit at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/source/Host/common/XML.cpp
Log Message:
-----------
[lldb] Parse XML files without the deprecated SAX1 API (#222974)
SAX1 is deprecated, switch to SAX2 instead.
Commit: 9fda68e41dcb8d19751bc042508eeee8bd9c596a
https://github.com/llvm/llvm-project/commit/9fda68e41dcb8d19751bc042508eeee8bd9c596a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/AttrDocs.td
Log Message:
-----------
[Clang] Document the interaction of malloc_span and alloc_size (#216967)
The `malloc_span` attribute is intended to be used for
`allocate_at_least`-like functions. Part of that interface is a
guarantee that the number of bytes returned are actually
dereferenceable. Document that, so that we can optimize on it in the
future.
Commit: e9f9afc6042da7cbbf1252702e86783f07cb46f4
https://github.com/llvm/llvm-project/commit/e9f9afc6042da7cbbf1252702e86783f07cb46f4
Author: John Brawn <john.brawn at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
A llvm/test/Transforms/SROA/large-alloca.ll
Log Message:
-----------
[SROA] Use SparseBitVector for splittable offsets (#222306)
Doing this means we consume memory proportional to the number of
offsets, not the size of the alloca as before. Inverting the logic so
that rather than initially marking all offsets as splittable then
removing those that aren't, we instead initially have all offsets
unsplittable and only add those that are splittable, means we should
take time proportional to the number of slices, not to the combined size
of slices.
This means we can remove the limit on alloca size, and this approach
should also be faster.
Commit: 0eaa2e690c85224b0afb700e2e33bbf242e55192
https://github.com/llvm/llvm-project/commit/0eaa2e690c85224b0afb700e2e33bbf242e55192
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llc/lib/BUILD.gn
Log Message:
-----------
[gn] port 474b7358a90e4f2 (llvm/tools/llc/lib) (#223370)
Commit: 77a26fadb88bdc523ef82bcaec8c7e6217701a57
https://github.com/llvm/llvm-project/commit/77a26fadb88bdc523ef82bcaec8c7e6217701a57
Author: Hung-Kuan Tseng <tseng.tim096 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
Log Message:
-----------
[mlir][memref] Keep memref.load attributes when eliding reinterpret_cast (#221314)
`RewriteLoadFromReinterpretCast` rebuilds the load on the source of the
`memref.reinterpret_cast` with the indices remapped to the non-unit
dimensions, but the rebuilt load carries none of `nontemporal`,
`alignment` or `invariant`:
```mlir
%rc = memref.reinterpret_cast %src to offset: [0], sizes: [1, 1, 8], strides: [8, 8, 1] : memref<1x8xf32> to memref<1x1x8xf32>
%0 = memref.load %rc[%c0, %c0, %i] alignment(16) nontemporal(true) invariant(true) : memref<1x1x8xf32>
// -memref-elide-reinterpret-cast today
%0 = memref.load %src[%c0, %i] : memref<1x8xf32>
```
The rewrite only changes how the same element is addressed, so the three
attributes describe the same access. This forwards them. Same shape of
fix as #221312 for `gpu-decompose-memrefs`.
Commit: 26b9d50cbdff788b70a743da97be30c278c5d79b
https://github.com/llvm/llvm-project/commit/26b9d50cbdff788b70a743da97be30c278c5d79b
Author: Jay Foad <jay.foad at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Log Message:
-----------
[AMDGPU] Select the GFX80 encoding family from the subtarget. NFCI. (#219190)
pseudoToMCOpcode() used the D16Buf TSFlag to switch individual instructions to
the GFX80 encoding family on subtargets with UnpackedD16VMem. Select GFX80 for
the whole subtarget instead, and fall back on VI when a pseudo has no GFX80
real. That is what the flag was encoding anyway: only buffer instructions with
unpacked D16 data have a GFX80 encoding.
D16Buf is now unused, so remove it and free up TSFlags bit 50.
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 7b579a91dc6b7df584f021e283004043a402571c
https://github.com/llvm/llvm-project/commit/7b579a91dc6b7df584f021e283004043a402571c
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
Log Message:
-----------
[gn build] Port 240670d0d5dc (#223371)
Commit: 1adf54c67fff78a552e5554f0f8fd783511f8334
https://github.com/llvm/llvm-project/commit/1adf54c67fff78a552e5554f0f8fd783511f8334
Author: Nico Weber <thakis at chromium.org>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port d873afedebd0 (#223372)
Commit: dbe4e7e799bc5e5707334e31dfbc19542388c2ac
https://github.com/llvm/llvm-project/commit/dbe4e7e799bc5e5707334e31dfbc19542388c2ac
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll
Log Message:
-----------
[X86] zero-call-used-regs-simd.ll - add baseline test coverage from #212147 (#223339)
Commit: c013403e8eace0714ded0202be1a220c358233d8
https://github.com/llvm/llvm-project/commit/c013403e8eace0714ded0202be1a220c358233d8
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/CodeGen/AArch64/sve/dup.c
Log Message:
-----------
[clang][cir] Updates SVE tests for dup intrinsics (#222681)
Updates tests for dup intrinsics to match the tests used for classical
code-gen in
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c.
This is in preparation for merging the two files.
Commit: 900b3d6aae5735ba040951d0029161c42da52417
https://github.com/llvm/llvm-project/commit/900b3d6aae5735ba040951d0029161c42da52417
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/C/C23/n2508.c
M clang/test/C/C2y/n3259.c
M clang/test/C/C2y/n3260.c
M clang/test/C/C2y/n3273.c
M clang/test/C/C2y/n3298.c
M clang/test/C/C2y/n3353.c
M clang/test/C/C2y/n3409.c
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/Lexer/cxx2c-raw-strings.cpp
M clang/test/Lexer/hexfloat.cpp
M clang/test/Misc/warning-flags.c
M clang/test/Parser/cxx2c-delete-with-message.cpp
M clang/test/Sema/c2x-attr.c
M clang/test/Sema/fixed-enum.c
M clang/test/Sema/for.c
M clang/test/Sema/pre-c2x-restrict-qualifier.c
M clang/test/SemaCXX/cxx98-compat-pedantic.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/reinterpret-fn-obj-pedantic.cpp
Log Message:
-----------
[Clang] Put compat diagnostics in the pedantic group iff ext_warn==false (#220670)
The `compat-pedantic` groups are supposed to be used if a given
extension is only diagnosed in `-Wpedantic`. Update the compat
diagnostics to reflect this and move various diagnostics that already
adhere to this pattern to compat diagnostics.
Commit: bc5c36113551b13e41606573da58334ea17db1ab
https://github.com/llvm/llvm-project/commit/bc5c36113551b13e41606573da58334ea17db1ab
Author: Bastian Hagedorn <bhagedorn at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
A mlir/test/Target/LLVMIR/nvvm/ex2_invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
Log Message:
-----------
[mlir][NVVM] Add packed EX2 operations (#220501)
Add NVVM dialect operations for the public packed EX2 PTX instructions:
* `nvvm.ex2.f16x2` lowers to `ex2.approx.f16x2`
* `nvvm.ex2.bf16x2` lowers to `ex2.approx.ftz.bf16x2`
The existing scalar `nvvm.ex2` operation is unchanged. Includes LLVM IR
translation tests for both overloads.
Commit: 7421fba54dea2d03ea7b756cc4f0ba248c4e30b3
https://github.com/llvm/llvm-project/commit/7421fba54dea2d03ea7b756cc4f0ba248c4e30b3
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/lib/Core/Relocation.cpp
A bolt/test/RISCV/relr.s
Log Message:
-----------
[BOLT][RISCV] Support reading RV64 RELR relocations (#222265)
Clang linked with packed relative dynamic relocations aborts when the
RELR reader requests the target relative relocation type. Return
`R_RISCV_RELATIVE` for RV64, preserving the RV32 restriction and other
targets.
Assisted by GPT-6.
Commit: fe72b9678b037eaa71627a503dcc17288f9c3811
https://github.com/llvm/llvm-project/commit/fe72b9678b037eaa71627a503dcc17288f9c3811
Author: Yoni Katzuv <yoni.katzuv at quantum-machines.co>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/include/mlir/Analysis/DataFlowFramework.h
M mlir/lib/Analysis/DataFlowFramework.cpp
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
M mlir/test/Analysis/test-foo-analysis.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
Log Message:
-----------
[mlir][dataflow] Deduplicate data-flow solver worklist items (#221983)
The solver enqueues a work item every time a state it depends on
changes, so the same item can appear in the worklist many times.
A duplicate work item is re-processed even though its inputs have not
changed since the previous processing. For example, a dense analysis can
visit a join point with N predecessors up to N times in a row.
To deduplicate the worklist, pending items are tracked using a
`DenseSet`, and an item that is already pending is not pushed again.
Items are removed from the set when dequeued, before being visited, so
an analysis can still re-enqueue the point it is currently visiting.
Since analyses already have to be monotone to reach a fixed point, this
change does not affect analysis results, only the number of visits until
convergence. The test `FooState` used XOR for the join operation, which
is not monotone; the join operation was switched to OR and dependent
tests were updated.
A test that counts how many times a join block with several predecessors
is visited was added to check the deduplication.
Commit: b18c59ead34b97b087146cce7513a060d9ea1b85
https://github.com/llvm/llvm-project/commit/b18c59ead34b97b087146cce7513a060d9ea1b85
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/test/AST/ByteCode/cxx11.cpp
Log Message:
-----------
[clang][bytecode] Improve array index and offset add/sub bounds checks wrt. opaque pointers (#223353)
We were previously causing an assertion since the index had more than 64
bits.
Commit: 013599011a6cc2f5a9d4cbeefc24ee44f3023317
https://github.com/llvm/llvm-project/commit/013599011a6cc2f5a9d4cbeefc24ee44f3023317
Author: Letu Ren <fantasquex at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
Log Message:
-----------
[CIR][X86] Emit cir.clz/cir.ctz for lzcnt/tzcnt builtins (#222669)
These x86 builtins were lowered through cir.call_llvm_intrinsic even
though dedicated CIR bit-count ops already exist.
Assisted-by: grok-4.6
Signed-off-by: Letu Ren <fantasquex at gmail.com>
Commit: f196f6a12bf431a28f76d873e4bdeb3dceac679c
https://github.com/llvm/llvm-project/commit/f196f6a12bf431a28f76d873e4bdeb3dceac679c
Author: Matteo Di Iorio <104271382+splicer3 at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
Log Message:
-----------
[libc][Bazel] Add missing F16 math targets (#222937)
Addresses #221799 by adding all existing F16 tests that were missing
Bazel targets.
Validated by running all 184 F16 tests with bazel test.
Commit: b8c7806bd5e3a40ce3fabd8743d73d77e7a417ab
https://github.com/llvm/llvm-project/commit/b8c7806bd5e3a40ce3fabd8743d73d77e7a417ab
Author: Akash Banerjee <akash.banerjee at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
A flang/test/Lower/OpenMP/target-data-use-device-addr-descriptor.f90
Log Message:
-----------
[Flang][OpenMP] Fix use_device_addr descriptor types (#222961)
Fix invalid FIR for assumed-shape arrays in use_device_addr by using
matching descriptor-reference types and loading the descriptor inside
the region. Added tests.
Co-authored-by: Codex <codex at openai.com>
Commit: 26462ac6c2b0a5932a4354957e6e0ba8f4824383
https://github.com/llvm/llvm-project/commit/26462ac6c2b0a5932a4354957e6e0ba8f4824383
Author: Thrrreeee <shijinrui at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/unittests/Core/BinaryContext.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
M bolt/unittests/Profile/PerfScripts.cpp
Log Message:
-----------
[BOLT][RISCV] Add basic RISC-V initialization support for unit tests (#222883)
This change addresses the uninstantiated test suite failures in
RISC-V-only builds discussed in #217604. That PR proposed a temporary
workaround using GTEST_ALLOW_UNINSTANTIATED_PARAMETERIZED_TEST.
Add the basic setup needed to instantiate and initialize the existing
test suites for riscv64, including the correct ELF machine type and
subtarget features, and remove the temporary allowances.
Commit: 67397010eb5541f08fcdbb8be86b8b799ca88142
https://github.com/llvm/llvm-project/commit/67397010eb5541f08fcdbb8be86b8b799ca88142
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
Log Message:
-----------
[ORC] Use lookupAndApply for EPCGenericRTDyldMemoryManager (#223377)
EPCGenericRTDyldMemoryManager::CreateWithDefaultBootstrapSymbols
resolved its memory-manager and EH-frame symbol addresses with
EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: 9008f496e3dd414cb25aedd47168bc83bf52f470
https://github.com/llvm/llvm-project/commit/9008f496e3dd414cb25aedd47168bc83bf52f470
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
Log Message:
-----------
AMDGPU: Use subarch triples in new tests added since all were converted (#223385)
Commit: 004d5960e8e187b1e2b4a55e6221399aa076c258
https://github.com/llvm/llvm-project/commit/004d5960e8e187b1e2b4a55e6221399aa076c258
Author: Zihao Wang <rekind133 at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-bf16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-f16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-smla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
A llvm/test/Transforms/LoopVectorize/X86/CostModel/partial-reduce-dot-product.ll
Log Message:
-----------
[X86][CodeGen] Support partial-reduce dot products (#205373)
Part of #187779
Lower the llvm.vector.partial.reduce dot product shapes onto the X86 dot
product instructions:
i8 x i8 -> i32: vpdpbusd (AVX512-VNNI, AVX-VNNI)
vpdpbssd / vpdpbuud (AVX-VNNI-INT8, AVX10.2)
i16 x i16 -> i32: vpdpwssd (AVX512-VNNI, AVX-VNNI)
vpdpwsud / vpdpwuud (AVX-VNNI-INT16, AVX10.2)
bf16 x bf16 -> f32: vdpbf16ps (AVX512-BF16)
f16 x f16 -> f32: vdpphps (AVX10.2)
The 128/256-bit shapes, and the 512-bit shapes on targets using 512-bit
registers, are registered as Custom. 512-bit shapes for which only the
VEX
encoding exists are split into two 256-bit dot products, and the
128/256-bit
shapes are widened to 512 bits on targets without VLX.
Teach X86TTIImpl::getPartialReductionCost about these shapes, costing
one
dot product per legal accumulator vector and otherwise falling back to
the
generic expansion cost, so that LoopVectorize can form partial
reductions
for them.
The DAG combiner forms partial reductions with narrower-than-legal types
when the widened shape is supported, so also widen the integer
PARTIAL_REDUCE_*MLA results the same way as PARTIAL_REDUCE_FMLA (expand,
then widen).
Commit: a55e86582aeac1d4af64fa315ed49764c3981fad
https://github.com/llvm/llvm-project/commit/a55e86582aeac1d4af64fa315ed49764c3981fad
Author: Ayokunle Amodu <ayokunle321 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
Log Message:
-----------
[CIR][AMDGPU] Add support for AMDGCN permlane builtins (#223161)
Adds codegen for the following AMDGCN permlane builtins:
- __builtin_amdgcn_permlane_bcast
- __builtin_amdgcn_permlane_up
- __builtin_amdgcn_permlane_down
- __builtin_amdgcn_permlane_xor
These are lowered to the corresponding `llvm.amdgcn.permlane.*`
intrinsics.
Assisted by: Claude Opus 5
Commit: 1af17ef01973f915ccbd168c01da1718097fd7f8
https://github.com/llvm/llvm-project/commit/1af17ef01973f915ccbd168c01da1718097fd7f8
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.h
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
A llvm/unittests/ExecutionEngine/Orc/SimpleRemoteEPCUtilsTest.cpp
Log Message:
-----------
[ORC] Carry out-of-band errors in SimpleRemoteEPC results (#223378)
ORC Wrapper functions may produce out-of-band error results (e.g. due to
serialization errors), but SimpleRemoteEPC / SimpleRemoteEPCServer never
handled these cases (they incorrectly asserted that they never
appeared).
Update the SimpleRemote protocol to use the TagAddr field (previously
unused for result messages) to encode Result message kinds: either a
Value, or an OutOfBandError. This allows out-of-band errors to flow
across the wire and be passed as results to their callers.
encodeResultMessage and decodeResultMessage implement the format /
handling: out-of-band errors (or failures to deserialize out-of-band
errors) are now passed to handlers as out-of-band error results. An
invalid Result message kind in the TagAddr field results in an
llvm::Error, ending the session.
SimpleRemoteEPCUtilsTest covers both kinds' round-trips, an unrecognized
kind, and a malformed out-of-band payload.
Commit: ea4b78c309418a395d3a36e3319d65c4cfd9f2b4
https://github.com/llvm/llvm-project/commit/ea4b78c309418a395d3a36e3319d65c4cfd9f2b4
Author: Donát Nagy <donat.nagy at ericsson.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
Log Message:
-----------
[analyzer] Chain checkers in runCheckersForEndFunction (#220970)
The function `runCheckersForEndFunction` had an unusual behavior that it
invoked the callbacks in parallel (introducing a new execution path for
each checker callback that produced a transition), unlike all other
analogous functions, which "chained" the checkers, executing them after
each other.
This behavior was introduced before 2011, when this callback was called
`check::EndPath`, to ensure that the `EndPath` callbacks are _final_ and
nodes created by them end up at the end of the execution path. When
interprocedural analysis (inlining functions) was introduced in 2013,
the callback was renamed to `EndFunction` (to reflect that it also
activates at the end of inlined functions), but the unusual behavior was
preserved.
There were 8 "real" checkers with `check::EndFunction` callbacks, but
most of them only created error nodes or did "nice to have" cleanup, so
the irregular behavior of this callback did not cause visible trouble.
However, none of the checkers actually _relies_ on the parallel
execution of the callbacks and the unusual transition pattern seriously
violates the established patterns of the analyzer; so this commit
rewrites `runCheckersForEndFunction` to follow the standard logic.
This may slightly perturb the analysis results (because it changes the
"shape" of the exploded graph), but -- based on my review of the
upstream EndFunction checkers -- should not cause any directed
functional changes.
For more background details see also the github review comments at
https://github.com/llvm/llvm-project/pull/217319#discussion_r3812950071
Commit: d57b857099bddf47c83317e64195d795015cabbd
https://github.com/llvm/llvm-project/commit/d57b857099bddf47c83317e64195d795015cabbd
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/Scalar/GVN.h
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[GVN] Deduplicate compare expressions creation (NFC) (#223389)
Minor opportunity to create GVN expressions for cmp instructions via
existing dedicated `createCmpExpr` handler.
Commit: 8fcab5cc958abe25199219ce3f7a4b53828e195d
https://github.com/llvm/llvm-project/commit/8fcab5cc958abe25199219ce3f7a4b53828e195d
Author: Adam Smith <adams at nvidia.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M bolt/lib/Core/Relocation.cpp
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
A bolt/test/RISCV/relr.s
M bolt/unittests/Core/BinaryContext.cpp
M bolt/unittests/Core/CMakeLists.txt
M bolt/unittests/Core/MCPlusBuilder.cpp
M bolt/unittests/Core/MemoryMaps.cpp
M bolt/unittests/Profile/CMakeLists.txt
M bolt/unittests/Profile/PerfScripts.cpp
M clang-tools-extra/clang-tidy/readability/ConvertMemberFunctionsToStaticCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.md
M clang-tools-extra/test/clang-tidy/checkers/readability/convert-member-functions-to-static.cpp
M clang/docs/CIR/CleanupAndEHDesign.md
M clang/docs/ReleaseNotes.md
M clang/docs/UsersManual.md
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/Diagnostic.td
M clang/include/clang/Basic/DiagnosticLexKinds.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/CIR/Dialect/IR/CIRDialect.td
M clang/include/clang/CIR/Dialect/IR/CIROpenCLAttrs.td
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Options/Options.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngine.h
M clang/lib/AST/ByteCode/Interp.cpp
M clang/lib/AST/ByteCode/Interp.h
M clang/lib/AST/ByteCode/InterpBuiltinObjectSize.cpp
M clang/lib/AST/ByteCode/Pointer.cpp
M clang/lib/AST/ByteCode/Pointer.h
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinAMDGPU.cpp
M clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
M clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.cpp
M clang/lib/CIR/CodeGen/CIRGenModule.h
M clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CIR/Dialect/IR/CIRDialect.cpp
M clang/lib/CIR/Dialect/IR/CIROpenCLAttrs.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.cpp
M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVMOpenCLMetadata.h
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cuda.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Lex/LiteralSupport.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaCast.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Core/CheckerManager.cpp
M clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
M clang/test/AST/ByteCode/cxx11.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
A clang/test/Analysis/explicit-lambda-capture.cpp
M clang/test/C/C23/n2508.c
M clang/test/C/C2y/n3259.c
M clang/test/C/C2y/n3260.c
M clang/test/C/C2y/n3273.c
M clang/test/C/C2y/n3298.c
M clang/test/C/C2y/n3353.c
M clang/test/C/C2y/n3409.c
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenBuiltins/X86/bmi-builtins.c
M clang/test/CIR/CodeGenBuiltins/X86/lzcnt-builtins.c
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenHIP/amdgcnspirv-kernel.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn-gfx1250.hip
M clang/test/CIR/CodeGenHIP/builtins-amdgcn.hip
M clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
A clang/test/CIR/CodeGenOpenCL/version.cl
A clang/test/CIR/IR/invalid-version.cir
A clang/test/CIR/IR/version.cir
A clang/test/CIR/Lowering/opencl-version-metadata.cir
M clang/test/CIR/Transforms/cxx-abi-lowering-attrs.cir
M clang/test/CXX/drs/cwg1xx.cpp
M clang/test/CXX/drs/cwg5xx.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/AArch64/sve/dup.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A clang/test/CodeGen/keep-inline-functions.c
A clang/test/CodeGen/keep-inline-functions.cpp
A clang/test/CodeGen/keep-inline-functions.cppm
M clang/test/CodeGen/ms-setjmp.c
A clang/test/CodeGen/thread-model.c
M clang/test/CodeGenCUDASPIRV/kernel-cc.cu
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
M clang/test/CodeGenHIP/hipspv-kernel.cpp
A clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fkeep-inline-functions.c
M clang/test/Driver/mingw.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/sparc-as.c
M clang/test/Driver/wasm-toolchain.c
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Lexer/cxx2c-raw-strings.cpp
M clang/test/Lexer/hexfloat.cpp
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M clang/test/Misc/warning-flags.c
M clang/test/OffloadTools/clang-nvlink-wrapper/nvlink-wrapper.c
M clang/test/Parser/cxx-extra-semi.cpp
M clang/test/Parser/cxx2c-delete-with-message.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/c2x-attr.c
M clang/test/Sema/fixed-enum.c
M clang/test/Sema/for.c
M clang/test/Sema/pre-c2x-restrict-qualifier.c
M clang/test/SemaCXX/blocks.cpp
M clang/test/SemaCXX/cxx2c-fold-exprs.cpp
M clang/test/SemaCXX/cxx98-compat-pedantic.cpp
M clang/test/SemaCXX/cxx98-compat.cpp
M clang/test/SemaCXX/enum.cpp
M clang/test/SemaCXX/ms-ctor-closure.cpp
M clang/test/SemaCXX/reinterpret-fn-obj-pedantic.cpp
A clang/test/SemaHIP/atomic-init.hip
M clang/test/SemaTemplate/concepts-lambda.cpp
M clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang/docs/OpenMP-declare-target.md
M flang/include/flang/Lower/OpenMP/Clauses.h
A flang/include/flang/Optimizer/Builder/Runtime/CUDA/Support.h
M flang/include/flang/Optimizer/OpenACC/Passes.td
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP/Clauses.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/Builder/CMakeLists.txt
A flang/lib/Optimizer/Builder/Runtime/CUDA/Support.cpp
M flang/lib/Optimizer/OpenACC/Transforms/ACCRecipeBufferization.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/MapInfoFinalization.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/lib/Optimizer/Transforms/LoopInvariantCodeMotion.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
M flang/test/Driver/flang-f-opts.f90
M flang/test/Driver/frame-pointer-forwarding.f90
M flang/test/Fir/OpenACC/recipe-bufferization.mlir
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
M flang/test/Lower/CUDA/cuda-return01.cuf
M flang/test/Lower/CUDA/cuda-return02.cuf
M flang/test/Lower/OpenACC/acc-declare-globals.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
A flang/test/Lower/OpenMP/omp-lib-integer-wrappers.f90
A flang/test/Lower/OpenMP/target-data-use-device-addr-descriptor.f90
M flang/test/Lower/module-parameter-linkonce-odr.f90
M flang/test/Transforms/OpenACC/acc-recipe-materialization-parallel.fir
M flang/test/Transforms/OpenACC/acc-recipe-materialization-reduction.fir
A flang/test/Transforms/function-attr-frame-pointer.fir
M flang/test/Transforms/licm.fir
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/__support/FPUtil/float80.h
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
A libc/utils/mathtools/wc_to_bin.py
M libcxx/docs/Status/Cxx26Issues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
A libcxx/test/std/utilities/meta/meta.unary/meta.unary.prop/has_unique_object_representations.verify.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
M lld/ELF/ICF.cpp
M lld/ELF/SymbolTable.cpp
M lld/ELF/SymbolTable.h
R lld/test/ELF/dynamic-list-cpp.s
M lld/test/ELF/dynamic-list-glob.s
M lld/test/ELF/lto/riscv-target-abi.ll
R lld/test/ELF/version-script-reassign-glob.s
A lld/test/ELF/version-script-wildcard-precedence.s
M lldb/include/lldb/Host/SafeMachO.h
M lldb/include/lldb/Target/Memory.h
M lldb/source/Host/common/XML.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Target/Memory.cpp
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/ObjectFile/MachO/TestObjectFileMachO.cpp
M lldb/unittests/Target/MemoryTest.cpp
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/LangRef.md
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/OrcRTBridge.h
M llvm/include/llvm/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/OpenMP/ClauseT.h
M llvm/include/llvm/Frontend/OpenMP/OMP.td
M llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/IR/Module.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerImpl.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Support/Allocator.h
M llvm/include/llvm/Support/CodeGen.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/Support/MathExtras.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/include/llvm/Transforms/Scalar/GVN.h
A llvm/include/llvm/Transforms/Utils/SplitModuleCommon.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SafeStack.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/OrcRTBridge.cpp
M llvm/lib/ExecutionEngine/Orc/Shared/SimpleRemoteEPCUtils.cpp
M llvm/lib/ExecutionEngine/Orc/SimpleRemoteEPC.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleExecutorMemoryManager.cpp
M llvm/lib/ExecutionEngine/Orc/TargetProcess/SimpleRemoteEPCServer.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Dominators.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Module.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Support/CMakeLists.txt
M llvm/lib/Support/KnownFPClass.cpp
M llvm/lib/Support/Unix/Path.inc
M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
M llvm/lib/Target/X86/X86TargetTransformInfo.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/CMakeLists.txt
M llvm/lib/Transforms/Utils/RelLookupTableConverter.cpp
M llvm/lib/Transforms/Utils/SplitModule.cpp
A llvm/lib/Transforms/Utils/SplitModuleCommon.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPReductionUtils.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/Analysis/ScalarEvolution/pointer-iv-addrec.ll
A llvm/test/Assembler/llvm.loop.align.ll
A llvm/test/Assembler/module-flags-thread-model.ll
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.ll
M llvm/test/CodeGen/AArch64/cmpbr-ccmp.mir
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
A llvm/test/CodeGen/AArch64/misched-postra-only1.mir
A llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AMDGPU/addrspacecast-barrier.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/barrier-addrspace-dereference.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/null-named-barrier-gv.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-byte-ptr-cast.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/sint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.f64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
A llvm/test/CodeGen/ARM/cbz-no-kill-flag.mir
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/atomic64-typed-resource.ll
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
A llvm/test/CodeGen/NVPTX/atomics-system-scope-sm50.err.ll
M llvm/test/CodeGen/NVPTX/cmpxchg.ll
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/RISCV/target-abi-invalid.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
M llvm/test/CodeGen/X86/cmp-shiftX-maskX.ll
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-bf16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-fmla-f16.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-smla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-sumla.ll
A llvm/test/CodeGen/X86/vector-partial-reduce-umla.ll
M llvm/test/CodeGen/X86/zero-call-used-regs-simd.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
A llvm/test/Linker/module-flags-thread-model.ll
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
R llvm/test/MC/RISCV/XVentanaCondOps-valid.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/MC/RISCV/target-abi-invalid.s
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/test/TableGen/directive1.td
M llvm/test/TableGen/directive2.td
A llvm/test/Transforms/AggressiveInstCombine/RISCV/lit.local.cfg
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/select-of-bittest.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
A llvm/test/Transforms/InstCombine/uitofp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
A llvm/test/Transforms/LoopVectorize/X86/CostModel/partial-reduce-dot-product.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/induction-cost.ll
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
A llvm/test/Transforms/RelLookupTableConverter/AArch64/dynamic_relocs.ll
M llvm/test/Transforms/RelLookupTableConverter/AArch64/no_relative_lookup_table.ll
R llvm/test/Transforms/RelLookupTableConverter/X86/relative_lookup_table.ll
A llvm/test/Transforms/RelLookupTableConverter/relative_lookup_table.ll
M llvm/test/Transforms/SLPVectorizer/X86/and-neg-pow2-copyable.ll
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps-2.ll
A llvm/test/Transforms/SLPVectorizer/X86/cancelled-copyable-self-use-deps.ll
A llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
M llvm/test/Transforms/SLPVectorizer/X86/logical-reduction-booleanized-leaves.ll
A llvm/test/Transforms/SROA/large-alloca.ll
A llvm/test/Transforms/SafeStack/X86/pointer-address-domtree.ll
A llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-indirect-call-anchor.prof
A llvm/test/Transforms/SampleProfile/Inputs/profile-mismatch-indirect-call.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-multiple-sampled-callees.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-zero-callee.prof
A llvm/test/Transforms/SampleProfile/non-probe-stale-profile-indirect-call-anchor.ll
A llvm/test/Transforms/SampleProfile/profile-mismatch-indirect-call.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch.ll
A llvm/test/Verifier/llvm.loop.align.ll
A llvm/test/Verifier/module-flags-thread-model.ll
A llvm/test/tools/dsymutil/Inputs/member-hash/2.o
A llvm/test/tools/dsymutil/Inputs/member-hash/debug-map.map
A llvm/test/tools/dsymutil/X86/member-hash.cpp
M llvm/test/tools/llubi/fp_cast.ll
M llvm/test/tools/llvm-split/unnamed.ll
M llvm/tools/llc/CMakeLists.txt
R llvm/tools/llc/NewPMDriver.cpp
R llvm/tools/llc/NewPMDriver.h
A llvm/tools/llc/lib/CMakeLists.txt
A llvm/tools/llc/lib/NewPMDriver.cpp
A llvm/tools/llc/lib/NewPMDriver.h
A llvm/tools/llc/lib/llcdriver.cpp
R llvm/tools/llc/llcdriver.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
M llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt
M llvm/unittests/ExecutionEngine/Orc/EPCGenericJITLinkMemoryManagerTest.cpp
A llvm/unittests/ExecutionEngine/Orc/SimpleRemoteEPCUtilsTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Support/AllocatorTest.cpp
M llvm/unittests/Support/KnownFPClassTest.cpp
M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/Basic/DirectiveEmitter.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M llvm/utils/gn/secondary/lldb/source/Plugins/SymbolFile/DWARF/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/HLSL/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Transforms/Utils/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
A llvm/utils/gn/secondary/llvm/tools/llc/lib/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Frontend/BUILD.gn
M mlir/examples/toy/Ch2/mlir/Dialect.cpp
M mlir/examples/toy/Ch3/mlir/Dialect.cpp
M mlir/examples/toy/Ch4/mlir/Dialect.cpp
M mlir/examples/toy/Ch5/mlir/Dialect.cpp
M mlir/examples/toy/Ch6/mlir/Dialect.cpp
M mlir/examples/toy/Ch7/mlir/Dialect.cpp
M mlir/include/mlir/Analysis/DataFlowFramework.h
M mlir/include/mlir/CAPI/Wrap.h
M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACC.h
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/Tosa/Utils/ConversionUtils.h
M mlir/include/mlir/IR/BuiltinTypes.td
M mlir/include/mlir/Query/Matcher/Marshallers.h
M mlir/include/mlir/Support/DebugStringHelper.h
M mlir/lib/Analysis/DataFlowFramework.cpp
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
M mlir/lib/Dialect/Affine/Utils/LoopUtils.cpp
M mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Loops.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MemRef/Transforms/ElideReinterpretCast.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCImplicitData.cpp
M mlir/lib/Dialect/OpenACC/Transforms/ACCRecipeMaterialization.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Dialect/PDLInterp/IR/PDLInterp.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Utils/Utils.cpp
M mlir/lib/Dialect/SMT/IR/SMTOps.cpp
M mlir/lib/Dialect/SPIRV/IR/MemoryOps.cpp
M mlir/lib/Dialect/Shape/IR/Shape.cpp
M mlir/lib/Dialect/Shard/Transforms/Partition.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaNarrowTypes.cpp
M mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/BuiltinTypes.cpp
M mlir/lib/IR/MLIRContext.cpp
M mlir/lib/IR/TypeDetail.h
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Tools/mlir-pdll-lsp-server/Protocol.cpp
M mlir/test/Analysis/DataFlow/test-staged-analyses.mlir
M mlir/test/Analysis/test-foo-analysis.mlir
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
M mlir/test/Dialect/MemRef/elide-reinterpret-cast-load.mlir
M mlir/test/Dialect/OpenACC/acc-implicit-data.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-parallel.mlir
M mlir/test/Dialect/OpenACC/acc-recipe-materialization-reduction.mlir
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/IR/invalid-builtin-types.mlir
M mlir/test/IR/parser.mlir
A mlir/test/Target/LLVMIR/nvvm/ex2_invalid.mlir
M mlir/test/Target/LLVMIR/nvvm/transcendentals.mlir
M mlir/test/lib/Analysis/TestDataFlowFramework.cpp
M openmp/device/include/Interface.h
M openmp/device/src/State.cpp
M openmp/module/omp_lib.F90.var
M openmp/runtime/src/dllexports
M openmp/runtime/src/include/omp.h.var
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_csupport.cpp
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_ftn_os.h
M openmp/runtime/src/kmp_stub.cpp
A openmp/runtime/test/api/kmp_integer_8_apis.f90
M orc-rt/CMakeLists.txt
M orc-rt/docs/CodingConventions.md
M orc-rt/include/CMakeLists.txt
M orc-rt/include/orc-rt-c/support/CoreTypes.h
M orc-rt/include/orc-rt-c/support/Error.h
A orc-rt/include/orc-rt-c/support/RTTI.h
A orc-rt/include/orc-rt/bedrock/SocketHandle.h
M orc-rt/include/orc-rt/bedrock/sps/SimpleRemoteCA.h
M orc-rt/include/orc-rt/support/Error.h
M orc-rt/include/orc-rt/support/RTTI.h
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/lib/bedrock/sps/SimpleRemoteCA.cpp
A orc-rt/lib/bedrock/sys/posix/SocketHandle.cpp
M orc-rt/lib/support/Error.cpp
M orc-rt/lib/support/RTTI.cpp
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
A orc-rt/test/unit/Inputs/RTTICrossDylibTestError.h
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.cpp
A orc-rt/test/unit/Inputs/RTTICrossDylibTestLib.h
A orc-rt/test/unit/bedrock/SocketHandleTest.cpp
A orc-rt/test/unit/bedrock/SocketTestUtils.h
M orc-rt/test/unit/bedrock/sps/SimpleRemoteCATest.cpp
A orc-rt/test/unit/bedrock/sys/posix/SocketTestUtils.cpp
M orc-rt/test/unit/support/CAPICompileTest.c
M orc-rt/test/unit/support/ErrorCAPITest.cpp
M orc-rt/test/unit/support/ErrorExceptionInteropTest.cpp
M orc-rt/test/unit/support/ErrorTest.cpp
A orc-rt/test/unit/support/RTTICrossDylibTest.cpp
M orc-rt/test/unit/support/RTTITest.cpp
M orc-rt/tools/ogre/CMakeLists.txt
M polly/include/polly/ScopInfo.h
M utils/bazel/llvm-project-overlay/libc/startup/linux/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/startup/linux/x86_64/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPCWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Merge branch 'main' into users/adams381/cir-callconv-dropped-return-res-attrs
Compare: https://github.com/llvm/llvm-project/compare/9d17025dd4ef...8fcab5cc958a
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