[all-commits] [llvm/llvm-project] f4ecba: [KnownFPClass] Unify and refine interested classes...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Sep 14 04:18:07 PDT 2026
Branch: refs/heads/users/alexey-bataev/spr/slpcost-based-choice-of-the-i1-reduction-form
Home: https://github.com/llvm/llvm-project
Commit: f4ecba36726d6bede2ab58890dfcc861c2bb28a9
https://github.com/llvm/llvm-project/commit/f4ecba36726d6bede2ab58890dfcc861c2bb28a9
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
Log Message:
-----------
[KnownFPClass] Unify and refine interested classes for `KnownFPClass::log` (#219751)
Previously, `ValueTracking` and `GISelValueTracking` only called
`KnownFPClass::log` when the requested classes included NaN or infinity.
As a result, narrowly interested queries could miss unconditional
deductions, for example, `log(x)` is never subnormal or negative zero
(With the exception of `PPCDoubleDouble`
https://github.com/llvm/llvm-project/issues/217658).
This change makes the interested-class handling consistent between
`ValueTracking` and `GISelValueTracking`. The source is queried only
when its classes are needed, but `KnownFPClass::log` is always called so
its unconditional deductions are preserved.
Future work:
- Fixing `KnownFPClass::log` for `PPCDoubleDouble`.
AI disclosure:
I used OpenAI Codex (sol 5.6) to help write the unit tests, which I
reviewed and ran locally.
Commit: c1f1a288ccd67f9b9dadefda9c510aa7568022e7
https://github.com/llvm/llvm-project/commit/c1f1a288ccd67f9b9dadefda9c510aa7568022e7
Author: Vicky Nguyen <vicky.trucviennguyen at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
Log Message:
-----------
[CIR][AArch64] Complete upstream vector saturating shift left NEON builtins (#221507)
Related to https://github.com/llvm/llvm-project/issues/185382
CIR lowering for the vector saturating shift left intrinsics
(https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-saturating-shift-left).
This completes the family.
Port tests from `clang/test/CodeGen/AArch64/neon-intrinsics.c` to
`clang/test/CodeGen/AArch64/neon/intrinsics.c`.
Commit: 0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
https://github.com/llvm/llvm-project/commit/0eac970fa7478ddf0083dc2a0a5c476ca3bb615a
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
Log Message:
-----------
RegisterCoalescer: Remove empty subranges after merging subranges (#222050)
Merging subranges in joinVirtRegs didn't try to clear empty ranges after
refineSubRanges, manifesting in an assert in overlaps checks later.
Exposed with subregister liveness once LiveIntervals runs before
TwoAddress.
Co-authored-by: Claude (Claude-Opus-4.8)
Commit: cff226a5716e4bc3589d4869066ea6687ed142ce
https://github.com/llvm/llvm-project/commit/cff226a5716e4bc3589d4869066ea6687ed142ce
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
Log Message:
-----------
[ConstraintElim] Fold sadd.with.overflow with a constant op. (#223239)
Generalize the overflow-math simplification to also allow simplifying
sadd.with.overflow if the second operand is constant, using
makeGuaranteedNoWrapRegion.
Note that this partially overlaps with the flag strengthening logic.
I'll share a patch soon to try to unify the code more.
No improvements in llvm-opt-benchmarks-nightly. It improves end-to-end
optimizations for Swift (which emits a lot of checked arithmetic) and
also Clang + UBsan.
An end-to-end improvement with overflow intrinsics is
https://llvm.godbolt.org/z/6nrj7aodd.
PR: https://github.com/llvm/llvm-project/pull/223239
Commit: 979b374a7ca7adc936d9339c1db79b0d6cda06db
https://github.com/llvm/llvm-project/commit/979b374a7ca7adc936d9339c1db79b0d6cda06db
Author: Ömer Sinan Ağacan <omer at osa1.net>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
Log Message:
-----------
[AggressiveInstCombine] Fix terminology in a few comments (NFC) (#222327)
Fix the comments (and a debug print) that say "dominated by trunc"
rather than "post-dominated".
Also fixes a Doxygen syntax (use \p instead of /p) and fix
capitalization in the middle of a sentence.
Commit: d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
https://github.com/llvm/llvm-project/commit/d36b94ae1dc4a61d3ccff73330adbe571ef1ccd6
Author: Taimuraz Kaitmazov <5769345+atassis at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
Log Message:
-----------
[MIRParser] Reject a one-element fixed-length vector type (#213290)
MIParser accepts `<1 x sN>` and then asserts while building the LLT, so
llc aborts during parsing instead of reporting a parse error:
```
Assertion `!EC.isScalar() && "invalid number of vector elements"' failed.
```
LLT has no one-element fixed-length vector. `getLLTForType`,
`getLLTForMVT` and
`LLT::changeElementCount` all map a one-element `ElementCount` to the
element
type through `LLT::scalarOrVector`, nothing calls `LLT::fixed_vector(1,
...)`,
and no in-tree .mir test uses the syntax. `verifyVectorElementCount`
already rejects 0 and anything above 2^16, so 1 was the remaining hole; it now
gets the same diagnostic instead of aborting the parser.
Scalable vectors are unaffected: `<vscale x 1 x sN>` is a valid type and
stays legal through the `HasVScale` check.
AI assistance: drafted with AI help; reviewed and validated by me.
Commit: ce73dba9552c93d1cc3abc481dff63a4ab6d0579
https://github.com/llvm/llvm-project/commit/ce73dba9552c93d1cc3abc481dff63a4ab6d0579
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
Log Message:
-----------
[clang][SPIR-V][AMDGPU] Fix variadic aggregate ABI classification for AMDGCN (#216326)
Mirror AMDGPUABIInfo fixed/variadic split
AMDGCNSPIRVABIInfo::classifyArgumentType did not distinguish fixed from
variadic arguments, so aggregates passed through `...` were
misclassified as indirect byref instead of direct
Commit: d91624c19074e219d5a5c5af45f48afd4cd9052a
https://github.com/llvm/llvm-project/commit/d91624c19074e219d5a5c5af45f48afd4cd9052a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
Log Message:
-----------
[AMDGPU] Fix MAI hazard scan missing 19-instruction-old hazards (#222040)
The scan only looked back 19 instructions, but gfx950 can need a gap of
20 after some MFMAs
A hazard exactly 19 instructions back was missed, so no wait was
inserted
Commit: 8864a4bb996d6bb541b0974d34991da40a643c90
https://github.com/llvm/llvm-project/commit/8864a4bb996d6bb541b0974d34991da40a643c90
Author: neoto <48843913+neoto at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
Log Message:
-----------
[Mips] Handle division by zero trap on MIPS1 (#201133)
LLVM currently emits the `teq` instruction for every arch version, but
`teq` is unsupported on MIPS1.
This special cases MIPS1 so that `bne(z)` and `break` are emitted
instead.
Compared to https://github.com/llvm/llvm-project/pull/81311, this should
also handle liveness as far as I can tell.
I didn't want to add another bool to the argument list so I combined
`IsMicroMips` and what was supposed to be `IsMips1` into an enum, which
feels much nicer in this case.
Besides that and the main change, I also changed the `hasSideEffects`
bit for `PseudoSDIV` and `PseudoUDIV`,
which allows the delay slot to be usefully filled - well, at least with
`-O1`+. This seems to be in line with what GCC does:
https://godbolt.org/z/zqcG5ha35
Tested using clang directly and through Zig's LLVM backend.
Closes https://github.com/llvm/llvm-project/issues/80554
Supersedes https://github.com/llvm/llvm-project/pull/81311
Commit: 85f694b3eeafc07e5c586fa15715facefba71094
https://github.com/llvm/llvm-project/commit/85f694b3eeafc07e5c586fa15715facefba71094
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
Log Message:
-----------
[ASan] Convert pointer-pair operands based on type (#218494)
`CreatePointerCast` was being called on everything without checking what
it actually is, so if the operand came from ptrtoint ... to i32 it just
crashes (its not a pointer).
now it check the type first - pointers get pointer-cast, ints get
zext/trunc'd to intptr width.
Fixes #217544
also edited regression tests for this
Commit: 4098f568c46e06b6df470111868b4c165dd80f4d
https://github.com/llvm/llvm-project/commit/4098f568c46e06b6df470111868b4c165dd80f4d
Author: Dhairyashil R G <dhairyashil25 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Don't fold in_bounds for negative constant indices (#219681)
`isInBounds` checked only that the transfer *ends* inside the source:
return cstOp.value() + vectorSize <= sourceSize;
The `in_bounds` attribute promises more than that. Its definition in
VectorOps.td says accesses "(including the starting point)" may run
out-of-bounds when it is "false", so setting it to "true" is a claim
about the start of the transfer as well as its end.
With a negative constant index the two disagree. For
vector.transfer_read %m[-1] : memref<8xf32>, vector<4xf32>
`-1 + 4 <= 8` holds, so the fold set `in_bounds = [true]`, even though
element -1 is read from outside `%m`.
The same expression also overflows for a large enough index: at `index =
2^63 - 1` the addition wraps and the fold again reports `in_bounds =
[true]`. Computing the bound as `sourceSize - vectorSize` instead avoids
the addition entirely; both operands are static, non-negative dimension
sizes, so the subtraction cannot overflow.
This is a spec-conformance fix, not a live miscompile report. A negative
index into a memref is already undefined behaviour, and the masked
lowering would not have caught it either: the guard
`generateInBoundsCheck` emits in VectorToSCF is `memrefDim > index +
iv`, an upper-bound check only.
Adds three regression tests, each of which fails without the change.
Assisted-by: Claude
Commit: b7877e01cb1087d81fd72eb320c3c7d3f8e03500
https://github.com/llvm/llvm-project/commit/b7877e01cb1087d81fd72eb320c3c7d3f8e03500
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
Log Message:
-----------
[ConstraintElim] Derive an unsigned IV bound from a signed relational latch. (#222762)
For a known non-negative backedge (either via isKnownNonNegative or
because the increment is increasing), 0 <=s PN <= B holds and implies
that B is non-negative as well.
Use that to translate a signed condition to the equivalent unsigned one.
Note that the general signed->unsigned rewrite cannot catch this,
because the precondition also needs rewriting to unsigned.
No llvm-opt-benchmark-nightly impact, but it can help remove runtime
checks generated by sanitizers or Swift code. An end-to-end C example is
https://clang.godbolt.org/z/vbd91MjaM.
Alive2 Proof: https://alive2.llvm.org/ce/z/G3Mv7t
PR: https://github.com/llvm/llvm-project/pull/222762
Commit: 914e15cd29f78e01e15378cfccff97d42e6e9e82
https://github.com/llvm/llvm-project/commit/914e15cd29f78e01e15378cfccff97d42e6e9e82
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Move the LLVMContext out of ReplaceableMetadataImpl. NFC (#222085)
No ReplaceableMetadataImpl method reads its LLVMContext reference, and
ValueAsMetadata reaches the context through the wrapped Value. Keep the
reference in a derived ReplaceableUsesWithContext, used by the two
owners with no other route to it: MDNode's on-demand RAUW support and
DIArgList.
Rename the base to ReplaceableUses: it is the use map behind RAUW for
the metadata kinds that support it, not a pimpl, and the name matches
ContextAndReplaceableUses and getReplaceableUses().
Make the base destructor protected, since getOrCreate() hands out
ReplaceableUses pointers that must never be deleted. Delete copy
assignment explicitly; the LLVMContext reference suppresses it
implicitly.
sizeof(ValueAsMetadata) 152 -> 144.
Aided by Opus 5
Commit: d44791d35a4b15f3da7855790203ca14f7953410
https://github.com/llvm/llvm-project/commit/d44791d35a4b15f3da7855790203ca14f7953410
Author: averne <45773016+averne at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
Log Message:
-----------
[AMDGPU] IGLP: Sanitize user schedule hints (#221256)
Fixes the following ICE:
```cpp
extern __shared__ int lds[];
__global__
void kern_ice() {
auto _ = lds[threadIdx.x];
__builtin_amdgcn_sched_barrier(~0x380); // Allow all except DS instructions
}
```
See: https://godbolt.org/z/oGfT1TTa4
Commit: cba24d6a935382154b0487d09c1d91a0e2bda04b
https://github.com/llvm/llvm-project/commit/cba24d6a935382154b0487d09c1d91a0e2bda04b
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Generalize folding IV increment into phi start value (NFC). (#223260)
simplifyRecipe folds
X = phi(0, IVInc)
IVInc = X + Step
Def = IVInc + Y
into a phi starting at Y, but only if Y is a live-in. Also allow values
defined in the block the phi's start value is coming from, which is
where the value conservatively has to be available.
NFC today, but preparation for modeling the full epilogue skeleton in
VPlan.
Commit: 8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
https://github.com/llvm/llvm-project/commit/8e23b6dfccb42a599e82c6a6c1a13bfb0a546c9e
Author: Shilei Tian <i at tianshilei.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
Log Message:
-----------
[NFC][AMDGPU] Fix clang-tidy warnings in VOPD related files (#223261)
Commit: 86858de86cb28299ebc9c0ce8a06e5a61ed6b261
https://github.com/llvm/llvm-project/commit/86858de86cb28299ebc9c0ce8a06e5a61ed6b261
Author: Aayush Shrivastava <iamaayushrivastava at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/test/Headers/__clang_hip_math.hip
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
M llvm/unittests/Analysis/ValueTrackingTest.cpp
Log Message:
-----------
[ValueTracking] Propagate non-negativity through fptosi (#217868)
Fixes #217442
`fptosi` is poison when the rounded value does not fit in the result
type, so `computeKnownBits` can assume the conversion rounds towards
zero without wrapping. Negative subnormals and negative zero always
round to 0, so only sources known to never be a negative normal or
negative infinity (i.e. values <= -1.0) can produce a negative result.
This lets InstCombine fold `(int)fabs(x) < 0` to `false`, matching GCC,
and also benefits other magnitude-clamping intrinsics such as sqrt.
Commit: 667efaee701ae5345f4cde42f8b3e5b7f98549ee
https://github.com/llvm/llvm-project/commit/667efaee701ae5345f4cde42f8b3e5b7f98549ee
Author: Benji Smith <6193112+Benjins at users.noreply.github.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
Log Message:
-----------
[InstCombine] Fix fold of comparison of rotates (#223263)
rotate(X, AmtX) == rotate(Y, AmtY) -> rotate(X, AmtX - AmtY) == Y
This fold is usually valid, but implicitly assumed that the bit width
was a power of two. This is now checked and the transform doesn't fire
if the bit width isn't a power of two.
Fixes https://github.com/llvm/llvm-project/issues/223262
Commit: 0485ad7e469a56443094872c0f57f2870eccb654
https://github.com/llvm/llvm-project/commit/0485ad7e469a56443094872c0f57f2870eccb654
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
A clang/test/CodeGen/thread-model.c
Log Message:
-----------
clang: Emit the "thread-model" module flag (#223156)
Commit: eb5c148b1cbc89c75a57a505d2533ae52e5bde44
https://github.com/llvm/llvm-project/commit/eb5c148b1cbc89c75a57a505d2533ae52e5bde44
Author: zhouguangyuan0718 <zhouguangyuan.xian at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
Log Message:
-----------
[MachineScheduler] Order fixed-FI memory operations by object offset (#219669)
## Summary
- sort fixed frame-index memory operands by their explicit stack offsets
- preserve the existing frame-index ordering for ordinary stack objects
and as a tie-breaker
- add an AArch64 MIR regression with fixed objects created out of offset
order
## Background
`BaseMemOpClusterMutation` currently orders frame-index bases by
frame-index number, adjusted for the stack growth direction. Fixed frame
objects are different from ordinary stack objects: they carry explicit
offsets, and their creation order is not required to match address
order.
As a result, a target clustering hook can receive two fixed objects in
reverse address order. AArch64's `shouldClusterFI` expects the incoming
fixed-object offsets to be ordered and aborts with `Object offsets are
not ordered` in an assertions-enabled build.
When both operands refer to fixed frame objects, compare their
`MachineFrameInfo` object offsets first. The existing frame-index
comparison remains the fallback, so the ordering of ordinary stack
objects is unchanged.
Make the ordering between fixed and non-fixed frame-index bases
explicit: non-fixed bases precede fixed bases for downward-growing
stacks, while fixed bases precede non-fixed bases for upward-growing
stacks. This preserves the existing cross-category ordering without
relying on non-fixed object offsets before frame layout.
The regression deliberately creates two fixed objects in an order that
disagrees with their explicit offsets. It covers both the legacy and new
machine-scheduler pass forms.
## AI assistance
OpenAI Codex was used to assist with the investigation, patch
preparation, testing, and drafting this PR description.
Commit: a129f830b8727c51c087db8278035d2c6f08da25
https://github.com/llvm/llvm-project/commit/a129f830b8727c51c087db8278035d2c6f08da25
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Use BitVector for RegisterSet in AsmMatcherEmitter (NFC) (#222525)
This patch replaces std::set with BitVector for RegisterSet in
AsmMatcherEmitter.
Without this patch, RegisterSet is represented as
std::set<const Record *, LessRecordByID>. On targets with large
register files like AMDGPU (~3,000 registers), repeatedly computing set
intersections and subset checks using std::set nodes incurs
significant overhead.
This patch assigns each register record a dense bit index ordered by
LessRecordByID. This allows us to represent RegisterSet as a
BitVector, enabling fast bitwise operations for set intersections and
subset checks.
This reduces the wall-clock time of generating AMDGPUGenAsmMatcher.inc
from 39.53s to 31.32s (a 20.8% speedup) across 3 runs while producing
bit-for-bit identical output across all targets.
Assisted-by: Antigravity
Commit: ac8aca03372551f8a8c999e86e5cb6cbfae3e307
https://github.com/llvm/llvm-project/commit/ac8aca03372551f8a8c999e86e5cb6cbfae3e307
Author: Yousef <yousef.idris01 at bcmail.cuny.edu>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
Log Message:
-----------
[GlobalISel] Add KnownBits support for G_INSERT_SUBVECTOR (#215048)
## Summary
Add KnownBits support for `G_INSERT_SUBVECTOR` in GlobalISel value
tracking.
The implementation splits the demanded elements between the original
vector and inserted subvector, ignores overwritten source elements, and
intersects the KnownBits information from the contributing operands.
Part of #150515.
## Testing
- `llvm-lit
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir`
- `llvm-lit llvm/test/CodeGen/AArch64/GlobalISel/knownbits-*.mir`
- 40/40 passed
Commit: 8497b7a259bbc8239d7358dc7bf83eb04b363c76
https://github.com/llvm/llvm-project/commit/8497b7a259bbc8239d7358dc7bf83eb04b363c76
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
Log Message:
-----------
[AMDGPU] Support TFE D16 format buffer loads on gfx8/10/11/12 (#211465)
gfx90a has no hardware encoding for TFE D16 format buffer loads, so
reject the combination there with a diagnostic. Other targets
(gfx8/10/11/12) do have real encodings, so add codegen support for them
instead of rejecting unconditionally.
Commit: 89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
https://github.com/llvm/llvm-project/commit/89c4368a5dab1fe3bbd3fbc4b9717b56154ef64f
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
Log Message:
-----------
[VPlan] Don't create no-op casts in truncateToMinimalBitwidths. (#223271)
No-op casts get folded to the input operand, which caused applyFlags to
crash if that was not a cast. Fix by avoiding creating such trivial
casts in the first place.
Commit: 82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
https://github.com/llvm/llvm-project/commit/82a18cf0c030a1c82ad32f74f1cb8bf67adf1649
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
M clang/test/Driver/mingw.cpp
Log Message:
-----------
[Clang][MinGW] Link default-manifest.o if exists (#223084)
Some MinGW distributions provide a pre-compiled manifest xml to disable
the UAC escalation dialog.
Link automatically the manifest only if it exists when linking an
executable.
Do the same as Cygwin (#220875) and align with GCC.
Commit: 9bf40ce33523745e19328924593134e4510bfa5f
https://github.com/llvm/llvm-project/commit/9bf40ce33523745e19328924593134e4510bfa5f
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
Log Message:
-----------
[AMDGPU] Fix s_buffer_load crash for illegal result types (#215483)
i1, i4, v2i1, v3i16, v6i8, and i128 had no SBUFFER_LOAD selection
pattern and crashed
Load a legal i32/vNi32 carrier instead and narrow/bitcast down to the
requested type
Commit: cf530065be1fccbd9ac1d5ccc7d55d80681de41d
https://github.com/llvm/llvm-project/commit/cf530065be1fccbd9ac1d5ccc7d55d80681de41d
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
Log Message:
-----------
[lldb][Process/FreeBSD-Kernel-Core] Dereference stoppcbs based on target kernel version (#222977)
As of `__FreeBSD_version 1400089` stoppcbs is a pointer to the pcbs
array. Dereference stoppcbs on sufficiently new kernels.
Obtained-from:
https://cgit.freebsd.org/src/commit/?id=0f2bb40bc7ddee7ba329d9b344623e2a186b4046
Commit: 4b08871f7ffe6ad818147145f8b6103e6c9b2c95
https://github.com/llvm/llvm-project/commit/4b08871f7ffe6ad818147145f8b6103e6c9b2c95
Author: Ziqing Luo <ziqing_luo at apple.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
Log Message:
-----------
[SSAF][SourceEdit] Wire in 'clang-ssaf-src-edit-merge' and add multi-TU tests (#220372)
With 'clang-ssaf-src-edit-merge', we can test source edits over multiple
translation units: their Replacements are merged before apply. This
covers both clean merges and conflicts.
Commit: e476e76df9b17ace8d12f85616482718901d4854
https://github.com/llvm/llvm-project/commit/e476e76df9b17ace8d12f85616482718901d4854
Author: David Green <david.green at arm.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Log Message:
-----------
[AArch64] Make ImmInsnModel operands optional. NFC (#223280)
This helps make sure we do not use them incorrectly, and should allow
them to
be checked for values in the future.
Commit: e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
https://github.com/llvm/llvm-project/commit/e33c1e82dfa3b9f091d5ff8ba81bfb8f6b87134d
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
Log Message:
-----------
[VPlan] Add tests for narrowing users of a widened induction (NFC). (#223277)
Add additional narrowing tests for wide IV including pointer inductions
and FP inductions.
Commit: cc6d78e8eea21e0ddc5376b1700af00e33a77e17
https://github.com/llvm/llvm-project/commit/cc6d78e8eea21e0ddc5376b1700af00e33a77e17
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
Log Message:
-----------
[VPlan] Fold shifts by zero. (#223276)
Add trivial folds of shifts by zero. This allows us to match IR SCEV
behavior (which looks through trivial shifts), w/o explicitly handling
those in getSCEVExprForVPValue.
Commit: 0c4e1a6b8941babd458e803041abc4d5186361e8
https://github.com/llvm/llvm-project/commit/0c4e1a6b8941babd458e803041abc4d5186361e8
Author: Florian Hahn <flo at fhahn.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
Log Message:
-----------
[VPlan] Set the containing plan when creating blocks (NFC). (#223269)
Now that we funnel all VP block creation through VPlan helpers, make
sure the Plan field is set for each block. This means we can remove the
CFG walk to find a Plan's entry.
Also drop an assertion in VPSlotTracker::getOrCreateName: a block now
knows its plan as soon as it is created.
This has a very small positive compile-time impact.
Commit: 462535b1455c639bfb1875b71720d94586a5f650
https://github.com/llvm/llvm-project/commit/462535b1455c639bfb1875b71720d94586a5f650
Author: Eric Ross <zerico2005 at gmail.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
Log Message:
-----------
[InstCombine][NFC] Move bitcast from float tests into their own file (#223196)
Commit: c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
https://github.com/llvm/llvm-project/commit/c577c6c3f88baddcb2f5368c5cf7f2ca6137b5be
Author: Minsoo Choo <minsoochoo0122 at proton.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
Log Message:
-----------
[lldb] Test undefined return addresses in signal frames (#223046)
Signal-frame CFI can explicitly mark its return-address register
undefined to represent a terminal synthetic context. This is useful for
contexts such as newly created FreeBSD kernel threads that do not have
an interrupted caller.
Verify that LLDB keeps the signal frame in the backtrace and terminates
the unwind without creating a caller.
Assisted-by: GPT
Commit: bce20f538caf18619a825c689883f652471091d3
https://github.com/llvm/llvm-project/commit/bce20f538caf18619a825c689883f652471091d3
Author: Zeyi Xu <zeyi2 at nekoarch.cc>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Add experimental Smidctrl, Ssidctrl, Smnip, and Ssnip support (#218108)
Add experimental MC support for Smidctrl, Ssidctrl, Smnip, and Ssnip
extensions.
This completes MC support for the ACLIC v0.20 extensions.
Commit: 63d2e62707e8ec6c070a3b258ea81f320920525c
https://github.com/llvm/llvm-project/commit/63d2e62707e8ec6c070a3b258ea81f320920525c
Author: Kazu Hirata <kazu at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Lex/PPMacroExpansion.cpp
Log Message:
-----------
[clang][Lex] Unique ModuleMacros with a UniquingSet (NFC) (#223270)
This patch migrates ModuleMacros in Preprocessor from llvm::FoldingSet
to llvm::UniquingSet.
ModuleMacro keys on a pair of Module * and const IdentifierInfo *.
Switching to UniquingSet allows us to look up macros with a typed key,
eliminating FoldingSetNodeID serialization at lookup sites and removing
ModuleMacro::Profile.
Assisted-by: Antigravity
Commit: 6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
https://github.com/llvm/llvm-project/commit/6d7e7fbafd8d010a3a4146b24e8cca2c8b7dc831
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
A llvm/test/Transforms/InstCombine/uitofp.ll
Log Message:
-----------
[InstCombine] Fold uitofp of masked truncations (#222592)
Fold an unsigned integer-to-floating-point conversion of a masked
truncation by widening the mask and eliminating the truncation:
`uitofp((trunc X) & C)` → `uitofp(X & zext(C))`
Apply the fold when the intermediate instructions have one use and
widening the integer operation is desirable.
This reduces the instruction count on both AMDGPU and NVPTX.
AMDGPU example: https://godbolt.org/z/rTYhM61ce
NVPTX example: https://godbolt.org/z/fWhsrne19
Commit: 9e70d8f070ba046b8e09388fa84b3a65eb2073e3
https://github.com/llvm/llvm-project/commit/9e70d8f070ba046b8e09388fa84b3a65eb2073e3
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/blocks.cpp
Log Message:
-----------
[Clang][NFC] add additional test coverage for default argument parsing errors (#222556)
Fixes #115280
Commit: 291b60a5bc416c8dd81731954680ebd41f599ab5
https://github.com/llvm/llvm-project/commit/291b60a5bc416c8dd81731954680ebd41f599ab5
Author: wanglei <wanglei at loongson.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
Log Message:
-----------
[LoongArch][test] Test 1- and 2-byte subtraction relocations. NFC (#222825)
Add MC tests for 1- and 2-byte subtraction relocations enabled by
#211754.
Commit: dbac421efa19a5901f2511958040e18e8188b112
https://github.com/llvm/llvm-project/commit/dbac421efa19a5901f2511958040e18e8188b112
Author: lntue <lntue at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
A libc/utils/mathtools/wc_to_bin.py
Log Message:
-----------
[libc][math] Fix fast path with small inputs for double precision sin/cos. (#221012)
https://github.com/llvm/llvm-project/pull/201748 added a fast branch for
small inputs to double precision sin/cos,
but the Ziv error bounds were too tight.
Fixes in this PR:
- Updating the Ziv error bounds to accommodate rounding errors.
- Copy binary64 sin/cos hard-to-round cases from the CORE-MATH project.
- Add python tool to convert textual hard to round cases to binary
files, and add those binary files.
- Add hard-to-round tests for double precision sin/cos in the exhaustive
test folder.
Fixes https://github.com/llvm/llvm-project/issues/220934.
Assisted-by: Gemini is used to generate the worst-case text-to-binary
tool.
Commit: a92db5feb9eb78ae7bf37d969391d9f94f181afb
https://github.com/llvm/llvm-project/commit/a92db5feb9eb78ae7bf37d969391d9f94f181afb
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen] Declare <TargetName>RegClassByHwModeTables in MC header (#223292)
When a target uses RegClassByHwMode in CompressPat, the generated
functions reference <TargetName>RegClassByHwModeTables.
Declare it under GET_INSTRINFO_MC_HELPER_DECLS (<Target>MCTargetDesc.h)
so it is visible to MC-layer users such as RISCVBaseInfo.cpp.
Fixes: 700d1f029d00 ("[TableGen] Support RegClassByHwMode in
CompressPat")
Commit: 10b2437880e6d3365f973174f6bce8e07f54f549
https://github.com/llvm/llvm-project/commit/10b2437880e6d3365f973174f6bce8e07f54f549
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/test/unit/CMakeLists.txt
Log Message:
-----------
[orc-rt] Build RTTICrossDylibTestLib with ORC_RT_COMPILE_FLAGS (#223144)
Without ORC_RT_COMPILE_FLAGS, the test library builds with C++ RTTI on
by default. This leads to link errors when the ORC runtime is built with
C++ RTTI turned off.
Commit: 72d03332c0cd0579ad09d00f9086c7cb6035fce0
https://github.com/llvm/llvm-project/commit/72d03332c0cd0579ad09d00f9086c7cb6035fce0
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M orc-rt/CMakeLists.txt
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/tools/ogre/CMakeLists.txt
Log Message:
-----------
[orc-rt] Add ORC_RT_BEDROCK_LIBRARY_TYPE (STATIC/SHARED) (#223288)
Add CMake options to build bedrock as either a static or shared library.
Default is static.
This is CMake infrastructure only. Shared library builds aren't actually
useable yet: bedrock doesn't export its C++ API, and its C API is
insufficient to do anything interesting. Tools and test code are updated
to link against the -object libraries directly, since they use the
(unexported) C++ API.
Commit: 5fa83314adddbd13e4347ec8fc22e235d5710978
https://github.com/llvm/llvm-project/commit/5fa83314adddbd13e4347ec8fc22e235d5710978
Author: Daniel Cederman <cederman at gaisler.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/test/Driver/sparc-as.c
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M llvm/lib/Target/Sparc/Sparc.td
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
Log Message:
-----------
[SPARC] Add LEON5 processor (#222912)
Same target exists in GCC.
Commit: f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
https://github.com/llvm/llvm-project/commit/f0f76dbbc4c79e7f05e9ba96e7e0171e0444362e
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve EHFrame registration symbols via lookupAndApply (#223304)
EHFrameRegistrationPlugin::Create resolved its register/deregister
alloc-action addresses with EPC.getBootstrapSymbols. For consistency,
switch to lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
https://github.com/llvm/llvm-project/commit/bdf664cf900fcf7aa0d30b730c7e0b752bcd3c89
Author: Pavel Labath <pavel at labath.sk>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
Log Message:
-----------
[libc] Implement pthread_attr_[gs]etschedparam (#222991)
This patch implements pthread_attr_setschedparam and
pthread_attr_getschedparam.
Like the schedpolicy patch, this commit only operates on the
pthread_attr_t object and does not attempt to install scheduling
parameters when creating a new thread.
I also don't attempt to validate the priority value here. The valid
priority range depends on the scheduling policy (which may not even be
set yet or could change later), and we can let the kernel validate the
parameters when creating the thread or setting scheduler settings.
While in there:
- update the file headers to the modern llvm format
- use proxy headers instead of direct pthread.h inclusion
Assisted-by: Gemini
Commit: aeefb10b01fb7cf11a1917230f10b663d5ec109b
https://github.com/llvm/llvm-project/commit/aeefb10b01fb7cf11a1917230f10b663d5ec109b
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M llvm/lib/IR/Metadata.cpp
M llvm/unittests/IR/MetadataTest.cpp
Log Message:
-----------
[IR] Simplify ValueAsMetadata::handleRAUW. NFC (#223301)
Metadata refers to a Value through its unique ValueAsMetadata wrapper.
When a Value is RAUW'd, handleRAUW reuses the old value's wrapper for
the new value if the new value has none yet; otherwise it moves the uses
to the new value's wrapper, with special cases for a local becoming a
constant, a constant becoming a local, and a value moving to another
function.
Always move the uses (or drop them in the last two cases) and delete the
old wrapper, so that a ValueAsMetadata wraps the same value for its
whole life.
Instruction counts for SLPVectorizer.cpp and X86ISelLowering.cpp at -O2
-g are unchanged (-0.04%, -0.01%).
Aided by Opus 5
Commit: 9a7c7f2b3a40c32e53dcaf2637087851d694cc60
https://github.com/llvm/llvm-project/commit/9a7c7f2b3a40c32e53dcaf2637087851d694cc60
Author: 陈子昂 <2802328816 at qq.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/lib/Headers/riscv_packed_simd.h
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
Log Message:
-----------
[Clang][RISCV] Add packed widening add accumulate intrinsics (#221622)
Add Clang header intrinsics for the RISC-V P-extension packed widening
add accumulate operations:
- __riscv_pwadda_i16x4
- __riscv_pwadda_i32x2
- __riscv_pwaddau_u16x4
- __riscv_pwaddau_u32x2
The header wrappers use generic LLVM IR. RV32 selects the direct
`pwadda.*` / `pwaddau.*` instructions. RV64 lowers the generic IR to the
decomposition specified by the P-extension intrinsic spec, including
`zip16p + pli.h + pm2adda.h/pm2addau.h` for the halfword forms.
Commit: f8c52ad174682e05e222c1456a9f3ad177cf464b
https://github.com/llvm/llvm-project/commit/f8c52ad174682e05e222c1456a9f3ad177cf464b
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
Log Message:
-----------
[TargetInstrInfo] Enable instruction size verification by default (#221687)
Enable verification for instruction sizes by default. When emitting
machine code, this checks that the reported instruction size is not
smaller than the actual instruction size. Not under-reporting
instruction sizes is critical for any target that does branch relaxation
(or similar) on MIR.
The default allows over-estimating the size. Targets can opt-in to
precise instruction sizes if they want.
Exclude two instructions on ARM, which report incorrect sizes, but
fixing those sizes breaks the constant islands pass for some reason.
Commit: a9253c774aae777f5c0135d063a3a044612ae48f
https://github.com/llvm/llvm-project/commit/a9253c774aae777f5c0135d063a3a044612ae48f
Author: Fangrui Song <i at maskray.me>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Support/Allocator.h
M llvm/unittests/Support/AllocatorTest.cpp
Log Message:
-----------
[Allocator] Don't overestimate alignment for operator new (#223300)
On many platforms with alignof(max_align_t)=16, when sizeof(T) == 24,
The placement new overestimates the alignment to 16:
`std::min(llvm::bit_ceil(Size), alignof(std::max_align_t)) = min(32, 16) = 16`.
We can use a better estimate: `min(countr_zero(Size),
alignof(max_align_t))`, which is hand-optimized to the form in the code.
Commit: 93d89033cddd47fc512dbe14917fd62d302f4f1d
https://github.com/llvm/llvm-project/commit/93d89033cddd47fc512dbe14917fd62d302f4f1d
Author: ʟᴜɴᴇx <thisissamir04 at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
Log Message:
-----------
[GlobalOpt] Fix assertion failure with CallInst user (#221955)
By removing the unnecessary assertion, which can get
out of sync with GlobalStatus.
Fixes: #221589
Commit: b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
https://github.com/llvm/llvm-project/commit/b357d1a4a3573f202b8a1a1cb6ac56c18b7b6faf
Author: Kane Wang <wangqiang1 at kylinos.cn>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
Log Message:
-----------
[RISCV] Lower f16 to i64 fp_to_[su]int via i32 on RV32 (#222829)
i64 is not a legal type on RV32, so f16 to i64 conversions used to be expanded to a __fixhfdi/__fixunshfdi libcall, which compiler-rt does not provide. f16 is the only FP type whose finite values always fit in an i32 after truncation towards zero, so custom expand them to an i32 conversion plus an extension instead; out of range values and NaN are poison, so the fcvt clamping is acceptable. With only Zfhmin/Zhinxmin the i32 conversion promotes f16 to f32, and both imply F/Zfinx so f32 is always legal. Other FP source types keep using the libcall.
Commit: bc985edd777ff8efab9f161444d4a9ff00c25574
https://github.com/llvm/llvm-project/commit/bc985edd777ff8efab9f161444d4a9ff00c25574
Author: Chris Copeland <chris at chrisnc.net>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
Log Message:
-----------
[CodeGen][test] use -float-abi=soft in 2009-03-29-SoftFloatVectorExtract.ll (#223122)
In #221434, using +soft-float with a hard-float ABI is now an error on
ARM.
This test does not specify a target triple, so it will fail when the
default triple is hard-float ARM. Explicitly specify -float-abi=soft
so the test will continue to use the host triple but force the
soft-float ABI
where applicable.
Commit: badec9b619f3f7d6090d5ae84a60adf416139a15
https://github.com/llvm/llvm-project/commit/badec9b619f3f7d6090d5ae84a60adf416139a15
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
Log Message:
-----------
[ORC] Resolve unwind-info alloc-actions via lookupAndApply (#223312)
UnwindInfoRegistrationPlugin::Create resolved its register- /
deregister-section alloc-actions with EPC.getBootstrapSymbols. For
consistency, switch to lookupAndApply/recordAddr on the bootstrap
JITDylib instead.
Commit: 109f29a7c0a3910a768fa7dd490ac8f51708b858
https://github.com/llvm/llvm-project/commit/109f29a7c0a3910a768fa7dd490ac8f51708b858
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
Log Message:
-----------
[SPIR-V] Print group operation of uniform group instructions as enum (#222540)
Opcodes typed `$groupOp` as i32imm, so the printer emitted 0 instead of
"Reduce" and spirv-as rejected the output
Commit: 20b53106931742d2e5e64132f06994980fe94d7d
https://github.com/llvm/llvm-project/commit/20b53106931742d2e5e64132f06994980fe94d7d
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
Log Message:
-----------
[OMPIRBuilder] Avoid use of ConstantExpr::getSizeOf() (#223323)
This will not be supported in ptradd representation. Directly
create a constant with the type size instead.
Commit: a872c86cf07ad71cc4e05a98c5169a27d600d16c
https://github.com/llvm/llvm-project/commit/a872c86cf07ad71cc4e05a98c5169a27d600d16c
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/Parser/cxx-extra-semi.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for extra semicolons in parameter lists (#222572)
Fixes #112377
Commit: 61519bf9fa07fed0546c2985a6884b60ca71ca2b
https://github.com/llvm/llvm-project/commit/61519bf9fa07fed0546c2985a6884b60ca71ca2b
Author: Oleksandr Tarasiuk <oleksandr.tarasiuk at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M clang/test/SemaCXX/enum.cpp
Log Message:
-----------
[Clang][NFC] add test coverage for parameter declaration errors (#222562)
Fixes #113465
Commit: ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
https://github.com/llvm/llvm-project/commit/ce4f831c9e951be16e80ac83465eb5f6d4dfe3c7
Author: Nikita Popov <npopov at redhat.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
Log Message:
-----------
[CGP] Clear poison generating flags when freezing icmp of constants (#223326)
Followup to https://github.com/llvm/llvm-project/pull/222314. That
PR only dropped the flags for the case where a new freeze instruction
was created, but of course we also need to do this if both operands
are constant and the freeze is dropped entirely.
Commit: fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
https://github.com/llvm/llvm-project/commit/fff8f393a9aa7c6199a3efa4e2d8f439f8c0f06e
Author: Sergei Druzhkov <serzhdruzhok at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
Log Message:
-----------
[lldb-dap] Fix logpoint to breakpoint conversion (#222906)
When user sets logpoint and after that removes `logMessage`, which
implicitly converts it to usual breakpoint, breakpoint still has
`BreakpointHitCallback`, which leads to missed stops.
Commit: 0f89e7a6027b9fc93032aa4d154028045ed9018f
https://github.com/llvm/llvm-project/commit/0f89e7a6027b9fc93032aa4d154028045ed9018f
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
Log Message:
-----------
[Flang][OpenMP] Show warning for -fdoconcurrent-to-openmp in SIMD only mode (#220943)
The OpenMP feature is considered enabled if either `-fopenmp` or
`-fopenmp-simd` have been passed. However, full OpenMP support is
required in order for the `-fdoconcurrent-to-openmp` option to take
effect.
A warning message that wasn't shown when SIMD-only OpenMP support was
enabled is fixed.
Commit: 860d945db8787845349096521157eabf09be81cb
https://github.com/llvm/llvm-project/commit/860d945db8787845349096521157eabf09be81cb
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223328)
Commit: 6e071ab17caa0058a83cdd1580026259fdaecb4f
https://github.com/llvm/llvm-project/commit/6e071ab17caa0058a83cdd1580026259fdaecb4f
Author: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
Log Message:
-----------
[RISCV] Rewrite ADD to SUB to reuse a materialized negated constant (#221027)
When an ADD needs a large constant whose negation is already
present in the DAG, rewrite (add X, C) into (sub X, -C) so both
share one materialization of -C instead of building it twice.
selectNegImm already does a related rewrite, but only when -C is
strictly cheaper than C and during instruction selection, where the
sibling constant may already have been selected into instructions.
Do it in PreprocessISelDAG instead, before selection, while both are
still ConstantSDNodes that getConstant can unique together. The
rewrite only fires when -C is no more expensive than C and a node
holding -C already exists, so it never adds a materialization.
Fixes https://github.com/llvm/llvm-project/issues/220555
Assisted-by: TRAE CLI (Opus 4.8)
Commit: 6d4ad3383e9b235c0f07a82be141bb57278650af
https://github.com/llvm/llvm-project/commit/6d4ad3383e9b235c0f07a82be141bb57278650af
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
Log Message:
-----------
[AMDGPU] Model waterfall loop EXEC update as a terminator (#219519)
Defining a register normally disqualifies an instruction from being a
terminator, so mark it unspillable instead
Skip this at -O0, since RegAllocFast ignores that and spills right after
the def
Commit: 6b5912a441c2236859a7cfe1e5ce3e02a547b588
https://github.com/llvm/llvm-project/commit/6b5912a441c2236859a7cfe1e5ce3e02a547b588
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
Revert "[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC)" (#223341)
Reverts llvm/llvm-project#223328 (looking into buildbot error, e.g.
https://github.com/llvm/llvm-project/pull/223328#issuecomment-5661919431)
Commit: 1042f3cd8299003876babb567d78540d30c019aa
https://github.com/llvm/llvm-project/commit/1042f3cd8299003876babb567d78540d30c019aa
Author: Mattéo Rizza Murgier <matteo.rizza-murgier at sipearl.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
Log Message:
-----------
[mlir][ComplexToStandard] Use negf/subf instead of multiplying by -1 (#222877)
Commit: e8d2def7e7ed18f22a493b72435468225c1047ba
https://github.com/llvm/llvm-project/commit/e8d2def7e7ed18f22a493b72435468225c1047ba
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
Log Message:
-----------
[libc++] Provide aligned allocation function iff the compiler claims support (#219199)
There isn't much of a point to providing declarations for aligned
allocation functions but not allowing the compiler to use them. So
either aligned allocations should be allowed to be used via
`-faligned-allocation` or not provided at all.
Commit: 1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
https://github.com/llvm/llvm-project/commit/1a2ee398b1fb7c36317a5ad6ae4f92b9f4097c69
Author: Sergio Afonso <safonsof at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M flang/docs/OpenMP-declare-target.md
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
Log Message:
-----------
[MLIR][OpenMP] DeclareTargetInterface and DeclareTargetAttr cleanup (#217295)
The changes introduced by this patch are intended to avoid triggering
multiple by name lookups to the "omp.declare_target" attribute every
time any data from the `DeclareTargetInterface` is queried, remove the
need for keeping multiple default values for the same data, clean up the
assembly format and generally improve the usage of the interface.
List of changes:
- `DeclareTargetInterface` only provides `setDeclareTarget` and
`getDeclareTarget` methods to handle the "omp.declare_target" attribute,
maintaining a single canonical way of accessing it.
- `DeclareTargetAttr` provides direct access to the capture clause and
device type enums, rather than wrapping them into an `Attribute`. These
are now mandatory as well. Both changes together make accessing them
more straightforward and simplify the attribute representation.
Commit: 37fe7024f2944f71d58b8608d209bda3254fa43a
https://github.com/llvm/llvm-project/commit/37fe7024f2944f71d58b8608d209bda3254fa43a
Author: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/test/CodeGen/SPIRV/read_image.ll
Log Message:
-----------
[SPIR-V] Add missing read_imageh builtin mapping (#222549)
Commit: c4c4bbaf14303d3e5399487c16ec6a0ff4754386
https://github.com/llvm/llvm-project/commit/c4c4bbaf14303d3e5399487c16ec6a0ff4754386
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__charconv/to_chars_integral.h
Log Message:
-----------
[libc++][NFC] Remove some unused functions from to_chars_integral.h (#223130)
Commit: d873afedebd0726700ba7f42a5d6e54dba288557
https://github.com/llvm/llvm-project/commit/d873afedebd0726700ba7f42a5d6e54dba288557
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
Log Message:
-----------
[libc++] Optimize string copy construction (#222021)
We know that the string size provided to `__init_copy_ctor_external` is
less than or equal to `max_size()`, so we don't need to do that check
again. Removing that check allows the compiler to ShrinkWrap the small
size path and also removes some unnecessary work in the allocating path.
Commit: 1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
https://github.com/llvm/llvm-project/commit/1a31493a5cc8c05db3473ffa35f6c1d1289fcd22
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
Log Message:
-----------
[libc++] Move _LIBCPP_HAS_COND_CLOCKWAIT into condition_variable.h (#222904)
`_LIBCPP_HAS_COND_CLOCKWAIT` is only used inside
`<__condition_variable/condition_variable.h>`, so we might as well move
it there.
Commit: 59f4a867528eeb8cd8823afb0ee4e5c4d2843741
https://github.com/llvm/llvm-project/commit/59f4a867528eeb8cd8823afb0ee4e5c4d2843741
Author: Akash Manna <akash.manna.mymail at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
Log Message:
-----------
[X86] Fix `"Cannot select"` for `bf16` vector selects on a scalar condition under `AVX10.2` (#222854)
Fixes #222673
A `select i1 %c, <8 x bfloat> %a, <8 x bfloat> %b` failed instruction
selection with `+avx10.2-512` on a `v8bf16 X86ISD::CMOV`. Selects on a
scalar condition are lowered to the `CMOV_VR*` pseudos and expanded to a
branch, but those pseudos only have patterns for integer and f16
vectors. Before #101603 bf16 vectors were treated as "soft" everywhere,
so `LowerSELECT` bitcast them to `v8i16` first and never produced a bf16
CMOV. That PR made bf16 non-soft under AVX10.2 to enable native
arithmetic, which silently removed the only bf16-aware path in
`LowerSELECT` without adding a replacement. `v16bf16` and `v32bf16` hit
the same thing.
`LowerSELECT` now takes the integer-bitcast path for every bf16 vector,
using the existing `isBF16orSoftF16` helper, so the select is lowered
exactly as it is on every other bf16 target and as `v8f16` is on FP16
targets. Scalar `bf16` is soft-promoted to `f32` before lowering, so it
is unaffected. Added `pseudo_cmov_lower-bf16.ll` alongside the f16
sibling, covering the reproducer plus `v8/v16/v32bf16` on both
`+avx512bf16,+avx512vl` and `+avx10.2-512`.
Commit: 1b97c0daeb67ef7895034a1702ccc04562283ecc
https://github.com/llvm/llvm-project/commit/1b97c0daeb67ef7895034a1702ccc04562283ecc
Author: Lang Hames <lhames at gmail.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
Log Message:
-----------
[ORC] Resolve JITLoaderGDB alloc actions via lookupAndApply (#223325)
ELFDebugObjectPlugin resolved its RegisterJITLoaderGDB alloc-action
address with EPC.getBootstrapSymbols. For consistency, switch to
lookupAndApply/recordAddr on the bootstrap JITDylib instead.
Commit: eb6d5dd90eb596f8b82632d03d2ad8517df2d764
https://github.com/llvm/llvm-project/commit/eb6d5dd90eb596f8b82632d03d2ad8517df2d764
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
Log Message:
-----------
[IVDescriptors] Address MonotonicDescriptor post-commit comments (NFC) (#223346)
Commit: f477555c212d2eddd65f5a791b19efe075e2c708
https://github.com/llvm/llvm-project/commit/f477555c212d2eddd65f5a791b19efe075e2c708
Author: Yao Qi <yao_qi at apple.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M lldb/include/lldb/Target/Memory.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Target/Memory.cpp
M lldb/unittests/Target/MemoryTest.cpp
Log Message:
-----------
[lldb] Memory cache: no overlap and read across cache entries (#222688)
The memory cache keeps two collections of cached bytes, L1 and L2, which
are named confusingly. L2 holds cache lines at aligned addresses, but
each line size is less than or equal to the fixed line size. L1 holds
pieces from arbitrary addresses with arbitrary lengths. This caused two
problems:
1. A lookup had to find every byte it wanted inside a *single*
entry. A range that spanned two adjacent entries missed even when the
two collections together already held every byte of it. The lookup
rejected such a read rather than take part of it from each entry.
2. The pieces could also overlap each other, which made the lookup
incomplete as well as ambiguous. It examined only the piece starting at
or below the address, so a short piece hid a longer one that covered the
whole read. The read missed with the bytes resident.
This change fixes these problems by introducing these properties to the
cache:
- At most one collection holds any given address.
- The line collection holds only whole, aligned lines (`LineCache`).
- The piece collection holds only fragments smaller than a line, and
they never overlap each other (`ChunkCache`).
- A read takes what it needs from consecutive entries in turn until a
miss (`ReadFromCaches`).
- `AddCacheData` (renamed from `AddL1CacheData`) splits incoming bytes
at line boundaries and drops bytes already held, so callers no longer
pick the cache tier.
Disjoint entries make the cache simple to reason about:
- A read no longer depends on which copy of an address is found first,
because there is only one.
- Probing one candidate is now complete. Since entries cannot
overlap, the entry starting at or below an address is the only one
that can hold it. No byte is stored twice.
- Invalidating an address touches one entry, with no second copy
elsewhere to find and drop.
- Callers of the cache need no knowledge of cache internals.
`ReadRanges` also uses `ReadFromCaches`. Previously, each requested
range had to fit entirely within a single cache entry. Ranges can now
be served across multiple entries and line boundaries. For example,
`Process::ReadCStringsFromMemory` reads strings in 256-byte windows.
Because strings start at arbitrary offsets, these windows frequently
span
two adjacent cache lines. Under the old lookup, such a window missed in
`ReadRanges` even when both lines were resident. It now hits from cache
across the line boundary.
`Flush` now drops all cached entries that intersect the range instead of
erasing only the entry matching the start address. It uses saturating
addition to prevent address wraparound. Its runtime is bounded by the
number of cached entries rather than the range size.
`GrowReadRange` isolates the read-ahead policy from `Read`. It aligns
the read address down to the line base so fetches land in `LineCache` as
whole lines. It caps read-ahead to two lines, skips the last line if
already resident, and clips the read at invalid ranges.
Assited-by: claude
Commit: 9271a73e189508743b4b2ad4393f12d5a8132fa9
https://github.com/llvm/llvm-project/commit/9271a73e189508743b4b2ad4393f12d5a8132fa9
Author: Igor Wodiany <igor.wodiany at amd.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
Log Message:
-----------
[AMDGPU] Mark `SI_WATERFALL_LOOP` as divergent in `hasDivergentBranch` (#218969)
When a vector instruction takes an SGPR source operand, sinking it out
of a loop with divergent exit would cause the vector instruction to only
get the value from the last iteration in the SGPR. However, in a
divergent loop the value of the SGPR operand may vary across iterations,
so the instruction cannot be sink out of the loop as only using the last
value is incorrect. Before this change `SI_LOOP` was marked as divergent
but `SI_WATERFALL_LOOP` was not, allowing such incorrect sinking for
waterfall loops.
Assisted-by: Claude Code
Commit: 611db63efe0456cca4745930977fcdfe64cc25a9
https://github.com/llvm/llvm-project/commit/611db63efe0456cca4745930977fcdfe64cc25a9
Author: MarkVeerasingam <122292447+MarkVeerasingam at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
Log Message:
-----------
[dfsan] Fix big-endian origin mask (#223247)
Fix the mask used when loading wide shadows on big-endian targets.
The previous expression used a 32-bit integer for the shift, producing
an incorrect zero mask for 64-bit wide shadows. Changed the expression
to use 1ULL so that a 64-bit mask is constructed correctly. The
resulting mask keeps the upper 32 bits and clears the lower 32 bits.
Previously, the big-endian path generated:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, 0
```
With this change, it generates:
```ll
%10 = load i64, ptr %6, align 1
%11 = and i64 %10, -4294967296
```
Added a SystemZ big-endian regression test.
cc: @uweigand @anoopkg6
Commit: c46d8f243727b467d8803c4b2430534b348daed1
https://github.com/llvm/llvm-project/commit/c46d8f243727b467d8803c4b2430534b348daed1
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
Log Message:
-----------
[SLP]Booleanize logical and/or nodes in the wide leaf type
i1 and/or tree nodes with booleanized wide leaves (one-use truncs of
wide values, zero-tests of values from [0, 1]) are registered in MinBWs
and emitted in the wide type; bit 0 of the result is the final value.
Reviewers: bababuck
Pull Request: https://github.com/llvm/llvm-project/pull/223250
Commit: 27c38b80934067471d7aa7477f894bcb8461a4f3
https://github.com/llvm/llvm-project/commit/27c38b80934067471d7aa7477f894bcb8461a4f3
Author: Harrison Hao <57025411+harrisonGPU at users.noreply.github.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
[AMDGPU] Select trunc(srl x, 16) as hi16 subregister on true16 (#221960)
Use the high 16 bits of a VGPR directly instead of shifting.
Before:
```
v_lshrrev_b32_e32 v1, 16, v0
v_add_f16_e32 v0.l, v0.l, v1.l
```
After:
```
v_add_f16_e32 v0.l, v0.l, v0.h
```
Example: https://godbolt.org/z/c7bE46hzb
Commit: 76d188487b121029f57a3512e3afb28b53bb4ea6
https://github.com/llvm/llvm-project/commit/76d188487b121029f57a3512e3afb28b53bb4ea6
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2026-09-14 (Mon, 14 Sep 2026)
Changed paths:
M bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
M clang/include/clang/Basic/AArch64CodeGenUtils.h
M clang/include/clang/Lex/MacroInfo.h
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Basic/Targets/Sparc.cpp
M clang/lib/Basic/Targets/Sparc.h
M clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/Targets/SPIR.cpp
M clang/lib/Driver/ToolChains/Arch/Sparc.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Headers/riscv_packed_simd.h
M clang/lib/Lex/PPMacroExpansion.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-conflict-edits-merge.cpp
A clang/test/Analysis/Scalable/source-edit-generation/multi-tu-edits-merge.cpp
M clang/test/CodeGen/AArch64/neon-intrinsics.c
M clang/test/CodeGen/AArch64/neon/intrinsics.c
M clang/test/CodeGen/RISCV/rvp-intrinsics.c
A clang/test/CodeGen/thread-model.c
M clang/test/CodeGenHIP/amdgcnspirv-uses-amdgpu-abi.cpp
A clang/test/Driver/Inputs/mingw_msys2_tree/msys64/mingw32/lib/default-manifest.o
M clang/test/Driver/mingw.cpp
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Driver/sparc-as.c
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Misc/target-invalid-cpu-note/sparc.c
M clang/test/Parser/cxx-extra-semi.cpp
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/SemaCXX/blocks.cpp
M clang/test/SemaCXX/enum.cpp
M cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
M flang/docs/OpenMP-declare-target.md
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/OpenMP/OpenMP.cpp
M flang/lib/Optimizer/OpenMP/AutomapToTargetData.cpp
M flang/lib/Optimizer/OpenMP/UnimplementedDeviceCheck.cpp
M flang/test/Driver/do_concurrent_to_omp_cli.f90
M flang/test/Integration/OpenMP/declare-target-funcs.f90
M flang/test/Integration/OpenMP/declare-target-named-main-interface.f90
M flang/test/Lower/OpenMP/declare-target-multiple-entry.f90
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-types/CMakeLists.txt
M libc/include/llvm-libc-types/pthread_attr_t.h
M libc/src/__support/math/cos.h
M libc/src/__support/math/sin.h
M libc/src/pthread/CMakeLists.txt
M libc/src/pthread/pthread_attr_getschedparam.cpp
M libc/src/pthread/pthread_attr_getschedparam.h
M libc/src/pthread/pthread_attr_init.cpp
M libc/src/pthread/pthread_attr_setschedparam.cpp
M libc/src/pthread/pthread_attr_setschedparam.h
M libc/test/src/math/exhaustive/CMakeLists.txt
A libc/test/src/math/exhaustive/cos.bin
A libc/test/src/math/exhaustive/cos.wc
A libc/test/src/math/exhaustive/cos_test.cpp
M libc/test/src/math/exhaustive/exhaustive_test.h
M libc/test/src/math/exhaustive/exhaustive_test_static_rounding.h
A libc/test/src/math/exhaustive/sin.bin
A libc/test/src/math/exhaustive/sin.wc
A libc/test/src/math/exhaustive/sin_test.cpp
A libc/test/src/math/exhaustive/worst_case_test.h
M libc/test/src/mathvec/exhaustive/exhaustive_test.h
M libc/test/src/pthread/CMakeLists.txt
M libc/test/src/pthread/pthread_attr_test.cpp
A libc/utils/mathtools/wc_to_bin.py
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
M libcxx/include/__charconv/to_chars_integral.h
M libcxx/include/__condition_variable/condition_variable.h
M libcxx/include/__config
M libcxx/include/__new/align_val_t.h
M libcxx/include/__new/global_new_delete.h
A libcxx/include/__utility/assume.h
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/src/include/aligned_alloc.h
M libcxx/src/support/new.ipp
M libcxx/test/libcxx/assertions/single_expression.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/new.size_align_nothrow.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align.except.pass.cpp
M libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/new.size_align_nothrow.except.pass.cpp
M libcxx/test/support/test_macros.h
M libcxxabi/src/fallback_malloc.cpp
M lldb/include/lldb/Target/Memory.h
M lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ProcessFreeBSDKernelCore.cpp
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Target/Memory.cpp
M lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
A lldb/test/Shell/Unwind/Inputs/signal-frame-undefined-ra.s
A lldb/test/Shell/Unwind/signal-frame-undefined-ra.test
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.cpp
M lldb/tools/lldb-dap/Protocol/ProtocolTypes.h
M lldb/tools/lldb-dap/SourceBreakpoint.cpp
M lldb/unittests/DAP/ProtocolTypesTest.cpp
M lldb/unittests/Target/MemoryTest.cpp
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/Analysis/IVDescriptors.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/include/llvm/Support/Allocator.h
M llvm/lib/Analysis/IVDescriptors.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/ExecutionEngine/Orc/Debugging/ELFDebugObjectPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/EHFrameRegistrationPlugin.cpp
M llvm/lib/ExecutionEngine/Orc/UnwindInfoRegistrationPlugin.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/Constants.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
M llvm/lib/Target/AArch64/AArch64ExpandImm.h
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
M llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsInstrInfo.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoP.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/SPIRV/SPIRVBuiltins.td
M llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombineInternal.h
M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer/SLPCostAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanPatternMatch.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/knownbits-insert-subvector.mir
M llvm/test/CodeGen/AArch64/cluster-frame-index.mir
A llvm/test/CodeGen/AArch64/coalescer-empty-subrange-early-lis.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.16bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.48bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-bf16-gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/bf16-math.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/bitcast_vector_bigint.ll
M llvm/test/CodeGen/AMDGPU/bitreverse.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll
M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps_nnan.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll
A llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
M llvm/test/CodeGen/AMDGPU/extract-subvector-16bit.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
M llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
M llvm/test/CodeGen/AMDGPU/fabs.f16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
M llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.bf16.ll
M llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
M llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
M llvm/test/CodeGen/AMDGPU/fmax_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
M llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
M llvm/test/CodeGen/AMDGPU/fmin_legacy.f16.ll
M llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll
M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/AMDGPU/fpow.ll
M llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
M llvm/test/CodeGen/AMDGPU/fract-match.ll
M llvm/test/CodeGen/AMDGPU/frexp-inf-nan-combine.ll
M llvm/test/CodeGen/AMDGPU/fshr.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
M llvm/test/CodeGen/AMDGPU/i1-to-bf16.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll
M llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bvh8_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dual_intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2bf16.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.illegal-types.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sched.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_nortn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd_rtn.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f32.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.format.i8.xfail.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.tfe.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
M llvm/test/CodeGen/AMDGPU/llvm.log.ll
M llvm/test/CodeGen/AMDGPU/llvm.log10.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.log2.ll
M llvm/test/CodeGen/AMDGPU/llvm.maximum.f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.minimum.f16.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-flat.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-global.ll
M llvm/test/CodeGen/AMDGPU/load-atomic-local.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
M llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.mir
M llvm/test/CodeGen/AMDGPU/mad-mix-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
M llvm/test/CodeGen/AMDGPU/mad-mix.ll
M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
M llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
M llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
M llvm/test/CodeGen/AMDGPU/repeated-divisor.ll
M llvm/test/CodeGen/AMDGPU/roundeven.ll
M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
M llvm/test/CodeGen/AMDGPU/scmp.ll
M llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
M llvm/test/CodeGen/AMDGPU/select-flags-to-fmin-fmax.ll
M llvm/test/CodeGen/AMDGPU/select.f16.ll
M llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll
A llvm/test/CodeGen/AMDGPU/si-optimize-exec-masking-andn2-wrexec.mir
M llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/ucmp.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-add.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fadd.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmaximum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fminimum.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-fmul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-mul.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
M llvm/test/CodeGen/AMDGPU/vector-reduce-umin.ll
M llvm/test/CodeGen/AMDGPU/vector_rebroadcast.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/waterfall-loop-exec-update-terminator.mir
M llvm/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll
A llvm/test/CodeGen/MIR/AArch64/parse-low-level-type-invalid11.mir
M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
M llvm/test/CodeGen/Mips/llvm-ir/urem.ll
M llvm/test/CodeGen/RISCV/add-imm64-to-sub.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
A llvm/test/CodeGen/RISCV/rvp-widening-add-acc.ll
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/readcycle.ll
M llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_uniform_group_instructions/uniform-group-instructions.ll
M llvm/test/CodeGen/SPIRV/read_image.ll
A llvm/test/CodeGen/X86/pseudo_cmov_lower-bf16.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll
A llvm/test/Instrumentation/DataFlowSanitizer/origin_load_big_endian.ll
M llvm/test/MC/LoongArch/Relocations/sub-expr.s
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/test/MC/RISCV/machine-csr-names.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/test/MC/Sparc/leon-pwrpsr-instruction.s
M llvm/test/TableGen/RegisterByHwMode.td
M llvm/test/Transforms/CodeGenPrepare/X86/freeze-brcond.ll
M llvm/test/Transforms/ConstraintElimination/induction-relational-predicate-latch.ll
M llvm/test/Transforms/ConstraintElimination/sadd-with-overflow.ll
A llvm/test/Transforms/GlobalOpt/CallInst-users-in-GlobalOpt.ll
M llvm/test/Transforms/InstCombine/fabs.ll
M llvm/test/Transforms/InstCombine/icmp-rotate.ll
A llvm/test/Transforms/InstCombine/known-bits-bitcast-from-fp.ll
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/InstCombine/sitofp.ll
A llvm/test/Transforms/InstCombine/uitofp.ll
M llvm/test/Transforms/LoopVectorize/RISCV/type-info-cache-evl-crash.ll
M llvm/test/Transforms/LoopVectorize/VPlan/vplan-scev-address-idioms.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-instruction-cost.ll
M llvm/test/Transforms/LoopVectorize/X86/predicated-udiv.ll
A llvm/test/Transforms/LoopVectorize/narrow-to-per-lane-replicates.ll
M llvm/test/Transforms/LoopVectorize/trunc-extended-icmps.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction1_lshr.ll
M llvm/test/Transforms/LoopVectorize/uniform_across_vf_induction2.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/revec-non-pow2.ll
M llvm/test/Transforms/SLPVectorizer/AMDGPU/reduction-i1-mask.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/remark-zext-incoming-for-neg-icmp.ll
M llvm/test/Transforms/SLPVectorizer/X86/alternate-cmp-swapped-pred.ll
M llvm/test/Transforms/SLPVectorizer/X86/logical-binops-booleanized-leaves.ll
M llvm/test/Transforms/SLPVectorizer/zext-incoming-for-neg-icmp.ll
M llvm/unittests/Analysis/IVDescriptorsTest.cpp
M llvm/unittests/Analysis/ValueTrackingTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp
M llvm/unittests/CodeGen/GlobalISel/KnownFPClassTest.cpp
M llvm/unittests/IR/MetadataTest.cpp
M llvm/unittests/Support/AllocatorTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M mlir/include/mlir/Dialect/OpenMP/OpenMPAttrDefs.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/OpenMP/Transforms/FunctionFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/HostOpFiltering.cpp
M mlir/lib/Dialect/OpenMP/Transforms/MarkDeclareTarget.cpp
M mlir/lib/Dialect/OpenMP/Utils/Utils.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir
M mlir/test/Dialect/OpenMP/invalid-interface.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M orc-rt/CMakeLists.txt
M orc-rt/lib/bedrock/CMakeLists.txt
M orc-rt/test/tools/CMakeLists.txt
M orc-rt/test/unit/CMakeLists.txt
M orc-rt/tools/ogre/CMakeLists.txt
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