[all-commits] [llvm/llvm-project] dbddb0: [𝘀𝗽𝗿] changes introduced through rebase

[Alexander Richardson via All-commits]

  Branch: refs/heads/users/arichardson/spr/tablegen-expose-remapregclassbyhwmode-helper-in-asmmatcher
  Home:   https://github.com/llvm/llvm-project
  Commit: dbddb0d0e5bcf0d8ead45e211a616994617fbcd4
      https://github.com/llvm/llvm-project/commit/dbddb0d0e5bcf0d8ead45e211a616994617fbcd4
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-09-13 (Sun, 13 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
    M llvm/test/TableGen/RegisterByHwMode.td
    M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/TableGen/InstrInfoEmitter.cpp

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.8-beta.1

[skip ci]


  Commit: b97cb24e7051939e874962505abbd19fffbb0dc7
      https://github.com/llvm/llvm-project/commit/b97cb24e7051939e874962505abbd19fffbb0dc7
  Author: Alex Richardson <alexrichardson at google.com>
  Date:   2026-09-13 (Sun, 13 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/TargetParser/RISCVISAInfo.cpp
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/CodeGen/RISCV/rvy/rvy-invalid-operands.mir
    M llvm/test/TableGen/RegisterByHwMode.td
    M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
    M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
    M llvm/utils/TableGen/InstrInfoEmitter.cpp

  Log Message:
  -----------
  rebase

Created using spr 1.3.8-beta.1


Compare: https://github.com/llvm/llvm-project/compare/75cb490c08be...b97cb24e7051

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