[all-commits] [llvm/llvm-project] 64b7df: [PassManager] Store analysis results in contiguous...
Alexander Richardson via All-commits
all-commits at lists.llvm.org
Sun Sep 13 21:41:25 PDT 2026
Branch: refs/heads/users/arichardson/spr/risc-vmc-add-support-for-rvy-loadsstores
Home: https://github.com/llvm/llvm-project
Commit: 64b7dfef40e59b8596a272a431aa3a4abcef33c1
https://github.com/llvm/llvm-project/commit/64b7dfef40e59b8596a272a431aa3a4abcef33c1
Author: Clemens Wasser <clemens.wasser at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerImpl.h
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M polly/include/polly/ScopInfo.h
Log Message:
-----------
[PassManager] Store analysis results in contiguous storage (#222003)
Store per-IR analysis results in a `SmallVector` instead of `std::list`
to avoid a heap allocation per cached analysis. The lookup map stores
the raw result pointer, which stays stable behind the unique_ptr.
geomean -0.12% for optimizing builds, clang build -0.34%
https://llvm-compile-time-tracker.com/compare.php?from=e6734a41bb41d91cb880fe7abce46d8146182518&to=4fc43802817cf8daddbebadb0b7fbfaa6286e7fe&stat=instructions:u
Commit: 2eb8c73f47c7bf6560fc6458713099fd5e1921a3
https://github.com/llvm/llvm-project/commit/2eb8c73f47c7bf6560fc6458713099fd5e1921a3
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
Log Message:
-----------
[AMDGPU] Expose buffer resource num_records width in TargetParser (#220103)
This also fixes the conflict in gfx12.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---------
Co-authored-by: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: 9a9ed337c81c4ca2b95e5f8f7fcb449220c722ae
https://github.com/llvm/llvm-project/commit/9a9ed337c81c4ca2b95e5f8f7fcb449220c722ae
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A llvm/test/tools/dsymutil/Inputs/member-hash/2.o
A llvm/test/tools/dsymutil/Inputs/member-hash/debug-map.map
A llvm/test/tools/dsymutil/X86/member-hash.cpp
Log Message:
-----------
[dsymutil] Test qualified name hashing for members (#223017)
hashFullyQualifiedName walks DW_AT_specification to reach a member's
enclosing struct, so the accelerator table entry for a type nested in an
out-of-line member function definition depends on that walk. Pin the
resulting hash.
The test has lived downstream since the fix that made the function take
its DWARFDie by value instead of by pointer, where the pointee went out
of scope during the walk. Give it a debug map of its own describing
member-hash/2.o rather than extending the shared dummy-debug-map.map,
which describes a different set of objects.
rdar://184990209
Commit: e41147d567ee1f3eddc77ff3cbf505a4d5158e84
https://github.com/llvm/llvm-project/commit/e41147d567ee1f3eddc77ff3cbf505a4d5158e84
Author: Ryan Buchner <rbuchner at qti.qualcomm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/XVentanaCondOps-valid.s
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Remove Ventana Conditional Ops (#221042)
This extension is used by any silicon as far as I am aware.
If any person/company was reliant on this extension, the extension
can be added back in under the same/different name.
AI Usage: Assisted by Codex
Commit: ecb66ef84fc881eb8bea392cbd9b61f83605b196
https://github.com/llvm/llvm-project/commit/ecb66ef84fc881eb8bea392cbd9b61f83605b196
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
Log Message:
-----------
[CIR][NFCI] Refactor uses of 'mlir::Location' vs 'SourceRange' on calls/etc (#222981)
As a prerequisite to an upcoming patch, emitCall needs access to the
Clang source locations, not just the mlir::Location. We're going to need
this in quite a few more places in the future, since there are various
diagnostics that use clang locations in the code generation.
This patch also has to change the RAII source location stuff, which I
switched to SourceRange. This should improve the amount of data we give
for our source information.
I DID have to remove the assertion on it though, because we do have a
few places that intentionally wanted an invalid location if other stuff
wasn't available (see the CUDA use in particular), but otherwise this
should allow us to improve our source location info, AND use it for
diagnostics in the future.
Commit: 9a762fce97374fb1ce5d2f21f99b5a7ed584ba71
https://github.com/llvm/llvm-project/commit/9a762fce97374fb1ce5d2f21f99b5a7ed584ba71
Author: Erich Keane <ekeane at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/test/CIR/CodeGen/atomic.c
Log Message:
-----------
[CIR] Implement 'simple' atomic inc/dec. (#222730)
This only works for types where a compare-exchange instruction (or just
a lock-free implementation matters) is possible, and a loop isn't
necessary. This is basically just a conversion of classic-codegen,
except it clarifies some of the logic (particularly around bools).
Commit: 28efe19f92567ec666e205b860cfd77f6f1764fc
https://github.com/llvm/llvm-project/commit/28efe19f92567ec666e205b860cfd77f6f1764fc
Author: Zaara Syeda <syzaara at ca.ibm.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M clang/docs/UsersManual.md
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Options/Options.td
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/CodeGen/keep-inline-functions.c
A clang/test/CodeGen/keep-inline-functions.cpp
A clang/test/CodeGen/keep-inline-functions.cppm
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fkeep-inline-functions.c
Log Message:
-----------
[Clang] Implement -fkeep-inline-functions (#218533)
Implement the -fkeep-inline-functions flag, which forces selected inline
function definitions to be emitted into the object file even if they
have been inlined into all their callers. The function retention
behavior follows GCC's semantics.
The front-end has been modified to:
- emit the selected functions even if they are unused; and
- add the selected functions to llvm.compiler.used/llvm.used to ensure
they are retained.
The functions selected for emission are inline function definitions that
are available in the current translation unit. available_externally
definitions are excluded because their authoritative definitions are
expected to be emitted by another translation unit.
This is also done for C99 inline function external definitions with
external linkage, which would normally be emitted into the object file
anyway, to ensure the functions are retained for LTO purposes.
See the proposed Clang documentation update for details on the function
selection criteria.
Commit: 204b703adb18599fc7f5d7b1bc0b0b410ca1ce15
https://github.com/llvm/llvm-project/commit/204b703adb18599fc7f5d7b1bc0b0b410ca1ce15
Author: Anshul Nigham <nigham at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
Fix bazel build for libc/test/UnitTest:string_utils (#223051)
Fixes https://github.com/llvm/llvm-project/pull/222988 (commit
18db3eee9d04) by adding missing dependencies.
Commit: 105ff16f816ffdce14b1d4895d8584971ef5192c
https://github.com/llvm/llvm-project/commit/105ff16f816ffdce14b1d4895d8584971ef5192c
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M lld/test/ELF/lto/riscv-target-abi.ll
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/test/CodeGen/RISCV/subtarget-features-std-ext.ll
M llvm/test/CodeGen/RISCV/target-abi-invalid.ll
M llvm/test/MC/RISCV/target-abi-invalid.s
M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
Log Message:
-----------
[RISCV] Change RISCVABI::computeTargetABI() to return Expected<ABI>
Return Expected<ABI> instead of printing to errs()/reportFatalUsageError
internally, so callers decide whether to fall back to the default ABI
or treat the failure as fatal, and so it's unit-testable. Also fold the
duplicated Hard-float 'f'/'d' ABI checks from RISCVAsmParser.cpp and
RISCVISelLowering.cpp into computeTargetABI(), and add RISCVBaseInfoTest
coverage for the error paths.
This change was created with the help of AI tools
Reviewed By: lenary
Pull Request: https://github.com/llvm/llvm-project/pull/213410
Commit: 51450333e1fd156fcdb20b61d7c70ed96461812b
https://github.com/llvm/llvm-project/commit/51450333e1fd156fcdb20b61d7c70ed96461812b
Author: YongKang Zhu <yongzhu at fb.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
Log Message:
-----------
[BOLT][AArch64][Android] Only the dumping thread can longjmp (#222719)
`__bolt_instr_recovery_active` is a process global flag and the reader
in `boltHandleFatalAndRecover()` runs on any thread. When a dump is in
flight, another thread that fails `assert()` or exhausts `GlobalAlloc`
in `instrumentIndirectCall()` could see the flag set, longjmp with the
dumping thread's buffer and restore the dump thread's sp/fp/lr. This
is wrong since the thread would then run on the dumping thread's stack
and later release a mutex that it does not own or hold.
`GlobalWriteProfileMutex` already serializes the writers, so one buffer
would be sufficient; only the reader side needs to know who owns the
buffer. Replace the flag with `__bolt_instr_recovery_tid` holding the
owner's thread ID, and longjmp only when it matches `__gettid()`. Other
threads will fall through to just record the failure and return.
Added a `__gettid()` syscall wrapper, for aarch64 only.
Assited-by: opus
Commit: 5c27600b852b9a86b7811142482a09defd963ad3
https://github.com/llvm/llvm-project/commit/5c27600b852b9a86b7811142482a09defd963ad3
Author: Deric C. <cheung.deric at gmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
A clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/atomic64-typed-resource.ll
Log Message:
-----------
[DirectX] Add texture support to atomicrmw lowering (#221369)
Fixes https://github.com/llvm/llvm-project/issues/218034
Fixes https://github.com/llvm/llvm-project/issues/186154
atomicrmw lowering didn't support textures. This PR adds that missing
support.
Assisted by: Claude Opus 5
Commit: 364bed30971df7fb50d7aadfc21f3996a97bf3a4
https://github.com/llvm/llvm-project/commit/364bed30971df7fb50d7aadfc21f3996a97bf3a4
Author: Tomohiro Kashiwada <kikairoya at gmail.com>
Date: 2026-09-12 (Sat, 12 Sep 2026)
Changed paths:
M clang/include/clang/Driver/ToolChain.h
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
Log Message:
-----------
(NFC)[Clang][Driver] Add ToolChain::GetFilePathIfExists and use it (#221063)
Replaces patterns like `if (TC.GetFilePath("file") != "file")` to avoid
repeating `"file"`.
Commit: 393710bbf74c4e7b92226603a18ead0bba70a8a0
https://github.com/llvm/llvm-project/commit/393710bbf74c4e7b92226603a18ead0bba70a8a0
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
A llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
Log Message:
-----------
Reland "[llvm][AArch64] Ensure stack alignment in non-sibcall tail calls with FPDiff" (#220406)
When a caller has a non-multiple of the minimum stack alignment more
argument stack space than the callee it is tail calling, we need to ensure that
the resulting FPDiff's magnitude has been rounded up to a multiple of the
platform's minimum stack alignment.
In this re-land there is a fixup to 234ce03692ede13ffd2fcb35570d801c1e332814,
which, because of the wrong order, wasn't actually moving NumBytes after
FPDiff had been re-aligned.
rdar://184474075
Commit: f77ec648706b957698a61e54a715bd69042ce491
https://github.com/llvm/llvm-project/commit/f77ec648706b957698a61e54a715bd69042ce491
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP] Fix -Wunused-lambda-capture in #223016 (#223053)
Clang will warn on this despite this being required for MSVC, so add a
workaround for now.
Commit: d42c701dc3d00dacff3806ea428a274aae39fed0
https://github.com/llvm/llvm-project/commit/d42c701dc3d00dacff3806ea428a274aae39fed0
Author: Kunal Pathak <kunalspathak at hotmail.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
A llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-indirect-call-anchor.prof
A llvm/test/Transforms/SampleProfile/Inputs/profile-mismatch-indirect-call.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-multiple-sampled-callees.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-zero-callee.prof
A llvm/test/Transforms/SampleProfile/non-probe-stale-profile-indirect-call-anchor.ll
A llvm/test/Transforms/SampleProfile/profile-mismatch-indirect-call.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch.ll
Log Message:
-----------
[SampleProfile] Ignore unsampled callees in profile anchors (#219335)
Sample profiles can retain zero-count callee entries in both flattened
body call targets and
unflattened callsite samples:
```text
probe 12:
foo: 10
cleanup: 0
```
Counting every entry as a distinct callee converts the uniquely sampled
foo callsite into
UnknownIndirectCallee. It then fails to match the direct IR call to foo,
causing valid
samples to be reported as stale.
Ignore zero-count entries when the same location has a sampled callee.
Preserve the existing
behavior for genuine multi-callee sites and locations where every callee
has zero samples.
```text
foo: 10, cleanup: 0 -> foo
foo: 10, bar: 1 -> UnknownIndirectCallee
foo: 0, cleanup: 0 -> unchanged
```
The change covers both:
- flattened call targets from body samples;
- inline callees from unflattened callsite samples.
## Related fixes
This is downstream profile-matching robustness related to #219079.
Those changes prevent invalid pseudo-probe context earlier in the
pipeline. This change
ensures that any zero-sample entries reaching the profile matcher are
not treated as
evidence of another executed callee.
## Tests
Added regression coverage for zero-sample callees, genuine multiple
sampled callees,
flattened body targets, and unflattened callsite samples.
Assisted by: Claude
Commit: 55221f7a2baca65325ad073eabdaf8cc18472e12
https://github.com/llvm/llvm-project/commit/55221f7a2baca65325ad073eabdaf8cc18472e12
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M flang/test/Driver/flang-f-opts.f90
Log Message:
-----------
[Flang/CI] Hotfix of flang/test/Driver/flang-f-opts.f90. (#223076)
The test started failing in Flang CI after #218533. This is just a
hotfix.
Commit: 17de86741560e43304c8c013092d80ae91d401ff
https://github.com/llvm/llvm-project/commit/17de86741560e43304c8c013092d80ae91d401ff
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M llvm/lib/IR/Dominators.cpp
Log Message:
-----------
[IR] Make verify<domtree> work in non-asserts builds (#223066)
It doesn't make sense to lose this test coverage in non-assert builds,
and I would expect a release build of opt to have a working
verify<domtree> pass. This also better matches the behavior of the other
verify<*> passes.
Commit: 242ccbf6b6d9d090762a87138c854f2d93b6ab60
https://github.com/llvm/llvm-project/commit/242ccbf6b6d9d090762a87138c854f2d93b6ab60
Author: Aiden Grossman <aidengrossman at google.com>
Date: 2026-09-11 (Fri, 11 Sep 2026)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
Log Message:
-----------
[BOLT] Fix -Wunused-template (#222439)
This was enabled by default in LLVM 23.1.0. It was disabled in LLVM
23.1.1, but it makes sense to fix the outstanding issues given they are
real.
Commit: 53f620e83c1554786c39ee2d3c1fada6d9f8e8c5
https://github.com/llvm/llvm-project/commit/53f620e83c1554786c39ee2d3c1fada6d9f8e8c5
Author: Alex Richardson <alexrichardson at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
M clang/docs/UsersManual.md
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
A clang/test/CodeGen/keep-inline-functions.c
A clang/test/CodeGen/keep-inline-functions.cpp
A clang/test/CodeGen/keep-inline-functions.cppm
A clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fkeep-inline-functions.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M flang/test/Driver/flang-f-opts.f90
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerImpl.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/lib/IR/Dominators.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
A llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/atomic64-typed-resource.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/XVentanaCondOps-valid.s
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/RegisterByHwMode.td
A llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-indirect-call-anchor.prof
A llvm/test/Transforms/SampleProfile/Inputs/profile-mismatch-indirect-call.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-multiple-sampled-callees.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-zero-callee.prof
A llvm/test/Transforms/SampleProfile/non-probe-stale-profile-indirect-call-anchor.ll
A llvm/test/Transforms/SampleProfile/profile-mismatch-indirect-call.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch.ll
A llvm/test/tools/dsymutil/Inputs/member-hash/2.o
A llvm/test/tools/dsymutil/Inputs/member-hash/debug-map.map
A llvm/test/tools/dsymutil/X86/member-hash.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M polly/include/polly/ScopInfo.h
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.8-beta.1
[skip ci]
Commit: e806adfb2ddb7b3d7e39f43787d37afc2196e705
https://github.com/llvm/llvm-project/commit/e806adfb2ddb7b3d7e39f43787d37afc2196e705
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2026-09-13 (Sun, 13 Sep 2026)
Changed paths:
M bolt/lib/Core/BinaryFunction.cpp
M bolt/runtime/common.h
M bolt/runtime/instr.cpp
M bolt/runtime/sys_aarch64.h
M clang/docs/UsersManual.md
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/ToolChain.h
M clang/include/clang/Options/Options.td
M clang/lib/CIR/CodeGen/CIRGenBuilder.h
M clang/lib/CIR/CodeGen/CIRGenCUDARuntime.cpp
M clang/lib/CIR/CodeGen/CIRGenCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenCall.cpp
M clang/lib/CIR/CodeGen/CIRGenClass.cpp
M clang/lib/CIR/CodeGen/CIRGenDecl.cpp
M clang/lib/CIR/CodeGen/CIRGenDeclOpenACC.cpp
M clang/lib/CIR/CodeGen/CIRGenException.cpp
M clang/lib/CIR/CodeGen/CIRGenExpr.cpp
M clang/lib/CIR/CodeGen/CIRGenExprAggregate.cpp
M clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp
M clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.cpp
M clang/lib/CIR/CodeGen/CIRGenFunction.h
M clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp
M clang/lib/CIR/CodeGen/CIRGenSYCL.cpp
M clang/lib/CIR/CodeGen/CIRGenVTables.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/Driver/ToolChain.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Cygwin.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/WebAssembly.cpp
M clang/test/CIR/CodeGen/atomic.c
M clang/test/CIR/CodeGen/paren-list-agg-init.cpp
M clang/test/CIR/CodeGenCXX/init-priority-attr.cpp
M clang/test/CIR/CodeGenHIP/ternary-struct-addrspace.hip
M clang/test/CIR/CodeGenOpenACC/compute-reduction-clause-int.cpp
A clang/test/CodeGen/keep-inline-functions.c
A clang/test/CodeGen/keep-inline-functions.cpp
A clang/test/CodeGen/keep-inline-functions.cppm
A clang/test/CodeGenHLSL/builtins/RWTexture-Interlocked.hlsl
M clang/test/Driver/clang_f_opts.c
A clang/test/Driver/fkeep-inline-functions.c
M clang/test/Driver/print-supported-extensions-riscv.c
M clang/test/Preprocessor/riscv-target-features.c
M flang/test/Driver/flang-f-opts.f90
M llvm/docs/RISCVUsage.md
M llvm/docs/ReleaseNotes.md
M llvm/include/llvm/IR/IntrinsicsDirectX.td
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerImpl.h
M llvm/include/llvm/Support/GenericLoopInfoImpl.h
M llvm/include/llvm/TargetParser/AMDGPUTargetParser.h
M llvm/include/llvm/TargetParser/RISCVISAInfo.h
M llvm/include/llvm/Transforms/IPO/SampleProfileMatcher.h
M llvm/lib/IR/Dominators.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/DirectX/DXILOpLowering.cpp
M llvm/lib/Target/DirectX/DXILResourceAccess.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
R llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/TargetParser/AMDGPUTargetParser.cpp
M llvm/lib/TargetParser/RISCVISAInfo.cpp
M llvm/lib/Transforms/IPO/SampleProfileMatcher.cpp
M llvm/lib/Transforms/Scalar/InferAlignment.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/arm64ec-varargs.ll
A llvm/test/CodeGen/AArch64/sme-za-tailcall-fpdiff-align.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-nonscalar.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture-unsupported-kind.ll
A llvm/test/CodeGen/DirectX/ResourceAtomicBinOp-texture.ll
M llvm/test/CodeGen/DirectX/ResourceAtomicBinOp.ll
M llvm/test/CodeGen/DirectX/ShaderFlags/atomic64-typed-resource.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/features-info.ll
M llvm/test/CodeGen/RISCV/pr148084.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/zicond-opts.ll
M llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll
R llvm/test/MC/RISCV/XVentanaCondOps-valid.s
M llvm/test/MC/RISCV/rvy/rvy-invalid-load-store.s
M llvm/test/MC/RISCV/rvy/rvy-valid-load-store-64.s
M llvm/test/MC/RISCV/rvy/rvy-valid-load-store.s
M llvm/test/MC/RISCV/rvy/rvyc-invalid-load-store.s
M llvm/test/MC/RISCV/rvy/rvyc-valid-load-store.s
M llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
M llvm/test/TableGen/RegClassByHwMode.td
M llvm/test/TableGen/RegisterByHwMode.td
A llvm/test/Transforms/SampleProfile/Inputs/non-probe-stale-profile-indirect-call-anchor.prof
A llvm/test/Transforms/SampleProfile/Inputs/profile-mismatch-indirect-call.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-multiple-sampled-callees.prof
A llvm/test/Transforms/SampleProfile/Inputs/pseudo-probe-profile-mismatch-zero-callee.prof
A llvm/test/Transforms/SampleProfile/non-probe-stale-profile-indirect-call-anchor.ll
A llvm/test/Transforms/SampleProfile/profile-mismatch-indirect-call.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-profile-mismatch.ll
A llvm/test/tools/dsymutil/Inputs/member-hash/2.o
A llvm/test/tools/dsymutil/Inputs/member-hash/debug-map.map
A llvm/test/tools/dsymutil/X86/member-hash.cpp
M llvm/tools/llubi/lib/Interpreter.cpp
M llvm/unittests/Target/RISCV/RISCVBaseInfoTest.cpp
M llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M polly/include/polly/ScopInfo.h
M utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel
Log Message:
-----------
drop the fake vendor extension, use feature flag instead and rebase
Created using spr 1.3.8-beta.1
Compare: https://github.com/llvm/llvm-project/compare/89dcbe57390a...e806adfb2ddb
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