[all-commits] [llvm/llvm-project] a129f8: [TableGen] Use BitVector for RegisterSet in AsmMat...

[Kazu Hirata via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a129f830b8727c51c087db8278035d2c6f08da25
      https://github.com/llvm/llvm-project/commit/a129f830b8727c51c087db8278035d2c6f08da25
  Author: Kazu Hirata <kazu at google.com>
  Date:   2026-09-13 (Sun, 13 Sep 2026)

  Changed paths:
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  [TableGen] Use BitVector for RegisterSet in AsmMatcherEmitter (NFC) (#222525)

This patch replaces std::set with BitVector for RegisterSet in
AsmMatcherEmitter.

Without this patch, RegisterSet is represented as
std::set<const Record *, LessRecordByID>.  On targets with large
register files like AMDGPU (~3,000 registers), repeatedly computing set
intersections and subset checks using std::set nodes incurs
significant overhead.

This patch assigns each register record a dense bit index ordered by
LessRecordByID.  This allows us to represent RegisterSet as a
BitVector, enabling fast bitwise operations for set intersections and
subset checks.

This reduces the wall-clock time of generating AMDGPUGenAsmMatcher.inc
from 39.53s to 31.32s (a 20.8% speedup) across 3 runs while producing
bit-for-bit identical output across all targets.

Assisted-by: Antigravity



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