[all-commits] [llvm/llvm-project] 8864a4: [Mips] Handle division by zero trap on MIPS1 (#201...

[neoto via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8864a4bb996d6bb541b0974d34991da40a643c90
      https://github.com/llvm/llvm-project/commit/8864a4bb996d6bb541b0974d34991da40a643c90
  Author: neoto <48843913+neoto at users.noreply.github.com>
  Date:   2026-09-13 (Sun, 13 Sep 2026)

  Changed paths:
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.td
    M llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll
    M llvm/test/CodeGen/Mips/llvm-ir/srem.ll
    M llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
    M llvm/test/CodeGen/Mips/llvm-ir/urem.ll

  Log Message:
  -----------
  [Mips] Handle division by zero trap on MIPS1 (#201133)

LLVM currently emits the `teq` instruction for every arch version, but
`teq` is unsupported on MIPS1.
This special cases MIPS1 so that `bne(z)` and `break` are emitted
instead.
Compared to https://github.com/llvm/llvm-project/pull/81311, this should
also handle liveness as far as I can tell.

I didn't want to add another bool to the argument list so I combined
`IsMicroMips` and what was supposed to be `IsMips1` into an enum, which
feels much nicer in this case.
Besides that and the main change, I also changed the `hasSideEffects`
bit for `PseudoSDIV` and `PseudoUDIV`,
which allows the delay slot to be usefully filled - well, at least with
`-O1`+. This seems to be in line with what GCC does:
https://godbolt.org/z/zqcG5ha35

Tested using clang directly and through Zig's LLVM backend.

Closes https://github.com/llvm/llvm-project/issues/80554
Supersedes https://github.com/llvm/llvm-project/pull/81311



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