[all-commits] [llvm/llvm-project] 46fc5b: [CIR] Accept `_BitInt` wider than 128 bits in x86_...

[Adam Smith via All-commits]

  Branch: refs/heads/users/adams381/cir-callconv-x86_64-bitint-wide
  Home:   https://github.com/llvm/llvm-project
  Commit: 46fc5bdf707e8addec5d50c3eb48dec001c1adb9
      https://github.com/llvm/llvm-project/commit/46fc5bdf707e8addec5d50c3eb48dec001c1adb9
  Author: Adam Smith <adams at nvidia.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M clang/include/clang/CIR/Dialect/IR/CIROps.td
    M clang/lib/CIR/Dialect/Transforms/CallConvLoweringPass.cpp
    M clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
    M clang/test/CIR/CodeGen/bitint-split-storage-nyi.c
    M clang/test/CIR/CodeGen/bitint.c
    A clang/test/CIR/CodeGen/call-conv-lowering-x86_64-bitint.c
    M clang/test/CIR/CodeGenBuiltins/builtin-bit.cpp
    M clang/test/CIR/Transforms/abi-lowering/x86_64-bitint.cir
    M clang/test/CIR/Transforms/abi-lowering/x86_64-int-nyi.cir

  Log Message:
  -----------
  [CIR] Accept `_BitInt` wider than 128 bits in x86_64 callconv lowering

With byval in place, a `_BitInt` wider than 128 bits can classify
Indirect and flow through the same byval/sret path as an oversized
aggregate.

That turned up a latent bug, fixed here since it was not reachable or
testable before: the byval/sret pointee type was using the raw declared
width instead of the padded storage width (e.g. `i200` instead of
`i256`), understating the copy size.

Widths whose padded storage integer is not a whole number of 16 bytes,
such as `_BitInt(129)` at `i192`, still have no in-memory layout in CIR
and now reach that gap through the byval and sret pointee instead of
through the classifier.  They stay NYI.

Drop the opt-out from the three CIR lit tests gated on this.

Assisted-by: Cursor / claude-opus-5



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