[all-commits] [llvm/llvm-project] abf413: [AggressiveInstCombine] Use DL.fitsInLegalInteger ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abf41391777c822d4f5010b1f38d5a0f09102ea1
      https://github.com/llvm/llvm-project/commit/abf41391777c822d4f5010b1f38d5a0f09102ea1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/AArch64/combine_ignore_debug.ll
    M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
    A llvm/test/Transforms/AggressiveInstCombine/RISCV/or-load.ll
    A llvm/test/Transforms/AggressiveInstCombine/RISCV/store-merge.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Use DL.fitsInLegalInteger instead of TTI.isTypeLegal in consecutive load/store combine. (#220310)

riscv64 doesn't have a legal i32 type in the backend, but we
support i16, and i32 loads/stores. AArch64 also supports i16
loads/stores even though i16 isn't legal.

Replace TTI.isTypeLegal with DL.fitsInLegalInteger and a check for
a power of 2 number of bytes. This covers i16 and i32 for RISC-V
and i16 for AArch64.

We could further relax this to cover types that the backend can handle
by splitting, but I'd like to leave that for a future patch.

I had to update some existing tests to have more accurate datalayouts.

The RISC-V tests are reduced from existing tests from AArch64 or X86 to
show some of the load sizes that can now be matched.



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