[all-commits] [llvm/llvm-project] 6c68a1: [CostModel][X86] Add variable divisor div/rem cost...

[Adam Scott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6c68a1661af7dce1f121fd20dfce72f4ddc4afc9
      https://github.com/llvm/llvm-project/commit/6c68a1661af7dce1f121fd20dfce72f4ddc4afc9
  Author: Adam Scott <adamscott200322 at gmail.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    A llvm/test/Analysis/CostModel/X86/div-rem-i64.ll
    A llvm/test/Analysis/CostModel/X86/div-rem-strictfp.ll
    M llvm/test/Analysis/CostModel/X86/div.ll
    A llvm/test/Analysis/CostModel/X86/masked-divrem.ll
    M llvm/test/Analysis/CostModel/X86/rem.ll
    M llvm/test/Analysis/CostModel/X86/size-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll
    M llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
    M llvm/test/Transforms/LoopVectorize/X86/divs-with-tail-folding.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr109581-unused-blend.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll
    M llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
    M llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
    M llvm/test/Transforms/SLPVectorizer/X86/div-possibly-extended-with-poisons.ll
    M llvm/test/Transforms/SLPVectorizer/X86/multi-nodes-to-shuffle.ll
    M llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
    M llvm/test/Transforms/SLPVectorizer/X86/parent-node-split-non-schedulable.ll
    M llvm/test/Transforms/SLPVectorizer/X86/runtime-alias-checks.ll

  Log Message:
  -----------
  [CostModel][X86] Add variable divisor div/rem costs for scalar and <=i32 vectors (#215124)

Div and rem by a variable divisor have no X86 cost entry at all, so they
fall through to the BasicTTI default and cost 1. A 20 to 40 cycle
unpipelined instruction ends up priced the same as an add.

That mattered less while vector integer division always scalarized,
since the price was wrong but the decision was usually right anyway.
After #205263 the <=i32 shapes lower through a float divide, so the
vector cost model is now describing a sequence that really exists and it
still prices it as scalarization.

This adds scalar entries plus five feature gated vector tables.

Numbers are the maximum llvm-mca Block RThroughput across the CPUs that
fold the shape with the low power lines excluded (atom and jaguar).
Vector entries take the max within the tier a CPU's feature level
selects, since the lookup takes the first matching table. Scalar takes
it across all of them.

rem is priced the same as div because a variable rem is the same
instruction and the hardware hands back the remainder in rdx or AH. For
vector the fold pays a multiply and subtract to recover it but the
divide dominates the throughput so the number doesnt change.

div-rem-strictfp.ll is new and pins the strictfp gate. Two SLP tests run
on forced negative thresholds and needed those raised so both produce
output identical to before at the new value.

---------

Co-authored-by: Simon Pilgrim <llvm-dev at redking.me.uk>



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