[all-commits] [llvm/llvm-project] 5d6c71: [VPlan] Narrow VPWidenGEPRecipe if only its first ...

[Mel Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d6c7162093204a3cf6914acafa73dea59134cc2
      https://github.com/llvm/llvm-project/commit/5d6c7162093204a3cf6914acafa73dea59134cc2
  Author: Mel Chen <mel.chen at sifive.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_prefer_scalable.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/outer_loop_test1_no_explicit_vect_width.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-avoid-scalarization.ll
    A llvm/test/Transforms/LoopVectorize/RISCV/interleaved-load-masked-store.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
    M llvm/test/Transforms/LoopVectorize/X86/gep-use-outside-loop.ll
    M llvm/test/Transforms/LoopVectorize/X86/outer_loop_test1_no_explicit_vect_width.ll
    M llvm/test/Transforms/LoopVectorize/dereferenceable-info-from-assumption-constant-size.ll
    M llvm/test/Transforms/LoopVectorize/nested-outer-loop-vect.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_contiguous.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_hcfg_construction.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_scalable.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_test1.ll
    M llvm/test/Transforms/LoopVectorize/outer_loop_test2.ll
    M llvm/test/Transforms/LoopVectorize/vplan-vectorize-inner-loop-reduction.ll
    M llvm/test/Transforms/LoopVectorize/vplan-widen-call-instruction.ll
    M llvm/test/Transforms/LoopVectorize/vplan-widen-select-instruction.ll

  Log Message:
  -----------
  [VPlan] Narrow VPWidenGEPRecipe if only its first lane is used. (#221171)

Extend existing narrowing in legalizeAndOptimizeInductions, already
applied to VPReplicateRecipe and VPWidenRecipe, to VPWidenGEPRecipe as
well. This improves cases where an interleaved access's insert position
shares an address calculation with a strided access (see
RISCV/interleaved-load-masked-store.ll), which previously caused the
legacy cost model to classify the address as non-uniform.



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications