[all-commits] [llvm/llvm-project] 4f32e4: [AArch64] Parameterize repeated FP divisor combin...

[yamash-fj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f32e473933d4a039d13fe2c0a4ccdde73c8b929
      https://github.com/llvm/llvm-project/commit/4f32e473933d4a039d13fe2c0a4ccdde73c8b929
  Author: yamash-fj <yamashita.ta-16 at fujitsu.com>
  Date:   2026-09-11 (Fri, 11 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64Features.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64Processors.td
    M llvm/test/CodeGen/AArch64/fdiv-combine.ll

  Log Message:
  -----------
  [AArch64]  Parameterize repeated FP divisor combine threshold by subtarget (#216930)

Changes:
This patch makes the threshold for combining repeated FP divisors
configurable per AArch64 subtarget, instead of using a single fixed
value 3 for all CPUs. Additionaly, set this value 2 for A64FX based on
observed profitability for this transform on A64FX.

Motivation:
Today, AArch64 uses a fixed threshold of 3 for reciprocal transform.
This means the transform runs when there are 3 FDIVs with the same
divisor (not 2). That is conservative for some subtargets, and it can
miss profitable opportunities on CPUs such as A64FX, where a lower
threshold appears to produce better code generation.
```
a / D; b / D; ...
=>
recip = 1.0 / D; a * recip; b * recip; ...
```

Note:
It does not change the semantics of the reciprocal transform itself.



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