[all-commits] [llvm/llvm-project] 5b2b0c: [mlir] Migrate AMDGPU/ROCDL to targets, not chipse...
Krzysztof Drewniak via All-commits
all-commits at lists.llvm.org
Thu Sep 10 15:53:42 PDT 2026
Branch: refs/heads/users/krzysz00/mlir-target-info-tablegen
Home: https://github.com/llvm/llvm-project
Commit: 5b2b0c0572a9b637c83c6d145087637a2d1bd65c
https://github.com/llvm/llvm-project/commit/5b2b0c0572a9b637c83c6d145087637a2d1bd65c
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-10 (Thu, 10 Sep 2026)
Changed paths:
M clang/test/CodeGen/link-builtin-bitcode.c
M llvm/lib/Target/AMDGPU/AMDGPU.td
M mlir/docs/ReleaseNotes.md
M mlir/include/mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h
M mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/include/mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h
M mlir/include/mlir/Conversion/MathToROCDL/MathToROCDL.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/AMDGPU/Utils/Chipset.h
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.h
A mlir/include/mlir/Dialect/LLVMIR/ROCDLTargetInfo.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToROCDLPipeline.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/GPU/Transforms/PromoteShuffleToAMDGPU.cpp
M mlir/lib/Dialect/GPU/Transforms/SubgroupReduceLowering.cpp
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
A mlir/lib/Dialect/LLVMIR/IR/ROCDLTargetInfo.cpp
R mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp-gfx1170.mlir
M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp.mlir
M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats.mlir
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dpp.mlir
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/global-prefetch.mlir
M mlir/test/Conversion/AMDGPUToROCDL/global_transpose_load.mlir
M mlir/test/Conversion/AMDGPUToROCDL/lds-barrier-gfx90c.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait_tensor.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait_unsupported.mlir
A mlir/test/Conversion/AMDGPUToROCDL/mfma-fp8-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
A mlir/test/Conversion/AMDGPUToROCDL/mfma-reduce-precision-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-ext.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-trunc-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-trunc.mlir
A mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1200-invalid.mlir
A mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1250-invalid.mlir
A mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane-var.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swizzle.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx1250_invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx950_invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_reject.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx11.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx1250.mlir
M mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-extf.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-truncf-tensor.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-truncf.mlir
M mlir/test/Conversion/GPUCommon/lower-global-id.mlir
M mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir
M mlir/test/Conversion/GPUCommon/memory-attrbution.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-attrs.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-noalias-attrs.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-noalias-warning.mlir
M mlir/test/Conversion/GPUToROCDL/constant-address-space.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barrier.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-hip.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-ballot.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-dialect.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-named-barrier.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-named-barrier-non-const.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-opencl.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/GPUToROCDL/memref.mlir
M mlir/test/Conversion/GPUToROCDL/private-func-no-c-interface.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
A mlir/test/Dialect/GPU/promote-shuffle-amdgpu-invalid.mlir
M mlir/test/Dialect/GPU/promote-shuffle-amdgpu.mlir
M mlir/test/Integration/GPU/ROCM/gpu-to-hsaco.mlir
M mlir/test/Integration/GPU/ROCM/printf.mlir
M mlir/test/Integration/GPU/ROCM/two-modules.mlir
M mlir/test/Integration/GPU/ROCM/vecadd.mlir
M mlir/test/Integration/GPU/ROCM/vector-transferops.mlir
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
M mlir/unittests/Dialect/AMDGPU/AMDGPUUtilsTest.cpp
M mlir/unittests/Dialect/LLVMIR/CMakeLists.txt
A mlir/unittests/Dialect/LLVMIR/ROCDLTargetInfoTest.cpp
Log Message:
-----------
[mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions
**migration tl;dr:** `chipset=` becomes `triple=`, migrate off of
`amdgpu::Chipset` to `ROCDL::TargetInfo`, and eventually change
`gfxXYZ` to `amdgpuX.YZ-amd-amdhsa` in that `triple` argument.
`amdgpu::Chipset` was an awkward hack that was hard to keep up to date
with changes in the compiler/new architectures, and didn't properly
support generic targets (and has been strongly disfavored by the
compiler team).
This PR replaces `amdgpu::Chipset` with `ROCDL::TargetInfo`, a
structure that uses LLVM's TargetParser and the underlying LLVM
features tables to get the real nature of the target being compiled
for.
This also helps MLIR move to
new-style (`-mtriple=amdgpuX.YZ-amd-amdhsa`) over "old
style" (`-mtriple=amdgcn-amd-amdhsa -mcpu=gfxXYZ`) triples.
The utility structure is moved from AMDGPU to ROCDL, both because it's
tied to LLVM rather directly and because projects like Triton should
be able to use these feature tests without pulling in the AMDGPU
dialect and its memref dependencies.
This migration also fixes a few correctness issues:
- Atomic emulation was producing floating-point additions that don't
exist on gfx90c (even though it's "after" gfx90a) and gfx908's more
precise about where emulation is needed.
- gfx90c was also being handed a bare `s_barrier`, but it has no
hardware barrier back-off, so it needs the inline asm workaround.
- gfx950 won't allow xf32 MFMAs anymore.
- permlane_swap forms that don't exist on some architectures no
longer lower.
- gfx11.7 is now listed as an OCP FP8-having target.
Some checks still need to check for a generation (ex. when encoding
s_waitcnt or what the semantics of a WMMA are) go through an
`isGeneration(N)` method, which checks for having instructions from
generation N but not N+1.
(The barrier lowering has been reordered to account for gfx13 not
having, but also not needing, BackOffBarrier.)
This migration changes the `chipset` options on most passes to triple,
chip, features of argument. The `triple` option can, in addition to
being an actual triple, a `gfxXYZ` name for compatibility. The same
rename happens to the IR-visible `chipset` attribute on
`transform.apply_conversion_patterns.gpu.gpu_to_rocdl` and
`transform.apply_patterns.gpu.gpu_shuffle_to_amdgpu`, which does break
existing transform scripts.
Chipset is deprecated instead of being removed so that folks have time
to migrate.
AI disclosure: I steered this, Claude wrote the code, I tried to clean
up the docs.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: b460d0c3f5140d50b301750baf2a58871c90fbd8
https://github.com/llvm/llvm-project/commit/b460d0c3f5140d50b301750baf2a58871c90fbd8
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-10 (Thu, 10 Sep 2026)
Changed paths:
M mlir/docs/ReleaseNotes.md
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/GPU/Pipelines/Passes.h
M mlir/include/mlir/Dialect/GPU/TransformOps/GPUTransformOps.td
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLTargetInfo.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToROCDLPipeline.cpp
M mlir/lib/Dialect/GPU/TransformOps/GPUTransformOps.cpp
M mlir/lib/Dialect/GPU/Transforms/ROCDLAttachTarget.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLTargetInfo.cpp
M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats-ocp.mlir
M mlir/test/Conversion/AMDGPUToROCDL/8-bit-floats.mlir
M mlir/test/Conversion/AMDGPUToROCDL/amdgpu-to-rocdl.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx11.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-gfx9.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dot-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/dpp.mlir
M mlir/test/Conversion/AMDGPUToROCDL/gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/global-prefetch.mlir
M mlir/test/Conversion/AMDGPUToROCDL/global_transpose_load.mlir
M mlir/test/Conversion/AMDGPUToROCDL/lds-barrier-gfx90c.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/load_lds.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait_tensor.mlir
M mlir/test/Conversion/AMDGPUToROCDL/memory_counter_wait_unsupported.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-fp8-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma-reduce-precision-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-ext.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-trunc-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/packed-trunc.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1200-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1250-invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane-gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane-var.mlir
M mlir/test/Conversion/AMDGPUToROCDL/permlane.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma-gfx950.mlir
M mlir/test/Conversion/AMDGPUToROCDL/sparse-mfma.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swizzle.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/swmmac-gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx1250.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx1250_invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_gfx950_invalid.mlir
M mlir/test/Conversion/AMDGPUToROCDL/transpose_load_reject.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx11.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx12.mlir
M mlir/test/Conversion/AMDGPUToROCDL/wmma-gfx1250.mlir
M mlir/test/Conversion/ArithToAMDGPU/16-bit-floats.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation-ocp.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats-ocp.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-extf.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-truncf-tensor.mlir
M mlir/test/Conversion/ArithToAMDGPU/scaling-truncf.mlir
M mlir/test/Conversion/GPUCommon/lower-global-id.mlir
M mlir/test/Conversion/GPUCommon/lower-memory-space-attrs.mlir
M mlir/test/Conversion/GPUCommon/memory-attrbution.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-attrs.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-noalias-attrs.mlir
M mlir/test/Conversion/GPUCommon/memref-arg-noalias-warning.mlir
M mlir/test/Conversion/GPUToROCDL/constant-address-space.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barrier.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-barriers-gfx12.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-hip.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-ballot.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-dialect.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-invalid-named-barrier.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-named-barrier-non-const.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-opencl.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-subgroup-id.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl.mlir
M mlir/test/Conversion/GPUToROCDL/memref.mlir
M mlir/test/Conversion/GPUToROCDL/private-func-no-c-interface.mlir
M mlir/test/Conversion/MathToROCDL/math-to-rocdl.mlir
M mlir/test/Dialect/AMDGPU/amdgpu-emulate-atomics.mlir
M mlir/test/Dialect/GPU/promote-shuffle-amdgpu-invalid.mlir
M mlir/test/Dialect/GPU/promote-shuffle-amdgpu.mlir
M mlir/test/Dialect/LLVMIR/attach-targets.mlir
A mlir/test/Dialect/LLVMIR/rocdl-attach-target-arch.mlir
M mlir/test/Integration/GPU/ROCM/gpu-lower-to-rocdl-pipeline.mlir
M mlir/test/Integration/GPU/ROCM/gpu-to-hsaco.mlir
M mlir/test/Integration/GPU/ROCM/printf.mlir
M mlir/test/Integration/GPU/ROCM/two-modules.mlir
M mlir/test/Integration/GPU/ROCM/vecadd.mlir
M mlir/test/Integration/GPU/ROCM/vector-transferops.mlir
M mlir/test/lib/Dialect/GPU/TestGpuRewrite.cpp
M mlir/unittests/Dialect/LLVMIR/ROCDLTargetInfoTest.cpp
Log Message:
-----------
[mlir][AMDGPU] Take an `arch` target ID instead of triple/chip/features
`features` was a general `-mattr` string, which needed a general feature
parser and let callers ask for arbitrary combinations we have no interest
in supporting. In practice the only things anyone sets are the wavefront
size and the xnack/sramecc settings that come off a device query.
Replace `triple`, `chip` and `features` with a single `arch` option that
names the target the way Clang does, parsed by `llvm::AMDGPU::TargetID`
rather than by hand. It accepts
- a processor, with optional target-ID modifiers: `gfx942`,
`gfx942:xnack+`, `gfx9-4-generic`;
- a triple: `amdgpu9.42-amd-amdhsa`;
- a full target ID: `amdcgn-amd-amdhsa--gfx90a:sramecc+:xnack-`, which
is what `rocminfo` prints for a device's ISA, so that output can be
pasted straight in.
Since `chipset=gfx942` becomes `arch=gfx942`, migration is a rename.
Only xnack and sramecc are target-ID features, and only on a processor
that supports switching them; this is exactly `clang::parseTargetID`'s
grammar. Wavefront size is not one of them - Clang carries it as an
ordinary `-mattr` feature - so `convert-gpu-to-rocdl` takes it as a
separate `wavesize` option, 0 meaning "whatever the architecture runs
at". The pipeline's `wave64` flag becomes `wavesize` too, which changes
its default on RDNA parts from wave64 to wave32.
`rocdl-attach-target` gains `arch` alongside the split options, which it
still needs because `#rocdl.target` feeds the TargetMachine, whose
`-mcpu` only takes a bare processor name. When `arch` is given it is
decomposed the same way the Clang driver does it: the processor becomes
the chip and the modifiers are appended to the features.
The feature bitset is unchanged as the internal representation, so
lowerings still ask `has(FEAT_...)`. `TargetInfo` also now forwards the
per-GPU numeric properties the TargetParser already exposed but it did
not - SGPR counts and granules, the VGPR granule, the LDS bank count and
the max waves per EU - along with the xnack/sramecc settings.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
Commit: c1377bd9a2b89be4cb9398330bfa681f62c0be3a
https://github.com/llvm/llvm-project/commit/c1377bd9a2b89be4cb9398330bfa681f62c0be3a
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-10 (Thu, 10 Sep 2026)
Changed paths:
M mlir/docs/ReleaseNotes.md
M mlir/include/mlir/Dialect/GPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/ROCDLTargetInfo.h
M mlir/lib/Dialect/GPU/Transforms/ROCDLAttachTarget.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLTargetInfo.cpp
M mlir/test/Dialect/LLVMIR/rocdl-attach-target-arch.mlir
M mlir/unittests/Dialect/LLVMIR/ROCDLTargetInfoTest.cpp
Log Message:
-----------
[mlir][ROCDL] Carry `arch`'s xnack/sramecc onto the module
`rocdl-attach-target` rejected a target ID that pinned xnack or sramecc,
because `#rocdl.target` feeds a TargetMachine and the backend no longer
accepts those two as subtarget features. Now that the module attributes
exist, migrate them instead of refusing: `TargetInfo` gains
`migrateArchFeaturesToModuleFlags`, which records the settings the target
ID pinned as `rocdl.xnack` / `rocdl.sramecc` on a module, and
`rocdl-attach-target` calls it on each module it attaches to.
A setting the target ID leaves open, or that the GPU does not support, is
left alone rather than written as false: an absent flag means "either",
so writing false would be a different request. That also means an
attribute already on the module survives an `arch` that says nothing
about the feature, while an `arch` that does pin it wins as the more
specific request.
Commit: 3761d4d44e728f225c26ae04d20b3fdf7a70c60b
https://github.com/llvm/llvm-project/commit/3761d4d44e728f225c26ae04d20b3fdf7a70c60b
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-10 (Thu, 10 Sep 2026)
Changed paths:
M mlir/docs/ReleaseNotes.md
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
M mlir/include/mlir/Dialect/GPU/Pipelines/Passes.h
M mlir/include/mlir/Dialect/LLVMIR/ROCDLTargetInfo.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MathToROCDL/MathToROCDL.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/EmulateAtomics.cpp
M mlir/lib/Dialect/GPU/Pipelines/GPUToROCDLPipeline.cpp
M mlir/lib/Dialect/LLVMIR/IR/ROCDLTargetInfo.cpp
A mlir/test/Conversion/ArithToAMDGPU/deprecated-chipset-alias.mlir
M mlir/test/Conversion/GPUToROCDL/gpu-to-rocdl-hip.mlir
M mlir/unittests/Dialect/LLVMIR/ROCDLTargetInfoTest.cpp
Log Message:
-----------
[mlir][AMDGPU] Keep `chipset` as a deprecated alias for `arch`
Renaming the option meant every existing invocation of these passes had
to be updated in lockstep. Accept the old spelling instead: `chipset` on
`convert-amdgpu-to-rocdl`, `convert-gpu-to-rocdl`, `convert-arith-to-amdgpu`,
`convert-math-to-rocdl` and `amdgpu-emulate-atomics`, and `chip` on
`gpu-lower-to-rocdl-pipeline`, which is what each of them was called
before the rename.
`arch` wins whenever it names a target; the alias is consulted only when
`arch` is still at the sentinel that means "no target given", so with
neither given the error still names the unusable default rather than an
empty string, and a stale alias value is reported as itself.
Commit: 1d67db78db8a303b32cc52f07a252b5ec65feaf8
https://github.com/llvm/llvm-project/commit/1d67db78db8a303b32cc52f07a252b5ec65feaf8
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2026-09-10 (Thu, 10 Sep 2026)
Changed paths:
M flang/test/Lower/OpenMP/target_cpu_features.f90
Log Message:
-----------
Update features test for flang
Compare: https://github.com/llvm/llvm-project/compare/d652eae828d1...1d67db78db8a
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