[all-commits] [llvm/llvm-project] 56d496: [RISCV] Remove TuneHasSingleElementVecFP64 has a c...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56d496fa86a8fd4be06b459c278753b4660f42d6
      https://github.com/llvm/llvm-project/commit/56d496fa86a8fd4be06b459c278753b4660f42d6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/unittests/TargetParser/RISCVTargetParserTest.cpp

  Log Message:
  -----------
  [RISCV] Remove TuneHasSingleElementVecFP64 has a configurable tune feature for sifive-x180. (#222496)

X180 is a DLEN=64 CPU with 1 vector ALU. By definition it is always
single element FP64.



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