[all-commits] [llvm/llvm-project] 19eb8b: [lldb] Expose vector registers through SBValue (#2...

[Bar Soloveychik via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 19eb8bf1a5fd01e2bca2c7112b7f393f946d67f4
      https://github.com/llvm/llvm-project/commit/19eb8bf1a5fd01e2bca2c7112b7f393f946d67f4
  Author: Bar Soloveychik <barsolo at meta.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M lldb/include/lldb/Utility/RegisterValue.h
    M lldb/source/Core/Value.cpp
    M lldb/source/Plugins/RegisterTypeBuilder/RegisterTypeBuilderClang.cpp
    M lldb/source/Plugins/RegisterTypeBuilder/RegisterTypeBuilderClang.h
    M lldb/source/Utility/RegisterValue.cpp
    M lldb/source/ValueObject/ValueObjectRegister.cpp
    M lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterVector.py
    M lldb/unittests/Target/RegisterTypeBuilderClangTest.cpp
    M lldb/unittests/Utility/RegisterValueTest.cpp

  Log Message:
  -----------
  [lldb] Expose vector registers through SBValue (#220707)

This is adding GDB remote vector register support.

- Build exact Clang types from parsed vector metadata.
- Use native Clang vectors where valid and arrays where required to
preserve exact layouts.
- Support nested, pointer, boolean, and non-power-of-two vectors.
- Expose vector lanes through `SBValue` children and expression paths.
- Handle typed vector data correctly across target byte orders.
- Add builder, SB API, layout, cache, and big-endian tests.

Example:
```
vector = frame.FindRegister("v0")
vector.GetNumChildren()                              # 4
vector.GetChildAtIndex(2).GetValue()                 # "3.5"
vector.GetValueForExpressionPath("[2]").GetValue()   # "3.5"

v = frame.FindRegister("v0")
print([v.GetChildAtIndex(i).GetValue()
       for i in range(v.GetNumChildren())])
# ['1.5', '2.5', '3.5', '4.5']
```
Structured `register read` output is added separately in patch 5.

---------

Co-authored-by: Bar Soloveychik <barsolo at fb.com>



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