[all-commits] [llvm/llvm-project] fd00fa: [ConstantTime] Use ARITH_FENCE as the combine barr...

[Akshay K via All-commits]

  Branch: refs/heads/users/wizardengineer/ct-select-core
  Home:   https://github.com/llvm/llvm-project
  Commit: fd00faf63a3688b6f073305245a2a023bc05eab8
      https://github.com/llvm/llvm-project/commit/fd00faf63a3688b6f073305245a2a023bc05eab8
  Author: AkshayK <iit.akshay at gmail.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/test/CodeGen/RISCV/ctselect-fallback-gisel.ll
    M llvm/test/CodeGen/RISCV/ctselect-fallback-scalable.ll
    M llvm/test/CodeGen/RISCV/ctselect-fallback.ll
    M llvm/test/CodeGen/X86/ctselect.ll

  Log Message:
  -----------
  [ConstantTime] Use ARITH_FENCE as the combine barrier in CT_SELECT expansion

Replace the CopyToReg/CopyFromReg vreg barrier in ExpandCTSELECT with
ISD::ARITH_FENCE. The legalizer no longer creates vregs or picks register
classes via getRegClassFor, and scalable vectors are now covered too.
Codegen tests regenerated; output stays branchless.



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