[all-commits] [llvm/llvm-project] 50ba23: [AMDGPU][GISel] Match constrained shifts across re...

[Anshil Gandhi via All-commits]

  Branch: refs/heads/users/gandhi56/globalisel/remove-redundant-and-shift
  Home:   https://github.com/llvm/llvm-project
  Commit: 50ba23b2a9dcb242ccaf5932f38a18e6135b2b99
      https://github.com/llvm/llvm-project/commit/50ba23b2a9dcb242ccaf5932f38a18e6135b2b99
  Author: Anshil Gandhi <Anshil.Gandhi at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shift-amount-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-fadd-v2-fneg-lo.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll

  Log Message:
  -----------
  [AMDGPU][GISel] Match constrained shifts across register bank copies

The constrained shift PatFrags (csh_mask_* wrapped by cshl_/csrl_/csra_)
supply GISelPredicateCode and are imported into the GlobalISel match
table, but they never fired for a divergent shift. AMDGPURegBankLegalize
places a cross-bank COPY in two positions inside the shape they match:

 - the mask constant stays in the SGPR bank, so a divergent G_AND reads
   it through a COPY and the frag's imm operand is not a G_CONSTANT;
 - a uniform G_AND feeding a divergent shift is copied to the VGPR bank,
   so the shift's amount operand is not a G_AND.

Either way GIM_CheckOpcode rejects the rule before isUnneededShiftMask
is ever consulted, and the redundant v_and_b32 survives into the output.

Set GIIgnoreCopies so the matcher emits GIM_RecordInsnIgnoreCopies for
those operands. A frag's flags only govern how its own operands are
found, so the first position needs the flag on csh_mask_* while the
second needs it on the node holding the shift; split the masked
alternative of each frag into its own record to carry it there. That
keeps the unmasked alternatives, and the fused patterns built on them,
matching exactly as before. isUnneededShiftMask also has to look through
the copy to read the constant, which getIConstantVRegVal does not do.
SelectionDAG is unaffected, as GISelFlags only feeds the GlobalISel
importer.

This complements the postlegalizer combiner rule from the previous
commit, which runs before the s16 -> s32 widening and bails on vector
types. csh_v4i32 in constrained-shift.ll is a case it cannot reach and
now drops four v_and_b32.

Add inst-select-shift-amount-mask.mir to cover both copy positions and
the rejected cases directly at instruction-select, since the combiner
otherwise removes most masks before selection runs.

Co-authored-by: Cursor <cursoragent at cursor.com>



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