[all-commits] [llvm/llvm-project] 15fa12: [TableGen][AMDGPU][RFC] Introduce register sequences

[Ivan Kosarev via All-commits]

  Branch: refs/heads/users/kosarev/registersequence-superregs-simple
  Home:   https://github.com/llvm/llvm-project
  Commit: 15fa127b7854971a2be200f9efd766458cd9e504
      https://github.com/llvm/llvm-project/commit/15fa127b7854971a2be200f9efd766458cd9e504
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/Analysis/DotMachineCFG/AMDGPU/functions.mir
    M llvm/test/Analysis/DotMachineCFG/AMDGPU/irreducible.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin-64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel-system-sgprs.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_kernel.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-abi-attribute-hints.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constant-fold-vector-op.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fence.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-tail-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/known-bits-sbfe.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/no-cse-nonlocal-convergent-instrs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-fmed3-minmax-const.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-call.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-poison.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-call.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/select-merge-values-build-vector-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
    M llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/add.ll
    M llvm/test/CodeGen/AMDGPU/add_i1.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-to-agpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.160bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.192bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.224bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.288bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.352bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.384bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.448bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
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    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-snop-padding.mir
    M llvm/test/CodeGen/AMDGPU/artificial-terminators.mir
    M llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-globalisel.ll
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
    M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
    M llvm/test/CodeGen/AMDGPU/bb-prolog-spill-during-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/block-should-not-be-in-alive-blocks.mir
    M llvm/test/CodeGen/AMDGPU/branch-folder-requires-no-phis.mir
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir
    M llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
    M llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
    M llvm/test/CodeGen/AMDGPU/buffer-store-dwordx4-vpk-mul-war-hazard-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/bug-pk-f32-imm-fold.mir
    M llvm/test/CodeGen/AMDGPU/bug-undef-spilled-agpr.mir
    M llvm/test/CodeGen/AMDGPU/build_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
    M llvm/test/CodeGen/AMDGPU/call-c-function.ll
    M llvm/test/CodeGen/AMDGPU/call-defs-mode-register.ll
    M llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/carryout-selection.ll
    M llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
    M llvm/test/CodeGen/AMDGPU/coalesce-copy-to-agpr-to-av-registers.mir
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    M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/postra-sink-update-dependency.mir
    M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
    M llvm/test/CodeGen/AMDGPU/preserve-only-inactive-lane.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
    M llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
    M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
    M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
    M llvm/test/CodeGen/AMDGPU/reduce-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/reg-coalescer-subreg-liveness.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-hoist-spill-live-range-upd.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-sgpr128-partial-def.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
    M llvm/test/CodeGen/AMDGPU/regpressure_printer.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/remat-dead-subreg.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/remat-through-copy.mir
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir
    M llvm/test/CodeGen/AMDGPU/remove-not-short-exec-branch-on-unconditional-jump.mir
    M llvm/test/CodeGen/AMDGPU/remove-register-flags.mir
    M llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-mfma-form-spill-cost-reset.ll
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-spill-joint-dom-mir.mir
    M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
    M llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.gfx11plus.ll
    M llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
    M llvm/test/CodeGen/AMDGPU/sched-barrier-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-dead-def-join.mir
    M llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
    M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_copies.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_cost.mir
    M llvm/test/CodeGen/AMDGPU/sched_mfma_rewrite_diff_types.mir
    M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/schedule-ilp.mir
    M llvm/test/CodeGen/AMDGPU/schedule-pending-queue.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-ilp-metric-spills.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure-no-unclustered-regions.mir
    M llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-cndmask-wave32.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-combine-sel.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-scavenge-fi-stack-id.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-unhandled.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/shrink-v-cmp-wave32-dead-vcc-lo.mir
    M llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir
    M llvm/test/CodeGen/AMDGPU/si-annotate-nested-control-flows.ll
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-copy-kills.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
    M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow-preserve-dom-tree.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.ll
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-cycle-header.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-body.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-initial-insert-in-latch.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-multi-entry-cycle.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-wwm-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs-preserve-rci.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
    M llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwwmregs-dbg-noreg.mir
    M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
    M llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-before-exec.mir
    M llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
    M llvm/test/CodeGen/AMDGPU/spill-partial-csr-sgpr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll
    M llvm/test/CodeGen/AMDGPU/spill-wait.mir
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/spill_kill_v16.mir
    M llvm/test/CodeGen/AMDGPU/spillv16.mir
    M llvm/test/CodeGen/AMDGPU/split-liverange-overlapping-copies.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-do-not-undo-subclass-split-with-remat.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/splitkit.mir
    M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/stack-realign.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
    M llvm/test/CodeGen/AMDGPU/statepoint-asm-printer.mir
    M llvm/test/CodeGen/AMDGPU/statepoint-insert-waitcnts.mir
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/stress-regalloc-limits-regalloc.mir
    M llvm/test/CodeGen/AMDGPU/sub_i1.ll
    M llvm/test/CodeGen/AMDGPU/subreg-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
    M llvm/test/CodeGen/AMDGPU/subvector-test.mir
    M llvm/test/CodeGen/AMDGPU/swdev282079.mir
    M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-epilog-phi.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-gen-structure.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-loop-carried-mem.mir
    M llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-unpipeline-compare.mir
    M llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/track-spilled-vgpr-liveness.mir
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
    M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
    M llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
    M llvm/test/CodeGen/AMDGPU/use_restore_frame_reg.mir
    M llvm/test/CodeGen/AMDGPU/v-cmp-cse-across-loop.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/valu-i1.ll
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard-true16.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
    M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
    M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
    M llvm/test/CodeGen/AMDGPU/verify-image.mir
    M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
    M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-dead-frame-in-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value-list.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/vgpr_constant64_to_sgpr.mir
    M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vopc-remat.mir
    M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt-atomic-rmw-optimization.ll
    M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-buffer-inv.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-func-global-inv.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-call-inreg-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
    M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/wqm.mir
    M llvm/test/CodeGen/AMDGPU/wwm-regalloc-partial-pool.mir
    M llvm/test/CodeGen/AMDGPU/wwm-regalloc-preallocation-guard.mir
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/wwm-spill-superclass-pseudo.mir
    M llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
    M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
    M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
    M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg-debug.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
    M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
    M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-class-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-invalid-register-name-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-mfi.ll
    M llvm/test/CodeGen/MIR/AMDGPU/preload-kernarg-stack-type-error.mir
    M llvm/test/CodeGen/MIR/AMDGPU/spill-phys-vgprs.mir
    M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
    M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
    M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
    M llvm/test/MC/AMDGPU/buffer-op-lds-operand.s
    M llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
    M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
    M llvm/test/MachineVerifier/AMDGPU/hazard-gfx1250-flat-src-hi.mir
    M llvm/test/MachineVerifier/AMDGPU/issue98474-missing-def-liveout-physical-subregister.mir
    M llvm/test/MachineVerifier/AMDGPU/unsupported-subreg-index-aligned-vgpr-check.mir
    M llvm/test/MachineVerifier/AMDGPU/verifier-pseudo-terminators.mir
    A llvm/test/TableGen/RegisterSequence.td
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
    M llvm/test/tools/llvm-reduce/mir/preserve-machine-function-info-amdgpu.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-defs.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-uses.mir
    M llvm/unittests/MIR/MachineMetadata.cpp
    M llvm/unittests/Target/AMDGPU/InstSizes.cpp
    M llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Introduce register sequences

The overwhelming majority of AMDGPU's registers are synthesized
tuples, and all of them are sequences of adjacent registers of
certain widths. We currently have no adequate representation of
them in TableGen: every such tuple is emitted as a descriptor
carrying its own name string and its own sub- and super-register
lists, so the generated register tables run to well over a
hundred megabytes for this one target. The names spell out every
member, so a four-register tuple is SGPR0_SGPR1_SGPR2_SGPR3. The
representation has no notion of register tuple widths, so we
implement the mapping between widths and register classes by
hand.

Representing tuples as a first register and a width would address
these issues. What stands in the way is that TableGen has no
notion of one register following another in a sequence.

This patch adds such a notion using RegisterSequence instances:

  def : RegisterSequence<[R0, R1, R2, R3]>;

Note that it is a relationship between the registers themselves
and not register classes. A register class may order or omit its
members freely without affecting the sequence.

This patch only uses sequences for naming. Where a tuple is made
of registers that follow one another, we name it after the first
of them and the total width, so SGPR0_128 instead of
SGPR0_SGPR1_SGPR2_SGPR3. Other tuples keep their longer names.
These names are code identifiers; the assembly names come from
the AsmName field, which we do not touch.

The patches that follow use the same relationship to describe
whole blocks of such tuples at once, so that the registers of a
block need no individual code names, no sub- or super-register
lists, no register units and finally no descriptors of their own.
The last commits declare the VGPRs, AGPRs and TTMPs as sequences
as well; only the SGPRs are declared here.

The bulk of the diff is the resulting test updates, a mechanical
rename of the affected register names.

Targets that declare no sequences are not affected. For AMDGPU,
all the register numbers stay as they were, and the only thing
that changes in the register descriptors is their names.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 50797004383d8b01a237e7f92b0092254938a332
      https://github.com/llvm/llvm-project/commit/50797004383d8b01a237e7f92b0092254938a332
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegister.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Reserve enum blocks for register sequences

The previous patch renamed tuples after their first register and
their width, but each one still gets its own enumerator. That is
wasteful, because the enumerators are very regular. All the
tuples that one RegisterTuples def builds from one sequence come
out next to each other in the enum, start at the beginning of the
sequence, and are evenly spaced along it. So we can just say
where the first one is and how many there are.

That is what this patch does: such a group of registers becomes a
block, named after the sequence and the width of its registers,
and a single enumerator stands for the whole group:

  SGPR_64_SEQ = 7683, // 53 registers.

To get at the registers, ask the block for the one that starts at
a given member:

  constexpr MCRegisterSequenceBlock SGPR_64 = {SGPR_64_SEQ, 53, 2};

AMDGPU::SGPR_64(30) is then what used to be called SGPR30_64. It
has the same two numbers in it, so it is easy to see which
register is meant. In the generated tables, where these registers
used to appear by name, they now appear as an offset from the
enumerator of their block, such as AMDGPU::SGPR_128_SEQ + 17.

A register goes in a block only where what we know about it can
be computed from the description of the block and its position in
it. In this patch that is just the register number, and to
compute it we need the registers to come from the same
RegisterTuples def, to begin at the first member of the sequence
and to be evenly spaced along it. We go over the registers in
enum order and end the block at the any register that does not
meet this. Later patches compute more about a register this way
and require more of it accordingly. A RegisterTuples def may well
hold registers that do not follow one another, and those get no
block and keep their old names. The eight VCCTuple registers,
which straddle the SGPR and VCC boundary, are an example of this.

NUM_TARGET_REGS is now given its value explicitly rather than
left to follow the enumerator before it, because that enumerator
may be a block containing many registers. Nothing depends on
NUM_TARGET_REGS while the last register of the enum has an
enumerator of its own, which is the case here, but a later patch
in this series declares the VGPRs as a sequence and makes the
last register part of a block. AsmMatcherEmitter sizes an array
by NUM_TARGET_REGS and fills it with one element per register, so
the generated matcher would fail to compile.

For AMDGPU this commit turns 347 SGPR enumerators into 13 blocks.
Register numbers and their code names returned by TRI->getName()
for debug purposes do not change.

Targets that declare no sequences are not affected.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: a8870cd4bc7b764b8aaf5d15f184ca90639c4dd6
      https://github.com/llvm/llvm-project/commit/a8870cd4bc7b764b8aaf5d15f184ca90639c4dd6
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Compute subregisters of block registers

TableGen emits a descriptor in MCRegisterDesc for every register,
and the SubRegs field of that descriptor is an offset into a
table of sub-register lists. Every register has a list of its own
there, and in a target with many register tuples that table is
one of the larger parts of the generated register information: in
AMDGPU it holds 105,440 entries.

The previous patches gathered registers into sequence blocks. A
block is a group of registers defined by one RegisterTuples def,
numbered one after another, each spanning members of one declared
sequence, and starting at members with a fixed spacing between
them. A block has one enumerator, standing for the block itself
rather than for any one of its registers, and a register of the
block is referred to as that enumerator plus its position in it.

Their sub-registers follow from their position too. In AMDGPU's
SGPR_128 block the first register is SGPR0_SGPR1_SGPR2_SGPR3 and
the second is SGPR4_SGPR5_SGPR6_SGPR7. Where the first has SGPR0
the second has SGPR4, four register numbers away; where the first
has the 64-bit SGPR0_SGPR1 the second has SGPR4_SGPR5, two
register numbers away, the 64-bit registers being themselves a
block with one register for every two SGPRs. Each sub-register
has a slope of its own, and the same slope takes the second
register's sub-registers to the third's.

When identifying blocks, we require that this holds for all its
members: every register has as many sub-registers as the first,
under the same sub-register indices, and the sub-registers of the
register at position P are those of the first register with P
times the corresponding slope added. The tables therefore hold
the sub-register list of the first register of each block and its
slopes, one per sub-register, and the registers after the first
are computed from that in MCSubRegIterator, which already exists
as _the_ interface to sub-registers.

In AMDGPU all so-far declared sequential registers form blocks,
so llvm/test/TableGen/RegisterSequence.td covers the case of a
register whose sub-registers do not follow the slopes: it must
end the block before itself, leaving the registers ahead of it in
a block, rather than costing them the block entirely.

The 13 AMDGPU SGPR blocks hold 347 registers between them, and
all but the first of each, 334 of them, no longer need a
sub-register list. AMDGPURegDiffLists goes from 105,440 entries
to 92,380, about 26 KB, the slopes counted in the new total. The
MCRegisterDesc descriptors remain: a descriptor with a computed
field still occupies a descriptor, and removing descriptors waits
until the remaining fields are computed the same way.

Co-Authored-By: Claude Sonnet 4.6 <noreply at anthropic.com>


  Commit: 27dc57acc3f85ef35595af48118b0524f8f46278
      https://github.com/llvm/llvm-project/commit/27dc57acc3f85ef35595af48118b0524f8f46278
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Compute super-registers of block registers

Every register carries a list of its super-registers in the
SuperRegs field of its MCRegisterDesc. The registers of a
sequence block do not need such lists: the block can describe the
super-registers of all its registers at once.

The registers of a block cover the same number of sequence
members each and begin an equal number of members apart. So do
the super-registers of any one width. Moving from one register of
the block to the next therefore moves a fixed number of registers
along the super-registers of that width, and two numbers describe
them all: where the first one that covers a register of the block
begins, and how far apart they follow one another. We call that a
series.

A block stores one series per width above its own. To list the
super-registers of one of its registers, we walk the series and
work out, for each, which of its registers covers that particular
register.

The lists this produces differ in length. Registers near the
start and the end of the sequence have fewer super-registers than
those in the middle, there being nothing beyond the ends for a
wider register to reach into. This needs no special handling: a
series yields nothing when the answer would fall outside it, and
the register moves on to the next series. One list of series
serves the whole block, and the registers at the ends simply get
fewer answers out of it.

A super-register may belong to no block, and then it is a series
on its own. It does not move as we go along the block, so its
spacing is zero and it answers for a run of the block's
registers. AMDGPU has eight such registers, the VCCTuple defs in
SIRegisterInfo.td: SGPR76_1024, SGPR92_512 and the rest, which
cover the last SGPRs together with VCC_LO and VCC_HI. The regular
generator cannot produce them, because the next register of each
width would run past the end of the sequence. They are
super-registers of 81 of the 347 registers in the SGPR blocks.

We check the result against the super-registers each register of
the block really has, and cut the block short at the first
register where the two disagree. This is what already happens
when a register's sub-registers depart from the pattern. Such a
register keeps a description of its own, as every register
outside a block does. The check runs after the blocks are formed
rather than while they are being formed, because a super-register
of a block register may itself belong to a block that does not
exist yet. Cutting a block short can leave a register outside
every block, so we repeat the pass until nothing changes.

This patch changes the order of super-registers. A block can hold
registers that begin at differently aligned members, and their
super-registers interleave differently for each of them, so no
single order over the series reproduces the old order for every
register of the block. The order has only ever guaranteed that a
register comes before its super-registers, and listing the series
narrowest first keeps to that, because a super-register holds
more register units than the register it covers.

Dropping the super-register lists of block registers takes
AMDGPURegDiffLists from 94304 to 93224 entries, about 2 KB. The
series come to 282 entries. The MCRegisterDesc descriptors stay
for now, as they did when the sub-registers moved out: a
descriptor with one computed field still takes up a descriptor.
Removing them waits until the remaining fields are computed the
same way.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 664894c7eadfc5e51dd1a97cb5895eca67b43011
      https://github.com/llvm/llvm-project/commit/664894c7eadfc5e51dd1a97cb5895eca67b43011
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Compute register units of block registers

The RegUnits field of an MCRegisterDesc holds the register units
of a register as a difflist. All registers of a sequence block
can share a single difflist.

The registers of a block differ only in where they start along
the sequence, and their register units are laid out the same way.
Each register holds as many units as the first one does, at the
same distances from one another, and the whole run of units sits
a fixed distance further along for each register of the block.
So a register of a block reads the distances stored for the first
register and applies them to its own first unit, which is the
first unit of the first register moved along by that fixed
distance. The block stores the distance.

This is the same approach we took for sub-registers, and a
simpler one. Sub-registers need a distance each, because a
sub-register that belongs to a block moves by fewer register
numbers than the registers that span it. Register units all move
together, so one distance covers them.

We check the units of every register of the block and cut the
block short where they stop matching, as we already do for
sub-registers and super-registers. The units need not be
consecutive, only laid out the same way in each register. This is
therefore weaker than the RegistersAreIntervals property, which
AMDGPU does not set here upstream.

This change does not reduce AMDGPURegDiffLists. A difflist
records distances rather than unit numbers, so we already emitted
the same difflist for every register of a block, and the table
already stored it once. We emitted thirteen difflists for the 347
registers of the SGPR blocks before, and we emit the same
thirteen now.

This is another step towards eliminating the descriptors of block
registers. The RegUnits field is now the same for every register
of a block, and once every field is the same, one descriptor can
serve the whole block and we can drop the rest.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 9d4372bb4ccda3610a5ba45aca20792464b48f1b
      https://github.com/llvm/llvm-project/commit/9d4372bb4ccda3610a5ba45aca20792464b48f1b
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Stop emitting register units of block registers

The previous patch made the registers of a sequence block compute
their register units from the block, but the emitter still writes
those units out. Nothing reads them, so stop writing them. For
every register of a block after the first, the RegUnits field is
now zero, in the same way that the SubRegs and SuperRegs fields
are already zero.

This is another step towards eliminating the descriptors of block
registers. The RegUnits field is now the same for every register
of a block except the first, and once every field is the same,
one descriptor can serve the whole block and we can drop the
rest.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: db5aa2e1cc22b5772889bde6fc7b1e33d555d7f7
      https://github.com/llvm/llvm-project/commit/db5aa2e1cc22b5772889bde6fc7b1e33d555d7f7
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
    M llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.h
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
    M llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
    M llvm/tools/llvm-exegesis/lib/LlvmState.cpp
    M llvm/tools/llvm-exegesis/lib/LlvmState.h
    M llvm/tools/llvm-objdump/SourcePrinter.cpp
    M llvm/unittests/CodeGen/InstrRefLDVTest.cpp
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Stop emitting names for block registers

The block stores one name, and getName() builds the register name
from it and the member the register starts at: SGPR_128 and
member 4 give SGPR4_128. The Name field of a block register is
now the empty string.

getName() therefore returns a std::string rather than a const
char *. No caller keeps the result: each one prints it or appends
it to something and is done. Two callers hand out a StringRef
into the name, and they now hold the string in a local variable
for the reference to point at. The heaviest caller is the MIR
parser, which asks every register for its name to build the map
it looks names up in. It builds that map once and copies the
names into it anyway.

This is another step towards eliminating the descriptors of block
registers. The Name field is now the same for every register of a
block, and once every field is the same, one descriptor can serve
the whole block and we can drop the rest.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: c100614584e65e16dbbf02ea64d008b4268fc521
      https://github.com/llvm/llvm-project/commit/c100614584e65e16dbbf02ea64d008b4268fc521
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/lib/DWARFCFIChecker/DWARFCFIAnalysis.cpp
    M llvm/lib/MC/MCRegisterInfo.cpp
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/Common/CodeGenRegisters.cpp
    M llvm/utils/TableGen/Common/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Share one descriptor between the registers of a block

The previous patches moved the sub-registers, the super-registers,
the register units and the name of a block register into the
block. What remains in an MCRegisterDesc is the same for every
register of a block: the sub-register indices, the lane masks of
the register units, and the constant and artificial flags. None
of these tells one register of a block from another anymore.

So a block has one descriptor, shared by all its registers. It
sits at the entry of the first register, because Desc is still
indexed by register number. get() returns it for every register
of the block, and callers read it as before, without knowing
about blocks.

The descriptors of the other registers of a block are now empty.
We still emit them, because MCRegisterInfo::Desc is indexed by
register number and dropping a descriptor would break that
indexing. The next patch changes how we address descriptors and
drops them.

A block may only hold registers that agree on what the shared
descriptor holds. We check the constant and artificial
flags while forming the block, and cut it short at the first
register that disagrees. Lane masks are not computed until well
after we form the blocks, so we check those in a later pass.

This patch also removes operator[], which had no callers of its
own and did the same as get(). Both were public, and nothing
outside MCRegisterInfo reads a descriptor, so get() is private
now. Callers reach a register's description through the methods
that know where each part of it lives.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 0e08f6b6a31d6c2f067ac980c967fb18d70314f7
      https://github.com/llvm/llvm-project/commit/0e08f6b6a31d6c2f067ac980c967fb18d70314f7
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/include/llvm/MC/MCRegisterInfo.h
    M llvm/test/TableGen/RegisterSequence.td
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Drop the descriptors of block registers

The previous patch gave all registers of a sequence block one
shared MCRegisterDesc, stored at the entry of the first register.
The entries of the other registers stayed in place, zeroed out,
because MCRegisterInfo::Desc is indexed by register number and
removing an entry would shift every register after it. This patch
removes them.

We add a table, RegDescIndexes, indexed by register number, that
says where to find what describes each register. If the low bit
of an entry is set, the register belongs to a sequence block, and
the rest of the entry is the index of that block in SeqBlocks. If
the low bit is clear, the register has a descriptor of its own,
and the rest of the entry is its index in Desc. MCSeqBlockDesc
gains a DescIndex field that gives the Desc index of the shared
descriptor, which we need because Desc is no longer indexed by
register number.

get() now reads the register's entry in RegDescIndexes and
follows it to the descriptor, and getSeqBlockOf() reads the same
entry and tests its low bit. Neither searches. They replace the
binary search over SeqBlocks that the previous patch had to
introduce, which ran on every read of every field of every
register descriptor.

The descriptor of a block register now describes the block rather
than any one of its registers. TableGen emits no descriptors for
the registers of a block.

For AMDGPU, AMDGPURegDesc goes from 21267 to 20933 descriptors,
saving 8,016 bytes, while RegDescIndexes costs 42,534 bytes. At
this point in the series that is a net loss of 34.5KB, because we
have declared only the SGPRs as a sequence so far. The last three
patches declare the other three register files, which drops
16,749 descriptors, about 402KB, and the table pays for itself
many times over.

Cost of one get() call, measured against the code from before
this series introduced blocks:

                           before   binary search   this patch
  all registers            1.25ns      4.53ns          1.60ns
  registers of a block     1.25ns      4.41ns          1.26ns

And with all four register files declared as sequences, where the
binary search has 50 blocks to search rather than 13:

  all registers            1.87ns      8.26ns          2.00ns
  registers of a block     1.87ns      9.42ns          1.25ns

A register that belongs to no block needs no special handling,
even when it sits between two blocks. That happens when we cut a
block short. Such a register simply has a descriptor of its own,
like any register outside a block. AMDGPU does not have this
case, so the RegisterSequence.td test covers it.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: a1fca93be461cd485c51a478c08c2df0cf91ae8c
      https://github.com/llvm/llvm-project/commit/a1fca93be461cd485c51a478c08c2df0cf91ae8c
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-to-ptradd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fold-binop-into-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-s64-s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
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    M llvm/test/CodeGen/AMDGPU/pei-vgpr-block-spill-csr.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
    M llvm/test/CodeGen/AMDGPU/postra-bundle-vimage-vsample-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink-livein-subrange.mir
    M llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir
    M llvm/test/CodeGen/AMDGPU/pr51516.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir
    M llvm/test/CodeGen/AMDGPU/readlane_exec0.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fail-unsatisfiable-overlapping-tuple-hints.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-fast-dont-drop-subreg-index-issue61134.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
    M llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-dbg-loc.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12-dvgpr.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs-gfx12.mir
    M llvm/test/CodeGen/AMDGPU/release-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/rem_i128.ll
    M llvm/test/CodeGen/AMDGPU/remat-physreg-copy-subreg-extract-already-live-at-def-issue120970.mir
    M llvm/test/CodeGen/AMDGPU/remat-smrd.mir
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-insert-extract.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-subreg-src2-chain.mir
    M llvm/test/CodeGen/AMDGPU/sad.ll
    M llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll
    M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/sched-dynamic-vgpr-blocks.mir
    M llvm/test/CodeGen/AMDGPU/sched-image-sample-post-RA.mir
    M llvm/test/CodeGen/AMDGPU/sched.group.classification.mir
    M llvm/test/CodeGen/AMDGPU/schedmodel-dummywrite.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-latency.mir
    M llvm/test/CodeGen/AMDGPU/schedule-physregdeps.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
    M llvm/test/CodeGen/AMDGPU/sdwa-vop2-64bit.mir
    M llvm/test/CodeGen/AMDGPU/select-undef.ll
    M llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/shrink-carry.mir
    M llvm/test/CodeGen/AMDGPU/shrink-fma-f64.mir
    M llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies-av-constrain.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-agprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-subreg-imm.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/si-insert-hard-clauses-no-nesting.mir
    M llvm/test/CodeGen/AMDGPU/si-optimize-vgpr-live-range-dbg-instr.ll
    M llvm/test/CodeGen/AMDGPU/sibling-call.ll
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/smfmac_alloc_failure_no_agpr_O0.ll
    M llvm/test/CodeGen/AMDGPU/soft-waitcnt-deletion.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
    M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/spill-wait.mir
    M llvm/test/CodeGen/AMDGPU/spill192.mir
    M llvm/test/CodeGen/AMDGPU/spill224.mir
    M llvm/test/CodeGen/AMDGPU/spill288.mir
    M llvm/test/CodeGen/AMDGPU/spill320.mir
    M llvm/test/CodeGen/AMDGPU/spill352.mir
    M llvm/test/CodeGen/AMDGPU/spill384.mir
    M llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
    M llvm/test/CodeGen/AMDGPU/srem.ll
    M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
    M llvm/test/CodeGen/AMDGPU/swdev502267-use-after-free-last-chance-recoloring-alloc-succeeds.mir
    M llvm/test/CodeGen/AMDGPU/syncscopes.ll
    M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
    M llvm/test/CodeGen/AMDGPU/tied-op-for-wwm-scratch-reg-spill-restore.mir
    M llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
    M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
    M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b16.mir
    M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
    M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard-attrs.mir
    M llvm/test/CodeGen/AMDGPU/valu-read-sgpr-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
    M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
    M llvm/test/CodeGen/AMDGPU/verifier-sdwa-cvt.mir
    M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
    M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/verify-image.mir
    M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-blocks-funcinfo.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
    M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
    M llvm/test/CodeGen/AMDGPU/vopd-combine-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
    M llvm/test/CodeGen/AMDGPU/vopd-gfx12-f64-relaxed.mir
    M llvm/test/CodeGen/AMDGPU/wait-before-stores-with-scope_sys.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
    M llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-buffer-inv.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-gfx1250.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-kmcnt-scc-different-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-prefetch-flushed.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-ds-store-barrier.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-opt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-multiple-funcs.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-no-redundant.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-out-order.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-sample-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-wcg-attributes.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt.mir
    M llvm/test/CodeGen/AMDGPU/waterfall-call-target-av-register-failure.ll
    M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/whole-wave-functions-pei.mir
    M llvm/test/CodeGen/AMDGPU/wmma-coexecution-valu-hazards.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1250-w32.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx1251-w32.mir
    M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
    M llvm/test/CodeGen/AMDGPU/wmma-nop-hoisting.mir
    M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/AMDGPU/xor.ll
    M llvm/test/CodeGen/MIR/AMDGPU/addrspacecast-nonnull.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
    M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi-def.mir
    M llvm/test/CodeGen/MIR/AMDGPU/ptradd-flags.mir
    M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
    M llvm/test/MC/AMDGPU/buffer-op-swz-operand.s
    M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir
    M llvm/test/MachineVerifier/AMDGPU/issue98474-missing-def-liveout-physical-subregister.mir
    M llvm/test/MachineVerifier/AMDGPU/lit64.mir
    M llvm/test/MachineVerifier/AMDGPU/register-killed-inside-loop.mir
    M llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir
    M llvm/test/MachineVerifier/AMDGPU/test_g_incompatible_range.mir
    M llvm/test/MachineVerifier/AMDGPU/unsupported-unaligned-vgpr-check-vsrc-operand.mir
    M llvm/test/MachineVerifier/AMDGPU/verifier-copyLanemask-invalid-lanemask.mir
    M llvm/test/MachineVerifier/AMDGPU/verifier-ec-subreg-liveness.mir
    M llvm/test/MachineVerifier/AMDGPU/verify-reg-sequence.mir
    M llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-masks.mir
    M llvm/test/tools/llvm-reduce/mir/reduce-register-uses-generic.mir
    M llvm/test/tools/llvm-reduce/mir/tracks-reg-liveness.mir
    M llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp
    M llvm/unittests/Target/AMDGPU/LiveRegUnits.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Declare the VGPR register sequence

The SGPRs have been declared as a register sequence since the
start of this series, and the machinery that turns that into
savings is now in place. Declare the VGPRs the same way. This
needs no code changes, only the declaration: every VGPR tuple
width forms a full-length block.

The number of sequence blocks goes from 13 to 26, and they now
cover 13,547 of AMDGPU's 21,267 registers. Comparing the
generated tables before and after:

  MCRegisterDesc descriptors  20,933 ->  7,746   (-63.0%)
  RegDiffLists cells          93,224 -> 66,376   (-28.8%)

In bytes, for the three tables that change:

  MCRegisterDesc          502,392 -> 185,904
  RegDescIndexes           42,534 ->  42,534
  RegDiffLists            186,448 -> 132,752
  total                   731,374 -> 361,190   (-50.6%)

This is also what makes RegDescIndexes worth having. It covers
every register, whether or not the register belongs to a block,
so with only the SGPRs declared it cost more than the descriptors
it let us drop. With the VGPRs declared we save 362KB.

The generated files shrink as well. AMDGPUGenRegisterInfoEnums.inc
goes from 1.6MB to 465KB, and AMDGPUGenRegisterInfoMCDesc.inc
from 35.1MB to 24.3MB.

Most of this patch is test updates. We now name VGPR tuples after
their first register and their width, so we print and parse
$vgpr0_vgpr1 as $vgpr0_64 and $vgpr0_vgpr1_vgpr2_vgpr3 as
$vgpr0_128. The SGPR tuples went through the same rename at the
start of this series. Tuples over registers that do not follow
one another keep their old names, because they form no block.

This is also the point at which the last register of the enum
becomes part of a block, which is why we give NUM_TARGET_REGS its
value explicitly rather than let it follow the enumerator before
it. See the patch that reserves the enum blocks.

Register numbers do not change, and neither does anything else
about the registers. The two patches that follow declare the
AGPRs and the TTMPs.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 94fa1a1297cf46eea87675d45b3cd0d1084a74d1
      https://github.com/llvm/llvm-project/commit/94fa1a1297cf46eea87675d45b3cd0d1084a74d1
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx942.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-waterfall-agpr.mir
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomic-cmpxchg.ll
    M llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-spill-copy.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
    M llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/av-spill-expansion-with-machine-cp.mir
    M llvm/test/CodeGen/AMDGPU/av-split-dead-valno-crash.ll
    M llvm/test/CodeGen/AMDGPU/av_movimm_pseudo_expansion.mir
    M llvm/test/CodeGen/AMDGPU/bad-agpr-vgpr-regalloc-priority.mir
    M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir
    M llvm/test/CodeGen/AMDGPU/copy_phys_vgpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir
    M llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
    M llvm/test/CodeGen/AMDGPU/inflate-av-remat-imm.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-agpr-negative-tests.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av-with-load-source.mir
    M llvm/test/CodeGen/AMDGPU/inflate-reg-class-vgpr-mfma-to-av.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx90a.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir
    M llvm/test/CodeGen/AMDGPU/mai-hazards.mir
    M llvm/test/CodeGen/AMDGPU/mcp-aligned-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
    M llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
    M llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
    M llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-failure-overlapping-insert-assert.mir
    M llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir
    M llvm/test/CodeGen/AMDGPU/remaining-virtual-register-operands.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-copy-from.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-vgpr-mfma-to-agpr-phi.ll
    M llvm/test/CodeGen/AMDGPU/sched-prefer-non-mfma.mir
    M llvm/test/CodeGen/AMDGPU/si-fold-operands-agpr-copy-reg-sequence.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
    M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-restore-partial-copy.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/unpack-non-coissue-insts-post-ra-scheduler.mir
    M llvm/test/CodeGen/AMDGPU/vector-spill-restore-to-other-vector-type.mir
    M llvm/test/CodeGen/AMDGPU/verify-ds-gws-align.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
    M llvm/test/MachineVerifier/AMDGPU/fix-illegal-vector-copies.mir

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Declare the AGPR register sequence

Same as the previous patch, for the AGPRs. Again this needs no
code changes, only the declaration, and again every AGPR tuple
width forms a full-length block.

The number of sequence blocks goes from 26 to 39, and they now
cover 16,763 of AMDGPU's 21,267 registers. Comparing the generated
tables before and after:

  MCRegisterDesc descriptors   7,746 ->  4,543   (-41.4%)
  RegDiffLists cells          66,376 -> 39,192   (-41.0%)

In bytes, for the three tables that change:

  MCRegisterDesc          185,904 -> 109,032
  RegDescIndexes           42,534 ->  42,534
  RegDiffLists            132,752 ->  78,384
  total                   361,190 -> 229,950   (-36.3%)

Taken with the patch before it, the three tables now come to
229,950 bytes where they came to 731,374 with only the SGPRs
declared, a reduction of 69%.

AMDGPUGenRegisterInfoEnums.inc goes from 465KB to 205KB.

The test updates are the same rename as for the VGPRs, with
$agpr0_agpr1 becoming $agpr0_64 and so on, and there are far
fewer of them: 56 files against 777. Tuples over registers that
do not follow one another keep their old names, because they form
no block.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


  Commit: 0873fabedc37acfa210a852dc04ac1b3e9ffa4a9
      https://github.com/llvm/llvm-project/commit/0873fabedc37acfa210a852dc04ac1b3e9ffa4a9
  Author: Ivan Kosarev <ivan.kosarev at amd.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/test/CodeGen/AMDGPU/resource-usage-crash-unhandled-reg.mir

  Log Message:
  -----------
  [TableGen][AMDGPU][RFC] Declare the TTMP register sequence

The last of the four register pools. Eleven of the twelve TTMP
tuple widths form blocks. The twelfth does not: a 512-bit tuple
spans sixteen TTMPs at a step of four, and with only sixteen
TTMPs in the pool there is just one place such a tuple fits, so
TTMP_512Regs produces a single register. One register is no run,
so it forms no block and stays an ordinary register named
TTMP0_512, like any register outside a block.

Unlike the VGPRs and AGPRs, this needs code changes. We name TTMP
tuples from hand-written C++, and a register of a block has no
enumerator of its own. Its value is still available, because the
block accessor is constexpr and works anywhere a constant does,
including in a case label. So the call sites now name the
register by its block and the member it starts at, TTMP_64(4)
rather than TTMP4_TTMP5, in the same way as SGPR_64(104) in
AMDGPUAsmParser.cpp.

The awkward one is MAP_REG2REG in AMDGPUBaseInfo.cpp, which maps
a register to its subtarget variant and back. It builds the
variant names by pasting _vi and _gfx9plus onto the register
name, and we cannot paste onto a block accessor. The variants
belong to no block and keep their long names, so we have to give
the case label and the pasted name separately. We add a macro
that takes the block and the member for the case label, and the
old name for the pasting.

TTMP0_512 needs one more macro variant of its own. It is the only
case where the register and its subtarget variants share no
common stem: we name the register after its width, while the
variants are still named after the registers they span.

The reservation loop in SIRegisterInfo.cpp no longer spells out
the number of TTMP pairs or the distance between them, and takes
both from the block instead.

The savings are small, there being only sixteen TTMPs: 25
descriptors and 1,844 bytes across the three tables. Taken with
the whole series, the tables now come to 228,106 bytes where they
came to 725,778 before any of this, a reduction of 69%, and
AMDGPUGenRegisterInfoEnums.inc is 87% smaller.

Only one test needed updating, against 777 for the VGPRs and 56
for the AGPRs.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>


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