[all-commits] [llvm/llvm-project] 7fe363: [RISCV] Fix infinite DAGCombine loop with SETCC an...

[AZero13 via All-commits]

  Branch: refs/heads/release/23.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 7fe36371c71bb6bef3361c4f7ef081fd2c913f16
      https://github.com/llvm/llvm-project/commit/7fe36371c71bb6bef3361c4f7ef081fd2c913f16
  Author: AZero13 <gfunni234 at gmail.com>
  Date:   2026-09-10 (Thu, 10 Sep 2026)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll

  Log Message:
  -----------
  [RISCV] Fix infinite DAGCombine loop with SETCC and SIGN_EXTEND_INREG (#221593)

We generalized (X & -(1 << C1) & 0xffffffff) == C2 << C1 using `sraiw`.
The combine generates a `SIGN_EXTEND_INREG` when simplifying.

However, when C1 is 0 and the sign bit (bit 31) of X is already known to
be zero, `DAGCombiner` sees that `SIGN_EXTEND_INREG` is semantically
equivalent to `AND X, 0xFFFFFFFF` (zext). Because `DAGCombiner`
considers `AND` to be more canonical than `SIGN_EXTEND_INREG` in this
context, it immediately reverts the node back to `AND`.

This caused an infinite DAGCombine loop. This patch disables the folding
when the C1 is zero. That case is covered by a later combine that already
checks if bit 31 is known to be zero.

Fixes: https://github.com/llvm/llvm-project/issues/221521
(cherry picked from commit f9a8dec9496fea7c55f591a66a64dbcdc085fc2d)



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