[all-commits] [llvm/llvm-project] 4bd42a: [InstCombine] restrict InstCombineNegator for sub(...

[zhijian lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4bd42ad3ade67d5c1498081df08cab4090a32551
      https://github.com/llvm/llvm-project/commit/4bd42ad3ade67d5c1498081df08cab4090a32551
  Author: zhijian lin <zhijian at ca.ibm.com>
  Date:   2026-09-09 (Wed, 09 Sep 2026)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
    M llvm/test/Transforms/InstCombine/negated-bitmask.ll

  Log Message:
  -----------
  [InstCombine] restrict InstCombineNegator for sub(y,and(lshr(x,C),1)) (#222075)

For the general sub(y,and(lshr(x,C),1)) case the rewrite replaces one
2-instructions
sequence with another without reducing instruction count, and the
resulting shl/ashr form prevents later target-specific combines (e.g.
on PowerPC the original lshr+and maps to a single rldicl, while the
shl+ashr form requires sldi+sradi).
in the patch, Only applies when this is a true negation (LHS is zero).
sub(0,and(lshr(x,C),1)) --> add(ashr(shl(x,(BW-1)-C),BW-1),0)



To unsubscribe from these emails, change your notification settings at https://github.com/llvm/llvm-project/settings/notifications