[all-commits] [llvm/llvm-project] 6afc07: [X86][ACEV1] Address review comments

[Ganesh via All-commits]

  Branch: refs/heads/users/ganeshgit/X86ACEV1
  Home:   https://github.com/llvm/llvm-project
  Commit: 6afc0729617a360cefda81c536a4e798c25a751a
      https://github.com/llvm/llvm-project/commit/6afc0729617a360cefda81c536a4e798c25a751a
  Author: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian at amd.com>
  Date:   2026-09-09 (Wed, 09 Sep 2026)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86_64.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/include/clang/Options/Options.td
    M clang/include/clang/Sema/SemaX86.h
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Headers/acev1intrin.h
    M clang/lib/Sema/SemaX86.cpp
    M clang/test/CodeGen/X86/acev1.c
    M clang/test/CodeGen/X86/acev1_api.c
    M clang/test/CodeGen/X86/acev1_bsr.c
    M clang/test/CodeGen/X86/acev1_errors.c
    A clang/test/CodeGen/X86/acev1_feature_errors.c
    M clang/test/CodeGen/X86/acev1_inline_asm.c
    R clang/test/CodeGen/X86/acev1_mxfp8.c
    M clang/test/CodeGen/X86/acev1_tile_movement.c
    M clang/test/Driver/x86-target-features.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrACE.td
    M llvm/lib/Target/X86/X86LowerAMXType.cpp
    M llvm/lib/Target/X86/X86LowerTileCopy.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/X86/ACEV1/acev1-greedy-ra.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-intrinsics.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-outer-product.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-tile-basic.ll
    M llvm/test/CodeGen/X86/ACEV1/acev1-tile-spill.ll
    M llvm/test/MC/X86/ACEV1/acev1-att.s
    M llvm/test/MC/X86/ACEV1/acev1-error.s
    M llvm/test/MC/X86/ACEV1/acev1-intel.s

  Log Message:
  -----------
  [X86][ACEV1] Address review comments

- Drop the AMX_TILE dependency; under acev1 enable only the AMX
  instructions that ACE v1 actually shares.
- Namespace the ACE-invented intrinsics under llvm.x86.acev1.* and leave
  the shared AMX-AVX512 ones in the flat llvm.x86.* namespace.
- Sync the public intrinsic and builtin names with GCC, and add the
  helper macros from the ACE v1 spec.
- Tighten Sema checking of the outer-product group bits, and add driver,
  preprocessor and feature-error test coverage.
- Spell BSR0 literally in the AsmStrings with Defs/Uses instead of
  carrying it as a custom operand, which removes the bespoke handling
  from X86AsmParser and both instruction printers.
- Drop the unused BSR register class; like TMMCFG, BSR0 needs only its
  X86Reg definition and the getReservedRegs entry.
- Adopt the operand-type record naming convention, 't' for a TILE and
  'e' for a GR32 index, on both the instructions and their pseudos,
  retiring the ad-hoc _REG suffix.
- Use WriteSystem rather than WriteVecLogic for the tile outer products
  and the BSR moves.
- Pass tiles by pointer in the unit tests, and drop comments that only
  restate the code.



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